OV - exec - Loop 236

	Loop Id: 236	Module: exec	Source: advec_mom.cpp:74-75 [...]	Coverage: 2.21%

0x420934 LDR	Q26, [X5, X0]    [1]

0x420938 ADD	X14, X0, #16

0x42093c ADD	X30, X0, #32

0x420940 ADD	X28, X0, #48

0x420944 ADD	X27, X0, #64

0x420948 ADD	X26, X0, #80

0x42094c ADD	X25, X0, #96

0x420950 ADD	X24, X0, #112

0x420954 STR	Q26, [X4, X0]    [5]

0x420958 LDR	Q27, [X2, X0]    [3]

0x42095c LDR	Q7, [X3, X0]    [4]

0x420960 FADD	V16.2D, V27.2D, V26.2D

0x420964 FSUB	V17.2D, V16.2D, V7.2D

0x420968 STR	Q17, [X1, X0]    [2]

0x42096c ADD	X0, X0, #128

0x420970 LDR	Q24, [X5, X14]    [1]

0x420974 STR	Q24, [X4, X14]    [5]

0x420978 LDR	Q25, [X2, X14]    [3]

0x42097c LDR	Q18, [X3, X14]    [4]

0x420980 FADD	V19.2D, V25.2D, V24.2D

0x420984 FSUB	V20.2D, V19.2D, V18.2D

0x420988 STR	Q20, [X1, X14]    [2]

0x42098c LDR	Q21, [X5, X30]    [1]

0x420990 STR	Q21, [X4, X30]    [5]

0x420994 LDR	Q22, [X2, X30]    [3]

0x420998 LDR	Q23, [X3, X30]    [4]

0x42099c FADD	V0.2D, V22.2D, V21.2D

0x4209a0 FSUB	V30.2D, V0.2D, V23.2D

0x4209a4 STR	Q30, [X1, X30]    [2]

0x4209a8 LDR	Q31, [X5, X28]    [1]

0x4209ac STR	Q31, [X4, X28]    [5]

0x4209b0 LDR	Q1, [X2, X28]    [3]

0x4209b4 LDR	Q2, [X3, X28]    [4]

0x4209b8 FADD	V3.2D, V1.2D, V31.2D

0x4209bc FSUB	V28.2D, V3.2D, V2.2D

0x4209c0 STR	Q28, [X1, X28]    [2]

0x4209c4 LDR	Q29, [X5, X27]    [1]

0x4209c8 STR	Q29, [X4, X27]    [5]

0x4209cc LDR	Q4, [X2, X27]    [3]

0x4209d0 LDR	Q5, [X3, X27]    [4]

0x4209d4 FADD	V6.2D, V4.2D, V29.2D

0x4209d8 FSUB	V26.2D, V6.2D, V5.2D

0x4209dc STR	Q26, [X1, X27]    [2]

0x4209e0 LDR	Q27, [X5, X26]    [1]

0x4209e4 STR	Q27, [X4, X26]    [5]

0x4209e8 LDR	Q7, [X2, X26]    [3]

0x4209ec LDR	Q16, [X3, X26]    [4]

0x4209f0 FADD	V17.2D, V7.2D, V27.2D

0x4209f4 FSUB	V24.2D, V17.2D, V16.2D

0x4209f8 STR	Q24, [X1, X26]    [2]

0x4209fc LDR	Q25, [X5, X25]    [1]

0x420a00 STR	Q25, [X4, X25]    [5]

0x420a04 LDR	Q18, [X2, X25]    [3]

0x420a08 LDR	Q19, [X3, X25]    [4]

0x420a0c FADD	V20.2D, V18.2D, V25.2D

0x420a10 FSUB	V21.2D, V20.2D, V19.2D

0x420a14 STR	Q21, [X1, X25]    [2]

0x420a18 LDR	Q22, [X5, X24]    [1]

0x420a1c STR	Q22, [X4, X24]    [5]

0x420a20 LDR	Q23, [X2, X24]    [3]

0x420a24 LDR	Q0, [X3, X24]    [4]

0x420a28 FADD	V30.2D, V23.2D, V22.2D

0x420a2c FSUB	V31.2D, V30.2D, V0.2D

0x420a30 STR	Q31, [X1, X24]    [2]

0x420a34 CMP	X9, X0

0x420a38 B.NE	420934

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 74 - 75

--------------------------------------------------------------------------------

74:         post_vol(i, j) = volume(i, j);

75:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.62
Bottlenecks	P12, P13, P14,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.3]
Source	advec_mom.cpp:74-75,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.33
CQA cycles if no scalar integer	13.33
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	13.33
Front-end cycles	8.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.58
P3 cycles	1.58
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.42
P7 cycles	1.42
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	13.33
P13 cycles	13.33
P14 cycles	13.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	66.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	2.40
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	5.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.62
Bottlenecks	P12, P13, P14,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.3]
Source	advec_mom.cpp:74-75,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.33
CQA cycles if no scalar integer	13.33
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	13.33
Front-end cycles	8.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.58
P3 cycles	1.58
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.42
P7 cycles	1.42
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	13.33
P13 cycles	13.33
P14 cycles	13.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	66.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	2.40
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	5.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.3]
Source file and lines	advec_mom.cpp:74-75
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:74-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 384 bytes. The binary loop is storing 256 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	66
loop length	264
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	8.00	8.00	13.33	13.33	13.33	0.00	0.00
cycles	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	8.00	8.00	13.33	13.33	13.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.25
Data deps.	1.00
Overall L1	13.33

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

29% of peak load performance is reached (28.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (19.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420934

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q26, [X5, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X0, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X0, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X0, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, X0, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR Q26, [X4, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q27, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q7, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V16.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V17.2D, V16.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q17, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q24, [X5, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q24, [X4, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q25, [X2, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q18, [X3, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V19.2D, V25.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V20.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q20, [X1, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q21, [X5, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q21, [X4, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q22, [X2, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q23, [X3, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V0.2D, V22.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V30.2D, V0.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q30, [X1, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q31, [X5, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q31, [X4, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q1, [X2, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [X3, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V3.2D, V1.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V28.2D, V3.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q28, [X1, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q29, [X5, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q29, [X4, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q4, [X2, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q5, [X3, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V6.2D, V4.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V26.2D, V6.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q26, [X1, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q27, [X5, X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q27, [X4, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q7, [X2, X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q16, [X3, X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V17.2D, V7.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V24.2D, V17.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q24, [X1, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q25, [X5, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q25, [X4, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q18, [X2, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q19, [X3, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V20.2D, V18.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V21.2D, V20.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q21, [X1, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q22, [X5, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q22, [X4, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q23, [X2, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q0, [X3, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V30.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V31.2D, V30.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q31, [X1, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X9, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 420934 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.3]
Source file and lines	advec_mom.cpp:74-75
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:74-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 384 bytes. The binary loop is storing 256 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	66
loop length	264
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	8.00	8.00	13.33	13.33	13.33	0.00	0.00
cycles	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	8.00	8.00	13.33	13.33	13.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.25
Data deps.	1.00
Overall L1	13.33

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

29% of peak load performance is reached (28.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (19.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420934

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q26, [X5, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X0, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X0, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X0, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, X0, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR Q26, [X4, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q27, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q7, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V16.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V17.2D, V16.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q17, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q24, [X5, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q24, [X4, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q25, [X2, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q18, [X3, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V19.2D, V25.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V20.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q20, [X1, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q21, [X5, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q21, [X4, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q22, [X2, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q23, [X3, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V0.2D, V22.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V30.2D, V0.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q30, [X1, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q31, [X5, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q31, [X4, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q1, [X2, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [X3, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V3.2D, V1.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V28.2D, V3.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q28, [X1, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q29, [X5, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q29, [X4, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q4, [X2, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q5, [X3, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V6.2D, V4.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V26.2D, V6.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q26, [X1, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q27, [X5, X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q27, [X4, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q7, [X2, X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q16, [X3, X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V17.2D, V7.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V24.2D, V17.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q24, [X1, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q25, [X5, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q25, [X4, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q18, [X2, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q19, [X3, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V20.2D, V18.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V21.2D, V20.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q21, [X1, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q22, [X5, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q22, [X4, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q23, [X2, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q0, [X3, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V30.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V31.2D, V30.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR Q31, [X1, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X9, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 420934 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code