OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 3.17% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4222c0 STP	X29, X30, [SP, #912]!

0x4222c4 ADD	X29, SP, #0

0x4222c8 STP	X19, X20, [SP, #16]

0x4222cc STP	X21, X22, [SP, #32]

0x4222d0 STP	X27, X28, [SP, #80]

0x4222d4 LDP	W28, W20, [X0, #48]

0x4222d8 LDP	W21, W2, [X0, #40]

0x4222dc ADD	W20, W20, #3

0x4222e0 CMP	W28, W20

0x4222e4 B.GE	422538

0x4222e8 ADD	W21, W21, #1

0x4222ec ADD	W19, W2, #3

0x4222f0 STP	X23, X24, [SP, #48]

0x4222f4 SUB	W24, W20, W28

0x4222f8 CMP	W21, W19

0x4222fc B.GE	42254c

0x422300 SUB	W22, W19, W21

0x422304 ORR	X27, XZR, X0

0x422308 BL	403890

0x42230c MADD	W24, W24, W22, WZR

0x422310 ORR	W23, WZR, W0

0x422314 BL	4038c0

0x422318 ORR	W4, WZR, W0

0x42231c UDIV	W5, W24, W23

0x422320 MSUB	W0, W5, W23, W24

0x422324 CMP	W4, W0

0x422328 B.CC	422564

  (262) 0x42232c MADD	W13, W5, W4, W0

  (262) 0x422330 ADD	W1, W5, W13

  (262) 0x422334 CMP	W13, W1

  (262) 0x422338 B.CS	42254c

(264) 0x42233c UDIV	W7, W13, W22

(264) 0x422340 ORR	X3, XZR, #3840

(264) 0x422344 STP	X25, X26, [SP, #64]

(264) 0x422348 FMOV	D16, #-1.0000000

(264) 0x42234c FMOV	D24, #1.0000000

(264) 0x422350 MOVK	X3, #16325

(264) 0x422354 FMOV	D17, #2.0000000

(264) 0x422358 ORR	W17, WZR, W22

(264) 0x42235c LDP	X25, X26, [X27]

(264) 0x422360 LDP	X23, X24, [X27, #16]

(264) 0x422364 FMOV	D18, X3

(264) 0x422368 MSUB	W6, W7, W22, W13

(264) 0x42236c ADD	W8, W7, W28

(264) 0x422370 LDR	X3, [X27, #32]

(264) 0x422374 SBFM	X9, X8, #0, #31

(264) 0x422378 STP	W20, W21, [SP, #104]

(264) 0x42237c ADD	W30, W8, #2

(264) 0x422380 ADD	X10, X9, #1

(264) 0x422384 SUB	W7, W8, #1

(264) 0x422388 ADD	W18, W6, W21

(264) 0x42238c ORR	X11, XZR, X10

(264) 0x422390 SUB	W14, W19, W18

(264) 0x422394 ADD	W27, W9, #1

(264) 0x422398 CMP	W5, W14

(264) 0x42239c CSEL	W12, W5, W14, #9

(264) 0x4223a0 ADD	W14, W13, W12

(264) 0x4223a4 CMP	W13, W14

(264) 0x4223a8 B.CS	422510

  (265) 0x4223ac LDR	X15, [X24]

  (265) 0x4223b0 SBFM	X0, X18, #0, #31

  (265) 0x4223b4 SUB	W13, W12, #1

  (265) 0x4223b8 ADD	X6, X0, #1

  (265) 0x4223bc LDR	X28, [X26]

  (265) 0x4223c0 ADD	X13, X6, X13

  (265) 0x4223c4 LDR	X19, [X3, #8]

  (265) 0x4223c8 MADD	X2, X9, X15, XZR

  (265) 0x4223cc LDR	X16, [X24, #16]

  (265) 0x4223d0 MADD	X4, X9, X28, XZR

  (265) 0x4223d4 LDR	X20, [X26, #16]

  (265) 0x4223d8 ADD	X22, X19, X9,LSL #3

  (265) 0x4223dc LDR	X18, [X23]

  (265) 0x4223e0 ADD	X15, X16, X2,LSL #3

  (265) 0x4223e4 LDR	X12, [X25]

  (265) 0x4223e8 ADD	X16, X20, X4,LSL #3

  (265) 0x4223ec LDR	X21, [X23, #16]

  (265) 0x4223f0 LDR	X8, [X25, #16]

  (265) 0x4223f4 B	4223fc

    (263) 0x4223f8 ADD	X6, X6, #1

    (263) 0x4223fc LDR	D30, [X16, X0,LSL #3]

    (263) 0x422400 SBFM	X2, X7, #0, #31

    (263) 0x422404 ORR	X5, XZR, X11

    (263) 0x422408 ORR	X4, XZR, X9

    (263) 0x42240c ORR	W20, WZR, W7

    (263) 0x422410 FCMPE	D30, #0

    (263) 0x422414 B.GE	422428

    (263) 0x422418 SBFM	X2, X30, #0, #31

    (263) 0x42241c ORR	X5, XZR, X9

    (263) 0x422420 ORR	X4, XZR, X11

    (263) 0x422424 ORR	W20, WZR, W27

    (263) 0x422428 MADD	X28, X18, X4, X0

    (263) 0x42242c FABS	D27, D30

    (263) 0x422430 MADD	X5, X12, X5, X0

    (263) 0x422434 MADD	X2, X2, X12, X0

    (263) 0x422438 MADD	X4, X12, X4, X0

    (263) 0x42243c LDR	D29, [X8, X5,LSL #3]

    (263) 0x422440 LDR	D28, [X8, X4,LSL #3]

    (263) 0x422444 LDR	D31, [X8, X2,LSL #3]

    (263) 0x422448 FSUB	D1, D29, S28

    (263) 0x42244c FSUB	D0, D28, S31

    (263) 0x422450 FABS	D26, D1

    (263) 0x422454 FMUL	D2, D0, D1

    (263) 0x422458 FABS	D25, D0

    (263) 0x42245c FMINNM	D22, D25, D26

    (263) 0x422460 FCMPE	D2, #0

    (263) 0x422464 B.LS	4224b4

    (263) 0x422468 LDR	D3, [X21, X28,LSL #3]

    (263) 0x42246c FCMPE	D1, #0

    (263) 0x422470 LDR	D23, [X22]

    (263) 0x422474 LDR	D19, [X19, X20,SXTW #3]

    (263) 0x422478 FDIV	D4, D27, D3

    (263) 0x42247c FCSEL	D21, D16, D24, #9

    (263) 0x422480 FMUL	D0, D23, D18

    (263) 0x422484 FADD	D5, D4, D24

    (263) 0x422488 FSUB	D6, D17, S4

    (263) 0x42248c FSUB	D7, D24, S4

    (263) 0x422490 FMUL	D20, D5, D25

    (263) 0x422494 FMUL	D27, D6, D26

    (263) 0x422498 FDIV	D29, D20, D19

    (263) 0x42249c FDIV	D31, D27, D23

    (263) 0x4224a0 FADD	D1, D29, D31

    (263) 0x4224a4 FMUL	D25, D1, D0

    (263) 0x4224a8 FMINNM	D26, D25, D22

    (263) 0x4224ac FMUL	D22, D26, D7

    (263) 0x4224b0 FMADD	D28, D21, D22, D28

    (263) 0x4224b4 FMUL	D30, D30, D28

    (263) 0x4224b8 STR	D30, [X15, X0,LSL #3]

    (263) 0x4224bc ORR	X0, XZR, X6

    (263) 0x4224c0 CMP	X6, X13

    (263) 0x4224c4 B.NE	4223f8

  (265) 0x4224c8 LDR	W6, [SP, #104]

  (265) 0x4224cc ADD	W30, W30, #1

  (265) 0x4224d0 ADD	W7, W7, #1

  (265) 0x4224d4 ADD	X11, X11, #1

  (265) 0x4224d8 ORR	X9, XZR, X10

  (265) 0x4224dc CMP	W6, W10

  (265) 0x4224e0 B.LE	422530

  (265) 0x4224e4 SUB	W5, W1, W14

  (265) 0x4224e8 ORR	W13, WZR, W14

  (265) 0x4224ec LDR	W18, [SP, #108]

  (265) 0x4224f0 ORR	W14, WZR, W17

  (265) 0x4224f4 ADD	X10, X10, #1

  (265) 0x4224f8 CMP	W5, W14

  (265) 0x4224fc CSEL	W12, W5, W14, #9

  (265) 0x422500 ADD	W14, W13, W12

  (265) 0x422504 ADD	W27, W9, #1

  (265) 0x422508 CMP	W13, W14

  (265) 0x42250c B.CC	4223ac

  (266) 0x422510 LDR	W6, [SP, #104]

  (266) 0x422514 ORR	W14, WZR, W13

  (266) 0x422518 ADD	W30, W30, #1

  (266) 0x42251c ADD	W7, W7, #1

  (266) 0x422520 ADD	X11, X11, #1

  (266) 0x422524 ORR	X9, XZR, X10

  (266) 0x422528 CMP	W6, W10

  (266) 0x42252c B.GT	4224e4

(264) 0x422530 LDP	X23, X24, [SP, #48]

(264) 0x422534 LDP	X25, X26, [SP, #64]

(264) 0x422538 LDP	X19, X20, [SP, #16]

(264) 0x42253c LDP	X21, X22, [SP, #32]

(264) 0x422540 LDP	X27, X28, [SP, #80]

(264) 0x422544 LDP	X29, X30, [SP], #112

(264) 0x422548 RET

  (262) 0x42254c LDP	X23, X24, [SP, #48]

  (262) 0x422550 LDP	X19, X20, [SP, #16]

  (262) 0x422554 LDP	X21, X22, [SP, #32]

  (262) 0x422558 LDP	X27, X28, [SP, #80]

  (262) 0x42255c LDP	X29, X30, [SP], #112

  (262) 0x422560 RET

  (262) 0x422564 ADD	W5, W5, #1

  (262) 0x422568 MOVZ	W0, #0

  (262) 0x42256c B	42232c

Coverage (%)	Name	Source Location	Module
►98.93+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.38
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4222c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W28, W20, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W21, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W20, W20, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W28, W20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 422538 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W21, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W24, W20, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W21, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42254c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W22, W19, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W24, W24, W22, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W23, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W4, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UDIV W5, W24, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W5, W23, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W4, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 422564 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.38
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4222c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W28, W20, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W21, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W20, W20, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W28, W20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 422538 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W21, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W24, W20, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W21, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42254c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W22, W19, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W24, W24, W22, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W23, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W4, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UDIV W5, W24, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W5, W23, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W4, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 422564 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.17	2.41
▼Loop 264 - advec_mom.cpp:180-211 - exec–	0.00	0.00
▼Loop 265 - advec_mom.cpp:182-211 - exec–	0.01	0.01
○Loop 263 - advec_mom.cpp:186-211 - exec	3.17	2.39
○Loop 266 - advec_mom.cpp:182-182 - exec	0.00	0.01
○Loop 262 - advec_mom.cpp:180-182 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code