OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 3.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x422040 STP	X29, X30, [SP, #944]!

0x422044 ADD	X29, SP, #0

0x422048 STP	X19, X20, [SP, #16]

0x42204c STP	X25, X26, [SP, #64]

0x422050 LDP	W25, W19, [X0, #48]

0x422054 LDP	W20, W3, [X0, #40]

0x422058 ADD	W25, W25, #1

0x42205c ADD	W19, W19, #3

0x422060 CMP	W25, W19

0x422064 B.GE	422294

0x422068 STP	X21, X22, [SP, #32]

0x42206c ADD	W22, W3, #3

0x422070 SUB	W26, W19, W25

0x422074 CMP	W20, W22

0x422078 B.GE	4222b0

0x42207c SUB	W21, W22, W20

0x422080 STP	X23, X24, [SP, #48]

0x422084 ORR	X23, XZR, X0

0x422088 MADD	W26, W26, W21, WZR

0x42208c BL	403890

0x422090 ORR	W24, WZR, W0

0x422094 BL	4038c0

0x422098 UDIV	W1, W26, W24

0x42209c ORR	W2, WZR, W0

0x4220a0 MSUB	W0, W1, W24, W26

0x4220a4 CMP	W2, W0

0x4220a8 B.CC	4222a4

(258) 0x4220ac MADD	W26, W1, W2, W0

(258) 0x4220b0 ADD	W18, W1, W26

(258) 0x4220b4 CMP	W26, W18

(258) 0x4220b8 B.CS	42228c

(258) 0x4220bc UDIV	W4, W26, W21

(258) 0x4220c0 ORR	X5, XZR, #3840

(258) 0x4220c4 LDR	X30, [X23, #32]

(258) 0x4220c8 FMOV	D16, #-1.0000000

(258) 0x4220cc FMOV	D24, #1.0000000

(258) 0x4220d0 MOVK	X5, #16325

(258) 0x4220d4 LDP	X16, X17, [X23]

(258) 0x4220d8 FMOV	D17, #2.0000000

(258) 0x4220dc FMOV	D18, X5

(258) 0x4220e0 LDP	X14, X15, [X23, #16]

(258) 0x4220e4 MSUB	W6, W4, W21, W26

(258) 0x4220e8 ADD	W7, W4, W25

(258) 0x4220ec SBFM	X12, X7, #0, #31

(258) 0x4220f0 ADD	W7, W6, W20

(258) 0x4220f4 SUB	W13, W22, W7

(258) 0x4220f8 CMP	W1, W13

(258) 0x4220fc CSEL	W8, W1, W13, #9

(258) 0x422100 ADD	W13, W26, W8

(258) 0x422104 CMP	W26, W13

(258) 0x422108 B.CS	42227c

  (260) 0x42210c LDR	X22, [X15]

  (260) 0x422110 SUB	W10, W8, #1

  (260) 0x422114 SBFM	X9, X7, #0, #31

  (260) 0x422118 ADD	X11, X9, #2

  (260) 0x42211c ADD	W25, W7, #1

  (260) 0x422120 LDR	X8, [X17]

  (260) 0x422124 ADD	X26, X11, X10

  (260) 0x422128 SBFM	X0, X25, #0, #31

  (260) 0x42212c LDR	X3, [X14]

  (260) 0x422130 MADD	X2, X12, X22, XZR

  (260) 0x422134 LDR	X24, [X15, #16]

  (260) 0x422138 MADD	X25, X12, X8, XZR

  (260) 0x42213c LDR	X10, [X17, #16]

  (260) 0x422140 UBFM	X1, X2, #61, #60

  (260) 0x422144 MADD	X7, X12, X3, XZR

  (260) 0x422148 SUB	X4, X1, #8

  (260) 0x42214c UBFM	X3, X25, #61, #60

  (260) 0x422150 LDR	X6, [X16]

  (260) 0x422154 SUB	X22, X3, #8

  (260) 0x422158 ADD	X9, X24, X4

  (260) 0x42215c LDR	X23, [X14, #16]

  (260) 0x422160 ADD	X4, X10, X22

  (260) 0x422164 LDR	X10, [X30, #8]

  (260) 0x422168 MADD	X11, X12, X6, XZR

  (260) 0x42216c LDR	X5, [X16, #16]

  (260) 0x422170 SUB	X24, X10, #8

  (260) 0x422174 HINT	#0

  (260) 0x422178 HINT	#0

  (260) 0x42217c HINT	#0

    (259) 0x422180 LDR	D30, [X4, X0,LSL #3]

    (259) 0x422184 SUB	W2, W0, #2

    (259) 0x422188 SUB	X1, X0, #1

    (259) 0x42218c ORR	X25, XZR, X0

    (259) 0x422190 ORR	W6, WZR, W2

    (259) 0x422194 FCMPE	D30, #0

    (259) 0x422198 B.GE	4221ac

    (259) 0x42219c ORR	X25, XZR, X1

    (259) 0x4221a0 ORR	W6, WZR, W0

    (259) 0x4221a4 ADD	W2, W0, #1

    (259) 0x4221a8 ORR	X1, XZR, X0

    (259) 0x4221ac ADD	X3, X11, X25

    (259) 0x4221b0 ADD	X25, X11, X1

    (259) 0x4221b4 ADD	X22, X11, W2,SXTW

    (259) 0x4221b8 LDR	D31, [X5, X22,LSL #3]

    (259) 0x4221bc FABS	D27, D30

    (259) 0x4221c0 ADD	X8, X7, X1

    (259) 0x4221c4 LDR	D28, [X5, X25,LSL #3]

    (259) 0x4221c8 LDR	D29, [X5, X3,LSL #3]

    (259) 0x4221cc FSUB	D0, D28, S31

    (259) 0x4221d0 FSUB	D1, D29, S28

    (259) 0x4221d4 FABS	D25, D0

    (259) 0x4221d8 FMUL	D2, D0, D1

    (259) 0x4221dc FABS	D26, D1

    (259) 0x4221e0 FMINNM	D22, D25, D26

    (259) 0x4221e4 FCMPE	D2, #0

    (259) 0x4221e8 B.LS	422238

    (259) 0x4221ec LDR	D3, [X23, X8,LSL #3]

    (259) 0x4221f0 FCMPE	D1, #0

    (259) 0x4221f4 LDR	D23, [X24, X0,LSL #3]

    (259) 0x4221f8 LDR	D19, [X10, X6,SXTW #3]

    (259) 0x4221fc FDIV	D4, D27, D3

    (259) 0x422200 FCSEL	D21, D16, D24, #9

    (259) 0x422204 FMUL	D20, D23, D18

    (259) 0x422208 FADD	D5, D4, D24

    (259) 0x42220c FSUB	D6, D17, S4

    (259) 0x422210 FSUB	D7, D24, S4

    (259) 0x422214 FMUL	D31, D5, D25

    (259) 0x422218 FMUL	D27, D6, D26

    (259) 0x42221c FDIV	D29, D31, D19

    (259) 0x422220 FDIV	D0, D27, D23

    (259) 0x422224 FADD	D1, D29, D0

    (259) 0x422228 FMUL	D25, D1, D20

    (259) 0x42222c FMINNM	D26, D25, D22

    (259) 0x422230 FMUL	D22, D26, D7

    (259) 0x422234 FMADD	D28, D21, D22, D28

    (259) 0x422238 FMUL	D30, D30, D28

    (259) 0x42223c STR	D30, [X9, X0,LSL #3]

    (259) 0x422240 ADD	X0, X0, #1

    (259) 0x422244 CMP	X0, X26

    (259) 0x422248 B.NE	422180

  (260) 0x42224c ADD	X12, X12, #1

  (260) 0x422250 CMP	W19, W12

  (260) 0x422254 B.LE	42228c

  (260) 0x422258 SUB	W1, W18, W13

  (260) 0x42225c ORR	W26, WZR, W13

  (260) 0x422260 ORR	W13, WZR, W21

  (260) 0x422264 ORR	W7, WZR, W20

  (260) 0x422268 CMP	W1, W13

  (260) 0x42226c CSEL	W8, W1, W13, #9

  (260) 0x422270 ADD	W13, W26, W8

  (260) 0x422274 CMP	W26, W13

  (260) 0x422278 B.CC	42210c

  (261) 0x42227c ADD	X12, X12, #1

  (261) 0x422280 ORR	W13, WZR, W26

  (261) 0x422284 CMP	W19, W12

  (261) 0x422288 B.GT	422258

(258) 0x42228c LDP	X21, X22, [SP, #32]

(258) 0x422290 LDP	X23, X24, [SP, #48]

(258) 0x422294 LDP	X19, X20, [SP, #16]

(258) 0x422298 LDP	X25, X26, [SP, #64]

(258) 0x42229c LDP	X29, X30, [SP], #80

(258) 0x4222a0 RET

(258) 0x4222a4 ADD	W1, W1, #1

(258) 0x4222a8 MOVZ	W0, #0

(258) 0x4222ac B	4220ac

0x4222b0 LDP	X21, X22, [SP, #32]

0x4222b4 B	422294

0x4222b8 HINT	#0

0x4222bc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.87+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

2% of peak load performance is reached (2.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 422294 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W3, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4222b0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MSUB W0, W1, W24, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 4222a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 422294 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

2% of peak load performance is reached (2.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 422294 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W3, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4222b0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MSUB W0, W1, W24, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 4222a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 422294 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.01	2.28
▼Loop 258 - advec_mom.cpp:108-139 - exec–	0.00	0.00
▼Loop 260 - advec_mom.cpp:110-139 - exec–	0.00	0.01
○Loop 259 - advec_mom.cpp:114-139 - exec	3.01	2.27
○Loop 261 - advec_mom.cpp:110-110 - exec	0.00	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code