OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:218-221 [...]	Coverage (incl. loops): 4.86% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 218 - 221

--------------------------------------------------------------------------------

218: #pragma omp parallel for simd collapse(2)

219:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

220:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

221:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i + 0, j - 1) - mom_flux(i, j)) / node_mass_post(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x421cc4 STP	X29, X30, [SP, #912]!

0x421cc8 ADD	X29, SP, #0

0x421ccc STP	X19, X20, [SP, #16]

0x421cd0 ORR	X20, XZR, X0

0x421cd4 STP	X21, X22, [SP, #32]

0x421cd8 LDP	W22, W1, [X0, #40]

0x421cdc LDP	W0, W19, [X0, #32]

0x421ce0 ADD	W2, W1, #3

0x421ce4 ADD	W22, W22, #1

0x421ce8 ADD	W3, W0, #1

0x421cec STP	W2, W3, [SP, #96]

0x421cf0 CMP	W22, W2

0x421cf4 B.GE	422004

0x421cf8 STP	X23, X24, [SP, #48]

0x421cfc ADD	W24, W19, #3

0x421d00 SUB	W23, W2, W22

0x421d04 CMP	W3, W24

0x421d08 B.GE	422000

0x421d0c SUB	W4, W24, W3

0x421d10 MADD	W19, W23, W4, WZR

0x421d14 STR	W4, [SP, #104]

0x421d18 BL	403890

0x421d1c ORR	W21, WZR, W0

0x421d20 BL	4038c0

0x421d24 UDIV	W6, W19, W21

0x421d28 ORR	W5, WZR, W0

0x421d2c MSUB	W7, W6, W21, W19

0x421d30 CMP	W0, W7

0x421d34 B.CC	422030

  (255) 0x421d38 MADD	W16, W6, W5, W7

  (255) 0x421d3c ADD	W8, W6, W16

  (255) 0x421d40 STR	W8, [SP, #108]

  (255) 0x421d44 CMP	W16, W8

  (255) 0x421d48 B.CS	422000

  (255) 0x421d4c LDR	W9, [SP, #104]

  (255) 0x421d50 STP	X25, X26, [SP, #64]

  (255) 0x421d54 LDR	W13, [SP, #100]

  (255) 0x421d58 UDIV	W10, W16, W9

  (255) 0x421d5c STP	X27, X28, [SP, #80]

  (255) 0x421d60 LDP	X27, X28, [X20]

  (255) 0x421d64 LDP	X25, X26, [X20, #16]

  (255) 0x421d68 MSUB	W11, W10, W9, W16

  (255) 0x421d6c ADD	W12, W10, W22

  (255) 0x421d70 SBFM	X5, X12, #0, #31

  (255) 0x421d74 ADD	W4, W11, W13

  (255) 0x421d78 SUB	W24, W24, W4

  (255) 0x421d7c HINT	#0

    (256) 0x421d80 CMP	W6, W24

    (256) 0x421d84 CSEL	W3, W6, W24, #9

    (256) 0x421d88 ADD	W23, W16, W3

    (256) 0x421d8c CMP	W16, W23

    (256) 0x421d90 B.CS	421fdc

    (256) 0x421d94 LDR	X18, [X26]

    (256) 0x421d98 SUB	W14, W5, #1

    (256) 0x421d9c SBFM	X17, X14, #0, #31

    (256) 0x421da0 LDR	X15, [X25]

    (256) 0x421da4 LDR	X20, [X27]

    (256) 0x421da8 MADD	X12, X17, X18, XZR

    (256) 0x421dac LDR	X1, [X28]

    (256) 0x421db0 MADD	X14, X18, X5, XZR

    (256) 0x421db4 MADD	X15, X5, X15, XZR

    (256) 0x421db8 LDR	X30, [X25, #16]

    (256) 0x421dbc MADD	X11, X5, X20, XZR

    (256) 0x421dc0 LDR	X16, [X26, #16]

    (256) 0x421dc4 MADD	X17, X5, X1, XZR

    (256) 0x421dc8 LDR	X22, [X27, #16]

    (256) 0x421dcc LDR	X24, [X28, #16]

    (256) 0x421dd0 CMP	W3, #1

    (256) 0x421dd4 B.EQ	421f98

    (256) 0x421dd8 UBFM	W19, W3, #1, #31

    (256) 0x421ddc SBFM	X2, X4, #0, #31

    (256) 0x421de0 UBFM	X13, X19, #60, #59

    (256) 0x421de4 ADD	X6, X11, X2

    (256) 0x421de8 SUB	X21, X13, #16

    (256) 0x421dec ADD	X20, X15, X2

    (256) 0x421df0 ADD	X1, X22, X6,LSL #3

    (256) 0x421df4 UBFM	X7, X21, #4, #63

    (256) 0x421df8 ADD	X19, X12, X2

    (256) 0x421dfc ADD	X8, X30, X20,LSL #3

    (256) 0x421e00 ADD	X9, X7, #1

    (256) 0x421e04 ADD	X21, X14, X2

    (256) 0x421e08 ADD	X7, X16, X19,LSL #3

    (256) 0x421e0c ADD	X2, X17, X2

    (256) 0x421e10 ANDS	X10, X9, #4160

    (256) 0x421e14 ADD	X9, X16, X21,LSL #3

    (256) 0x421e18 UBFM	X18, X6, #61, #60

    (256) 0x421e1c MOVZ	X0, #0

    (256) 0x421e20 ADD	X6, X24, X2,LSL #3

    (256) 0x421e24 UBFM	X20, X20, #61, #60

    (256) 0x421e28 UBFM	X19, X19, #61, #60

    (256) 0x421e2c UBFM	X21, X21, #61, #60

    (256) 0x421e30 UBFM	X2, X2, #61, #60

    (256) 0x421e34 B.EQ	421ed4

    (256) 0x421e38 CMP	X10, #1

    (256) 0x421e3c B.EQ	421ea0

    (256) 0x421e40 CMP	X10, #2

    (256) 0x421e44 B.EQ	421e74

    (256) 0x421e48 LDR	Q28, [X16, X21]

    (256) 0x421e4c MOVZ	X0, #16

    (256) 0x421e50 LDR	Q30, [X22, X18]

    (256) 0x421e54 LDR	Q0, [X30, X20]

    (256) 0x421e58 FNEG	V1.2D, V28.2D

    (256) 0x421e5c LDR	Q31, [X16, X19]

    (256) 0x421e60 LDR	Q29, [X24, X2]

    (256) 0x421e64 FMLA	V1.2D, V30.2D, V0.2D

    (256) 0x421e68 FADD	V2.2D, V31.2D, V1.2D

    (256) 0x421e6c FDIV	V3.2D, V2.2D, V29.2D

    (256) 0x421e70 STR	Q3, [X22, X18]

    (256) 0x421e74 LDR	Q24, [X9, X0]

    (256) 0x421e78 LDR	Q26, [X1, X0]

    (256) 0x421e7c LDR	Q4, [X8, X0]

    (256) 0x421e80 FNEG	V5.2D, V24.2D

    (256) 0x421e84 LDR	Q27, [X7, X0]

    (256) 0x421e88 LDR	Q25, [X6, X0]

    (256) 0x421e8c FMLA	V5.2D, V26.2D, V4.2D

    (256) 0x421e90 FADD	V6.2D, V27.2D, V5.2D

    (256) 0x421e94 FDIV	V7.2D, V6.2D, V25.2D

    (256) 0x421e98 STR	Q7, [X1, X0]

    (256) 0x421e9c ADD	X0, X0, #16

    (256) 0x421ea0 LDR	Q20, [X9, X0]

    (256) 0x421ea4 LDR	Q22, [X1, X0]

    (256) 0x421ea8 LDR	Q16, [X8, X0]

    (256) 0x421eac FNEG	V17.2D, V20.2D

    (256) 0x421eb0 LDR	Q23, [X7, X0]

    (256) 0x421eb4 LDR	Q21, [X6, X0]

    (256) 0x421eb8 FMLA	V17.2D, V22.2D, V16.2D

    (256) 0x421ebc FADD	V18.2D, V23.2D, V17.2D

    (256) 0x421ec0 FDIV	V19.2D, V18.2D, V21.2D

    (256) 0x421ec4 STR	Q19, [X1, X0]

    (256) 0x421ec8 ADD	X0, X0, #16

    (256) 0x421ecc CMP	X13, X0

    (256) 0x421ed0 B.EQ	421f8c

      (257) 0x421ed4 LDR	Q28, [X9, X0]

      (257) 0x421ed8 ADD	X20, X0, #16

      (257) 0x421edc ADD	X18, X0, #32

      (257) 0x421ee0 ADD	X10, X0, #48

      (257) 0x421ee4 LDR	Q30, [X1, X0]

      (257) 0x421ee8 LDR	Q0, [X8, X0]

      (257) 0x421eec FNEG	V1.2D, V28.2D

      (257) 0x421ef0 LDR	Q31, [X7, X0]

      (257) 0x421ef4 LDR	Q29, [X6, X0]

      (257) 0x421ef8 FMLA	V1.2D, V30.2D, V0.2D

      (257) 0x421efc FADD	V2.2D, V31.2D, V1.2D

      (257) 0x421f00 FDIV	V3.2D, V2.2D, V29.2D

      (257) 0x421f04 STR	Q3, [X1, X0]

      (257) 0x421f08 ADD	X0, X0, #64

      (257) 0x421f0c LDR	Q24, [X9, X20]

      (257) 0x421f10 LDR	Q26, [X1, X20]

      (257) 0x421f14 LDR	Q4, [X8, X20]

      (257) 0x421f18 FNEG	V5.2D, V24.2D

      (257) 0x421f1c LDR	Q27, [X7, X20]

      (257) 0x421f20 LDR	Q25, [X6, X20]

      (257) 0x421f24 FMLA	V5.2D, V26.2D, V4.2D

      (257) 0x421f28 FADD	V6.2D, V27.2D, V5.2D

      (257) 0x421f2c FDIV	V7.2D, V6.2D, V25.2D

      (257) 0x421f30 STR	Q7, [X1, X20]

      (257) 0x421f34 LDR	Q20, [X9, X18]

      (257) 0x421f38 LDR	Q22, [X1, X18]

      (257) 0x421f3c LDR	Q16, [X8, X18]

      (257) 0x421f40 FNEG	V17.2D, V20.2D

      (257) 0x421f44 LDR	Q23, [X7, X18]

      (257) 0x421f48 LDR	Q21, [X6, X18]

      (257) 0x421f4c FMLA	V17.2D, V22.2D, V16.2D

      (257) 0x421f50 FADD	V18.2D, V23.2D, V17.2D

      (257) 0x421f54 FDIV	V19.2D, V18.2D, V21.2D

      (257) 0x421f58 STR	Q19, [X1, X18]

      (257) 0x421f5c LDR	Q28, [X9, X10]

      (257) 0x421f60 LDR	Q30, [X1, X10]

      (257) 0x421f64 LDR	Q0, [X8, X10]

      (257) 0x421f68 FNEG	V1.2D, V28.2D

      (257) 0x421f6c LDR	Q31, [X7, X10]

      (257) 0x421f70 LDR	Q29, [X6, X10]

      (257) 0x421f74 FMLA	V1.2D, V30.2D, V0.2D

      (257) 0x421f78 FADD	V2.2D, V31.2D, V1.2D

      (257) 0x421f7c FDIV	V3.2D, V2.2D, V29.2D

      (257) 0x421f80 STR	Q3, [X1, X10]

      (257) 0x421f84 CMP	X13, X0

      (257) 0x421f88 B.NE	421ed4

    (256) 0x421f8c TBZ	W3, #0, 421fd8

    (256) 0x421f90 AND	W3, W3, #1951

    (256) 0x421f94 ADD	W4, W4, W3

    (256) 0x421f98 SBFM	X13, X4, #0, #31

    (256) 0x421f9c ADD	X11, X11, X13

    (256) 0x421fa0 ADD	X15, X15, X13

    (256) 0x421fa4 UBFM	X1, X11, #61, #60

    (256) 0x421fa8 ADD	X14, X14, X13

    (256) 0x421fac LDR	D24, [X30, X15,LSL #3]

    (256) 0x421fb0 ADD	X30, X12, X13

    (256) 0x421fb4 ADD	X12, X17, X13

    (256) 0x421fb8 LDR	D26, [X22, X1]

    (256) 0x421fbc LDR	D4, [X16, X14,LSL #3]

    (256) 0x421fc0 LDR	D5, [X16, X30,LSL #3]

    (256) 0x421fc4 LDR	D27, [X24, X12,LSL #3]

    (256) 0x421fc8 FNMSUB	D25, D24, D26, D4

    (256) 0x421fcc FADD	D6, D25, D5

    (256) 0x421fd0 FDIV	D7, D6, D27

    (256) 0x421fd4 STR	D7, [X22, X1]

    (256) 0x421fd8 ORR	W16, WZR, W23

    (256) 0x421fdc LDR	W23, [SP, #96]

    (256) 0x421fe0 ADD	X5, X5, #1

    (256) 0x421fe4 CMP	W23, W5

    (256) 0x421fe8 B.LE	422014

    (256) 0x421fec LDR	W22, [SP, #108]

    (256) 0x421ff0 LDR	W4, [SP, #100]

    (256) 0x421ff4 LDR	W24, [SP, #104]

    (256) 0x421ff8 SUB	W6, W22, W16

    (256) 0x421ffc B	421d80

(254) 0x422000 LDP	X23, X24, [SP, #48]

(254) 0x422004 LDP	X19, X20, [SP, #16]

(254) 0x422008 LDP	X21, X22, [SP, #32]

(254) 0x42200c LDP	X29, X30, [SP], #112

(254) 0x422010 RET

  (255) 0x422014 LDP	X23, X24, [SP, #48]

  (255) 0x422018 LDP	X25, X26, [SP, #64]

  (255) 0x42201c LDP	X27, X28, [SP, #80]

  (255) 0x422020 LDP	X19, X20, [SP, #16]

  (255) 0x422024 LDP	X21, X22, [SP, #32]

  (255) 0x422028 LDP	X29, X30, [SP], #112

  (255) 0x42202c RET

  (255) 0x422030 ADD	W6, W6, #1

  (255) 0x422034 MOVZ	W7, #0

  (255) 0x422038 B	421d38

0x42203c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:218-221
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:218-221
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421cc4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W19, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W3, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 422004 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W24, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W3, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 422000 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W4, W24, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W19, W23, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W7, W6, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 422030 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:218-221
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:218-221
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421cc4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W19, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W3, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 422004 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W24, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W3, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 422000 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W4, W24, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W19, W23, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W7, W6, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 422030 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.86	3.69
▼Loop 254 - advec_mom.cpp:218-221 - exec–	0.00	0.00
▼Loop 255 - advec_mom.cpp:218-221 - exec–	0.00	0.00
▼Loop 256 - advec_mom.cpp:220-221 - exec–	0.01	0.01
○Loop 257 - advec_mom.cpp:221-221 - exec	4.86	3.66

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code