OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:157-160 [...]	Coverage (incl. loops): 1.17% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 157 - 160

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

159:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

160:           node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4219c4 STP	X29, X30, [SP, #944]!

0x4219c8 ADD	X29, SP, #0

0x4219cc STP	X19, X20, [SP, #16]

0x4219d0 STP	X23, X24, [SP, #48]

0x4219d4 STP	X25, X26, [SP, #64]

0x4219d8 LDP	W25, W19, [X0, #24]

0x4219dc LDP	W20, W23, [X0, #16]

0x4219e0 SUB	W25, W25, #1

0x4219e4 ADD	W19, W19, #4

0x4219e8 CMP	W25, W19

0x4219ec B.GE	421ca4

0x4219f0 ADD	W20, W20, #1

0x4219f4 ADD	W23, W23, #3

0x4219f8 SUB	W26, W19, W25

0x4219fc CMP	W20, W23

0x421a00 B.GE	421ca4

0x421a04 STP	X21, X22, [SP, #32]

0x421a08 SUB	W21, W23, W20

0x421a0c ORR	X24, XZR, X0

0x421a10 MADD	W26, W26, W21, WZR

0x421a14 BL	403890

0x421a18 ORR	W22, WZR, W0

0x421a1c BL	4038c0

0x421a20 UDIV	W1, W26, W22

0x421a24 ORR	W2, WZR, W0

0x421a28 MSUB	W3, W1, W22, W26

0x421a2c CMP	W0, W3

0x421a30 B.CC	421cb8

(251) 0x421a34 MADD	W11, W1, W2, W3

(251) 0x421a38 ADD	W22, W1, W11

(251) 0x421a3c CMP	W11, W22

(251) 0x421a40 B.CS	421ca0

(251) 0x421a44 UDIV	W0, W11, W21

(251) 0x421a48 LDP	X18, X30, [X24]

(251) 0x421a4c FMOV	D31, #0.2500000

(251) 0x421a50 FMOV	V30.2D, #0.2500000

(251) 0x421a54 MSUB	W5, W0, W21, W11

(251) 0x421a58 ADD	W4, W0, W25

(251) 0x421a5c SBFM	X14, X4, #0, #31

(251) 0x421a60 ADD	W5, W5, W20

(251) 0x421a64 SUB	W17, W23, W5

  (252) 0x421a68 CMP	W1, W17

  (252) 0x421a6c CSEL	W1, W1, W17, #9

  (252) 0x421a70 ADD	W17, W11, W1

  (252) 0x421a74 CMP	W11, W17

  (252) 0x421a78 B.CS	421c84

  (252) 0x421a7c LDR	X12, [X18]

  (252) 0x421a80 LDR	X16, [X30]

  (252) 0x421a84 LDR	X11, [X18, #16]

  (252) 0x421a88 MADD	X15, X12, X14, XZR

  (252) 0x421a8c LDR	X23, [X30, #16]

  (252) 0x421a90 MADD	X16, X14, X16, XZR

  (252) 0x421a94 ADD	X12, X12, X15

  (252) 0x421a98 CMP	W1, #1

  (252) 0x421a9c B.EQ	421c3c

  (252) 0x421aa0 UBFM	W13, W1, #1, #31

  (252) 0x421aa4 SBFM	X6, X5, #0, #31

  (252) 0x421aa8 UBFM	X13, X13, #60, #59

  (252) 0x421aac ADD	X7, X15, X6

  (252) 0x421ab0 SUB	X8, X13, #16

  (252) 0x421ab4 ADD	X9, X12, X6

  (252) 0x421ab8 UBFM	X10, X8, #4, #63

  (252) 0x421abc UBFM	X24, X7, #61, #60

  (252) 0x421ac0 ADD	X25, X10, #1

  (252) 0x421ac4 UBFM	X4, X9, #61, #60

  (252) 0x421ac8 ADD	X2, X16, X6

  (252) 0x421acc ANDS	X3, X25, #4160

  (252) 0x421ad0 SUB	X26, X24, #8

  (252) 0x421ad4 SUB	X25, X4, #8

  (252) 0x421ad8 ADD	X6, X23, X2,LSL #3

  (252) 0x421adc MOVZ	X0, #0

  (252) 0x421ae0 ADD	X10, X11, X26

  (252) 0x421ae4 ADD	X8, X11, X25

  (252) 0x421ae8 ADD	X9, X11, X24

  (252) 0x421aec ADD	X7, X11, X4

  (252) 0x421af0 UBFM	X2, X2, #61, #60

  (252) 0x421af4 B.EQ	421b88

  (252) 0x421af8 CMP	X3, #1

  (252) 0x421afc B.EQ	421b58

  (252) 0x421b00 CMP	X3, #2

  (252) 0x421b04 B.EQ	421b30

  (252) 0x421b08 LDR	Q6, [X11, X26]

  (252) 0x421b0c MOVZ	X0, #16

  (252) 0x421b10 LDR	Q5, [X11, X24]

  (252) 0x421b14 LDR	Q4, [X11, X25]

  (252) 0x421b18 LDR	Q3, [X11, X4]

  (252) 0x421b1c FADD	V0.2D, V6.2D, V5.2D

  (252) 0x421b20 FADD	V1.2D, V4.2D, V3.2D

  (252) 0x421b24 FADD	V2.2D, V0.2D, V1.2D

  (252) 0x421b28 FMUL	V7.2D, V2.2D, V30.2D

  (252) 0x421b2c STR	Q7, [X23, X2]

  (252) 0x421b30 LDR	Q16, [X10, X0]

  (252) 0x421b34 LDR	Q17, [X9, X0]

  (252) 0x421b38 LDR	Q18, [X8, X0]

  (252) 0x421b3c LDR	Q28, [X7, X0]

  (252) 0x421b40 FADD	V19.2D, V16.2D, V17.2D

  (252) 0x421b44 FADD	V20.2D, V18.2D, V28.2D

  (252) 0x421b48 FADD	V21.2D, V19.2D, V20.2D

  (252) 0x421b4c FMUL	V22.2D, V21.2D, V30.2D

  (252) 0x421b50 STR	Q22, [X6, X0]

  (252) 0x421b54 ADD	X0, X0, #16

  (252) 0x421b58 LDR	Q27, [X10, X0]

  (252) 0x421b5c LDR	Q29, [X9, X0]

  (252) 0x421b60 LDR	Q26, [X8, X0]

  (252) 0x421b64 LDR	Q25, [X7, X0]

  (252) 0x421b68 FADD	V23.2D, V27.2D, V29.2D

  (252) 0x421b6c FADD	V24.2D, V26.2D, V25.2D

  (252) 0x421b70 FADD	V6.2D, V23.2D, V24.2D

  (252) 0x421b74 FMUL	V5.2D, V6.2D, V30.2D

  (252) 0x421b78 STR	Q5, [X6, X0]

  (252) 0x421b7c ADD	X0, X0, #16

  (252) 0x421b80 CMP	X13, X0

  (252) 0x421b84 B.EQ	421c30

    (253) 0x421b88 LDR	Q4, [X10, X0]

    (253) 0x421b8c ADD	X24, X0, #16

    (253) 0x421b90 ADD	X4, X0, #32

    (253) 0x421b94 ADD	X3, X0, #48

    (253) 0x421b98 LDR	Q3, [X9, X0]

    (253) 0x421b9c LDR	Q0, [X8, X0]

    (253) 0x421ba0 LDR	Q1, [X7, X0]

    (253) 0x421ba4 FADD	V2.2D, V4.2D, V3.2D

    (253) 0x421ba8 FADD	V7.2D, V0.2D, V1.2D

    (253) 0x421bac FADD	V16.2D, V2.2D, V7.2D

    (253) 0x421bb0 FMUL	V17.2D, V16.2D, V30.2D

    (253) 0x421bb4 STR	Q17, [X6, X0]

    (253) 0x421bb8 ADD	X0, X0, #64

    (253) 0x421bbc LDR	Q28, [X10, X24]

    (253) 0x421bc0 LDR	Q19, [X9, X24]

    (253) 0x421bc4 LDR	Q18, [X8, X24]

    (253) 0x421bc8 LDR	Q20, [X7, X24]

    (253) 0x421bcc FADD	V21.2D, V28.2D, V19.2D

    (253) 0x421bd0 FADD	V22.2D, V18.2D, V20.2D

    (253) 0x421bd4 FADD	V27.2D, V21.2D, V22.2D

    (253) 0x421bd8 FMUL	V29.2D, V27.2D, V30.2D

    (253) 0x421bdc STR	Q29, [X6, X24]

    (253) 0x421be0 LDR	Q26, [X10, X4]

    (253) 0x421be4 LDR	Q25, [X9, X4]

    (253) 0x421be8 LDR	Q23, [X8, X4]

    (253) 0x421bec LDR	Q24, [X7, X4]

    (253) 0x421bf0 FADD	V6.2D, V26.2D, V25.2D

    (253) 0x421bf4 FADD	V5.2D, V23.2D, V24.2D

    (253) 0x421bf8 FADD	V4.2D, V6.2D, V5.2D

    (253) 0x421bfc FMUL	V3.2D, V4.2D, V30.2D

    (253) 0x421c00 STR	Q3, [X6, X4]

    (253) 0x421c04 LDR	Q0, [X10, X3]

    (253) 0x421c08 LDR	Q7, [X9, X3]

    (253) 0x421c0c LDR	Q2, [X8, X3]

    (253) 0x421c10 LDR	Q1, [X7, X3]

    (253) 0x421c14 FADD	V16.2D, V0.2D, V7.2D

    (253) 0x421c18 FADD	V17.2D, V2.2D, V1.2D

    (253) 0x421c1c FADD	V28.2D, V16.2D, V17.2D

    (253) 0x421c20 FMUL	V19.2D, V28.2D, V30.2D

    (253) 0x421c24 STR	Q19, [X6, X3]

    (253) 0x421c28 CMP	X13, X0

    (253) 0x421c2c B.NE	421b88

  (252) 0x421c30 TBZ	W1, #0, 421c80

  (252) 0x421c34 AND	W1, W1, #1951

  (252) 0x421c38 ADD	W5, W5, W1

  (252) 0x421c3c SUB	W13, W5, #1

  (252) 0x421c40 SBFM	X26, X5, #0, #31

  (252) 0x421c44 SBFM	X25, X13, #0, #31

  (252) 0x421c48 ADD	X10, X12, X26

  (252) 0x421c4c ADD	X8, X15, X25

  (252) 0x421c50 ADD	X12, X12, X25

  (252) 0x421c54 ADD	X15, X15, X26

  (252) 0x421c58 LDR	D18, [X11, X10,LSL #3]

  (252) 0x421c5c ADD	X16, X16, X26

  (252) 0x421c60 LDR	D20, [X11, X12,LSL #3]

  (252) 0x421c64 LDR	D21, [X11, X8,LSL #3]

  (252) 0x421c68 LDR	D22, [X11, X15,LSL #3]

  (252) 0x421c6c FADD	D29, D20, D21

  (252) 0x421c70 FADD	D27, D18, D22

  (252) 0x421c74 FADD	D26, D27, D29

  (252) 0x421c78 FMUL	D25, D26, D31

  (252) 0x421c7c STR	D25, [X23, X16,LSL #3]

  (252) 0x421c80 ORR	W11, WZR, W17

  (252) 0x421c84 ADD	X14, X14, #1

  (252) 0x421c88 CMP	W19, W14

  (252) 0x421c8c B.LE	421ca0

  (252) 0x421c90 SUB	W1, W22, W11

  (252) 0x421c94 ORR	W17, WZR, W21

  (252) 0x421c98 ORR	W5, WZR, W20

  (252) 0x421c9c B	421a68

(251) 0x421ca0 LDP	X21, X22, [SP, #32]

(251) 0x421ca4 LDP	X19, X20, [SP, #16]

(251) 0x421ca8 LDP	X23, X24, [SP, #48]

(251) 0x421cac LDP	X25, X26, [SP, #64]

(251) 0x421cb0 LDP	X29, X30, [SP], #80

(251) 0x421cb4 RET

(251) 0x421cb8 ADD	W1, W1, #1

(251) 0x421cbc MOVZ	W3, #0

(251) 0x421cc0 B	421a34

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:157-160
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157-160
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4219c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W23, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421ca4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W23, W23, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421ca4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W21, W23, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W22, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 421cb8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:157-160
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157-160
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4219c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W23, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421ca4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W23, W23, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421ca4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W21, W23, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W22, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 421cb8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.17	0.88
▼Loop 251 - advec_mom.cpp:157-160 - exec–	0.00	0.00
▼Loop 252 - advec_mom.cpp:159-160 - exec–	0.00	0.01
○Loop 253 - advec_mom.cpp:160-160 - exec	1.16	0.88

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code