OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:167-172 [...]	Coverage (incl. loops): 3.28% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 167 - 172

--------------------------------------------------------------------------------

167: #pragma omp parallel for simd collapse(2)

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x421580 STP	X29, X30, [SP, #752]!

0x421584 ADD	X29, SP, #0

0x421588 STP	X19, X20, [SP, #16]

0x42158c ORR	X20, XZR, X0

0x421590 STP	X23, X24, [SP, #48]

0x421594 LDP	W1, W0, [X0, #40]

0x421598 LDP	W23, W2, [X20, #48]

0x42159c ADD	W4, W1, #1

0x4215a0 ADD	W3, W2, #4

0x4215a4 STP	W3, W4, [SP, #208]

0x4215a8 CMP	W23, W3

0x4215ac B.GE	42198c

0x4215b0 ADD	W19, W0, #3

0x4215b4 STP	X21, X22, [SP, #32]

0x4215b8 SUB	W22, W3, W23

0x4215bc CMP	W4, W19

0x4215c0 B.GE	421988

0x4215c4 SUB	W5, W19, W4

0x4215c8 MADD	W24, W22, W5, WZR

0x4215cc STR	W5, [SP, #264]

0x4215d0 BL	403890

0x4215d4 ORR	W21, WZR, W0

0x4215d8 BL	4038c0

0x4215dc UDIV	W7, W24, W21

0x4215e0 ORR	W6, WZR, W0

0x4215e4 MSUB	W8, W7, W21, W24

0x4215e8 CMP	W0, W8

0x4215ec B.CC	4219b8

  (248) 0x4215f0 MADD	W1, W7, W6, W8

  (248) 0x4215f4 ADD	W9, W7, W1

  (248) 0x4215f8 STR	W9, [SP, #268]

  (248) 0x4215fc CMP	W1, W9

  (248) 0x421600 B.CS	421988

  (248) 0x421604 LDR	W11, [SP, #264]

  (248) 0x421608 FMOV	D31, #0.2500000

  (248) 0x42160c FMOV	V30.2D, #0.2500000

  (248) 0x421610 STP	X25, X26, [SP, #64]

  (248) 0x421614 LDR	W15, [SP, #212]

  (248) 0x421618 UDIV	W12, W1, W11

  (248) 0x42161c STP	X27, X28, [SP, #80]

  (248) 0x421620 LDP	X10, X27, [X20]

  (248) 0x421624 LDP	X26, X28, [X20, #16]

  (248) 0x421628 ORR	X24, XZR, X10

  (248) 0x42162c MSUB	W13, W12, W11, W1

  (248) 0x421630 LDR	X25, [X20, #32]

  (248) 0x421634 ADD	W14, W12, W23

  (248) 0x421638 SBFM	X23, X14, #0, #31

  (248) 0x42163c ADD	W22, W13, W15

  (248) 0x421640 SUB	W3, W19, W22

    (249) 0x421644 CMP	W7, W3

    (249) 0x421648 CSEL	W2, W7, W3, #9

    (249) 0x42164c ADD	W16, W1, W2

    (249) 0x421650 STR	W16, [SP, #140]

    (249) 0x421654 CMP	W1, W16

    (249) 0x421658 B.CS	421964

    (249) 0x42165c LDR	X30, [X24]

    (249) 0x421660 SUB	W17, W23, #1

    (249) 0x421664 SBFM	X18, X17, #0, #31

    (249) 0x421668 LDR	X1, [X25]

    (249) 0x42166c LDR	X4, [X27]

    (249) 0x421670 MADD	X20, X18, X30, XZR

    (249) 0x421674 LDR	X0, [X26]

    (249) 0x421678 MADD	X21, X30, X23, XZR

    (249) 0x42167c MADD	X3, X18, X1, XZR

    (249) 0x421680 LDR	X19, [X28]

    (249) 0x421684 MADD	X30, X1, X23, XZR

    (249) 0x421688 MADD	X10, X18, X4, XZR

    (249) 0x42168c LDR	X7, [X28, #16]

    (249) 0x421690 MADD	X11, X4, X23, XZR

    (249) 0x421694 MADD	X12, X23, X0, XZR

    (249) 0x421698 LDR	X14, [X26, #16]

    (249) 0x42169c MADD	X13, X23, X19, XZR

    (249) 0x4216a0 LDR	X6, [X24, #16]

    (249) 0x4216a4 STR	X7, [SP, #104]

    (249) 0x4216a8 LDR	X5, [X25, #16]

    (249) 0x4216ac LDR	X16, [X27, #16]

    (249) 0x4216b0 STP	X14, X11, [SP, #144]

    (249) 0x4216b4 STP	X13, X10, [SP, #160]

    (249) 0x4216b8 STP	X12, X21, [SP, #176]

    (249) 0x4216bc STP	X3, X20, [SP, #192]

    (249) 0x4216c0 CMP	W2, #1

    (249) 0x4216c4 B.EQ	4218c0

    (249) 0x4216c8 SBFM	X18, X22, #0, #31

    (249) 0x4216cc UBFM	W19, W2, #1, #31

    (249) 0x4216d0 ADD	X8, X20, X18

    (249) 0x4216d4 ADD	X9, X3, X18

    (249) 0x4216d8 ADD	X15, X21, X18

    (249) 0x4216dc UBFM	X17, X8, #61, #60

    (249) 0x4216e0 ADD	X7, X6, X8,LSL #3

    (249) 0x4216e4 ADD	X1, X5, X9,LSL #3

    (249) 0x4216e8 UBFM	X8, X9, #61, #60

    (249) 0x4216ec UBFM	X9, X15, #61, #60

    (249) 0x4216f0 ADD	X3, X6, X15,LSL #3

    (249) 0x4216f4 SUB	X15, X8, #8

    (249) 0x4216f8 ADD	X10, X10, X18

    (249) 0x4216fc STP	X8, X9, [SP, #216]

    (249) 0x421700 SUB	X8, X9, #8

    (249) 0x421704 ADD	X4, X30, X18

    (249) 0x421708 UBFM	X20, X4, #61, #60

    (249) 0x42170c SUB	X21, X17, #8

    (249) 0x421710 ADD	X4, X5, X4,LSL #3

    (249) 0x421714 SUB	X9, X20, #8

    (249) 0x421718 ADD	X11, X11, X18

    (249) 0x42171c STP	X15, X8, [SP, #112]

    (249) 0x421720 UBFM	X15, X10, #61, #60

    (249) 0x421724 MOVZ	X0, #0

    (249) 0x421728 STR	X15, [SP, #248]

    (249) 0x42172c LDR	X15, [SP, #104]

    (249) 0x421730 STP	X20, X21, [SP, #232]

    (249) 0x421734 ADD	X20, X12, X18

    (249) 0x421738 ADD	X18, X13, X18

    (249) 0x42173c ADD	X13, X16, X10,LSL #3

    (249) 0x421740 ADD	X12, X14, X20,LSL #3

    (249) 0x421744 SUB	X14, X17, #8

    (249) 0x421748 UBFM	X21, X20, #61, #60

    (249) 0x42174c ADD	X8, X6, X14

    (249) 0x421750 UBFM	X20, X11, #61, #60

    (249) 0x421754 ADD	X14, X16, X11,LSL #3

    (249) 0x421758 STR	X9, [SP, #128]

    (249) 0x42175c LDR	X11, [SP, #128]

    (249) 0x421760 ADD	X15, X15, X18,LSL #3

    (249) 0x421764 UBFM	X18, X18, #61, #60

    (249) 0x421768 LDP	X9, X10, [SP, #112]

    (249) 0x42176c STR	X18, [SP, #256]

    (249) 0x421770 UBFM	X18, X19, #60, #59

    (249) 0x421774 ADD	X11, X5, X11

    (249) 0x421778 ADD	X9, X5, X9

    (249) 0x42177c ADD	X10, X6, X10

    (249) 0x421780 TBZ	W19, #0, 421804

    (249) 0x421784 LDR	X19, [SP, #232]

    (249) 0x421788 LDR	Q21, [X6, X17]

    (249) 0x42178c LDP	X17, X0, [SP, #216]

    (249) 0x421790 LDR	Q18, [X5, X19]

    (249) 0x421794 LDR	X19, [SP, #120]

    (249) 0x421798 LDR	Q20, [X5, X17]

    (249) 0x42179c LDR	X17, [SP, #240]

    (249) 0x4217a0 LDR	Q7, [X6, X19]

    (249) 0x4217a4 LDR	X19, [SP, #128]

    (249) 0x4217a8 LDR	Q19, [X6, X0]

    (249) 0x4217ac MOVZ	X0, #16

    (249) 0x4217b0 LDR	Q17, [X6, X17]

    (249) 0x4217b4 LDR	Q6, [X5, X19]

    (249) 0x4217b8 LDR	X17, [SP, #112]

    (249) 0x4217bc FMUL	V0.2D, V19.2D, V18.2D

    (249) 0x4217c0 LDR	X19, [SP, #104]

    (249) 0x4217c4 FMUL	V1.2D, V7.2D, V6.2D

    (249) 0x4217c8 LDR	Q16, [X5, X17]

    (249) 0x4217cc FMLA	V0.2D, V21.2D, V20.2D

    (249) 0x4217d0 LDR	X17, [SP, #144]

    (249) 0x4217d4 FMLA	V1.2D, V17.2D, V16.2D

    (249) 0x4217d8 FADD	V2.2D, V0.2D, V1.2D

    (249) 0x4217dc FMUL	V3.2D, V2.2D, V30.2D

    (249) 0x4217e0 STR	Q3, [X17, X21]

    (249) 0x4217e4 LDR	Q5, [X16, X20]

    (249) 0x4217e8 LDP	X21, X20, [SP, #248]

    (249) 0x4217ec LDR	Q4, [X16, X21]

    (249) 0x4217f0 FSUB	V22.2D, V5.2D, V4.2D

    (249) 0x4217f4 FADD	V23.2D, V22.2D, V3.2D

    (249) 0x4217f8 STR	Q23, [X19, X20]

    (249) 0x4217fc CMP	X18, X0

    (249) 0x421800 B.EQ	4218b4

      (250) 0x421804 LDR	Q24, [X3, X0]

      (250) 0x421808 ADD	X17, X0, #16

      (250) 0x42180c LDR	Q25, [X4, X0]

      (250) 0x421810 LDR	Q28, [X10, X0]

      (250) 0x421814 LDR	Q27, [X11, X0]

      (250) 0x421818 LDR	Q29, [X7, X0]

      (250) 0x42181c FMUL	V26.2D, V24.2D, V25.2D

      (250) 0x421820 LDR	Q21, [X1, X0]

      (250) 0x421824 LDR	Q19, [X8, X0]

      (250) 0x421828 FMUL	V18.2D, V28.2D, V27.2D

      (250) 0x42182c LDR	Q0, [X9, X0]

      (250) 0x421830 FMLA	V26.2D, V29.2D, V21.2D

      (250) 0x421834 FMLA	V18.2D, V19.2D, V0.2D

      (250) 0x421838 FADD	V20.2D, V26.2D, V18.2D

      (250) 0x42183c FMUL	V7.2D, V20.2D, V30.2D

      (250) 0x421840 STR	Q7, [X12, X0]

      (250) 0x421844 LDR	Q17, [X14, X0]

      (250) 0x421848 LDR	Q6, [X13, X0]

      (250) 0x42184c FSUB	V1.2D, V17.2D, V6.2D

      (250) 0x421850 FADD	V16.2D, V1.2D, V7.2D

      (250) 0x421854 STR	Q16, [X15, X0]

      (250) 0x421858 ADD	X0, X0, #32

      (250) 0x42185c LDR	Q2, [X3, X17]

      (250) 0x421860 LDR	Q3, [X4, X17]

      (250) 0x421864 LDR	Q5, [X10, X17]

      (250) 0x421868 LDR	Q4, [X11, X17]

      (250) 0x42186c LDR	Q22, [X7, X17]

      (250) 0x421870 FMUL	V23.2D, V2.2D, V3.2D

      (250) 0x421874 LDR	Q24, [X1, X17]

      (250) 0x421878 LDR	Q25, [X8, X17]

      (250) 0x42187c FMUL	V28.2D, V5.2D, V4.2D

      (250) 0x421880 LDR	Q27, [X9, X17]

      (250) 0x421884 FMLA	V23.2D, V22.2D, V24.2D

      (250) 0x421888 FMLA	V28.2D, V25.2D, V27.2D

      (250) 0x42188c FADD	V29.2D, V23.2D, V28.2D

      (250) 0x421890 FMUL	V26.2D, V29.2D, V30.2D

      (250) 0x421894 STR	Q26, [X12, X17]

      (250) 0x421898 LDR	Q21, [X14, X17]

      (250) 0x42189c LDR	Q19, [X13, X17]

      (250) 0x4218a0 FSUB	V18.2D, V21.2D, V19.2D

      (250) 0x4218a4 FADD	V0.2D, V18.2D, V26.2D

      (250) 0x4218a8 STR	Q0, [X15, X17]

      (250) 0x4218ac CMP	X18, X0

      (250) 0x4218b0 B.NE	421804

    (249) 0x4218b4 TBZ	W2, #0, 421960

    (249) 0x4218b8 AND	W2, W2, #1951

    (249) 0x4218bc ADD	W22, W22, W2

    (249) 0x4218c0 LDP	X14, X4, [SP, #176]

    (249) 0x4218c4 SUB	W7, W22, #1

    (249) 0x4218c8 SBFM	X13, X22, #0, #31

    (249) 0x4218cc SBFM	X1, X7, #0, #31

    (249) 0x4218d0 ADD	X3, X30, X13

    (249) 0x4218d4 ADD	X30, X30, X1

    (249) 0x4218d8 LDP	X8, X12, [SP, #192]

    (249) 0x4218dc ADD	X9, X4, X1

    (249) 0x4218e0 ADD	X15, X4, X13

    (249) 0x4218e4 ADD	X18, X14, X13

    (249) 0x4218e8 LDR	D20, [X5, X3,LSL #3]

    (249) 0x4218ec ADD	X10, X8, X1

    (249) 0x4218f0 ADD	X0, X12, X1

    (249) 0x4218f4 LDR	D7, [X5, X30,LSL #3]

    (249) 0x4218f8 ADD	X11, X8, X13

    (249) 0x4218fc ADD	X21, X12, X13

    (249) 0x421900 LDR	D17, [X6, X9,LSL #3]

    (249) 0x421904 LDR	D6, [X6, X15,LSL #3]

    (249) 0x421908 LDR	D16, [X5, X10,LSL #3]

    (249) 0x42190c LDR	D2, [X6, X0,LSL #3]

    (249) 0x421910 FMUL	D1, D7, D17

    (249) 0x421914 LDR	D3, [X5, X11,LSL #3]

    (249) 0x421918 FMUL	D5, D20, D6

    (249) 0x42191c LDR	D4, [X6, X21,LSL #3]

    (249) 0x421920 LDP	X6, X5, [SP, #144]

    (249) 0x421924 FMADD	D22, D16, D2, D1

    (249) 0x421928 LDR	X19, [SP, #104]

    (249) 0x42192c FMADD	D23, D3, D4, D5

    (249) 0x421930 ADD	X20, X5, X13

    (249) 0x421934 FADD	D24, D23, D22

    (249) 0x421938 FMUL	D28, D24, D31

    (249) 0x42193c STR	D28, [X6, X18,LSL #3]

    (249) 0x421940 LDP	X17, X2, [SP, #160]

    (249) 0x421944 LDR	D27, [X16, X20,LSL #3]

    (249) 0x421948 ADD	X22, X2, X13

    (249) 0x42194c ADD	X7, X17, X13

    (249) 0x421950 LDR	D25, [X16, X22,LSL #3]

    (249) 0x421954 FSUB	D29, D27, S25

    (249) 0x421958 FADD	D26, D29, D28

    (249) 0x42195c STR	D26, [X19, X7,LSL #3]

    (249) 0x421960 LDR	W1, [SP, #140]

    (249) 0x421964 ADD	X23, X23, #1

    (249) 0x421968 LDR	W16, [SP, #208]

    (249) 0x42196c CMP	W16, W23

    (249) 0x421970 B.LE	42199c

    (249) 0x421974 LDR	W13, [SP, #268]

    (249) 0x421978 LDR	W22, [SP, #212]

    (249) 0x42197c LDR	W3, [SP, #264]

    (249) 0x421980 SUB	W7, W13, W1

    (249) 0x421984 B	421644

(247) 0x421988 LDP	X21, X22, [SP, #32]

(247) 0x42198c LDP	X19, X20, [SP, #16]

(247) 0x421990 LDP	X23, X24, [SP, #48]

(247) 0x421994 LDP	X29, X30, [SP], #272

(247) 0x421998 RET

  (248) 0x42199c LDP	X21, X22, [SP, #32]

  (248) 0x4219a0 LDP	X25, X26, [SP, #64]

  (248) 0x4219a4 LDP	X27, X28, [SP, #80]

  (248) 0x4219a8 LDP	X19, X20, [SP, #16]

  (248) 0x4219ac LDP	X23, X24, [SP, #48]

  (248) 0x4219b0 LDP	X29, X30, [SP], #272

  (248) 0x4219b4 RET

  (248) 0x4219b8 ADD	W7, W7, #1

  (248) 0x4219bc MOVZ	W8, #0

  (248) 0x4219c0 B	4215f0

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #752]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W1, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W23, W2, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W4, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W3, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42198c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421988 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W22, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 4219b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #752]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W1, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W23, W2, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W4, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W3, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42198c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421988 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W22, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 4219b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.28	2.49
▼Loop 247 - advec_mom.cpp:167-172 - exec–	0.00	0.00
▼Loop 248 - advec_mom.cpp:167-172 - exec–	0.00	0.00
▼Loop 249 - advec_mom.cpp:169-172 - exec–	0.00	0.01
○Loop 250 - advec_mom.cpp:170-172 - exec	3.28	2.47

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code