OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:146-149 [...]	Coverage (incl. loops): 4.85% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 146 - 149

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x421228 STP	X29, X30, [SP, #912]!

0x42122c ADD	X29, SP, #0

0x421230 STP	X19, X20, [SP, #16]

0x421234 ORR	X20, XZR, X0

0x421238 STP	X21, X22, [SP, #32]

0x42123c STP	X23, X24, [SP, #48]

0x421240 LDP	W22, W23, [X0, #40]

0x421244 LDP	W0, W19, [X0, #32]

0x421248 ADD	W22, W22, #1

0x42124c ADD	W23, W23, #3

0x421250 CMP	W22, W23

0x421254 B.GE	421554

0x421258 ADD	W19, W19, #3

0x42125c STP	X27, X28, [SP, #80]

0x421260 ADD	W28, W0, #1

0x421264 SUB	W24, W23, W22

0x421268 CMP	W28, W19

0x42126c B.GE	421550

0x421270 SUB	W1, W19, W28

0x421274 MADD	W27, W24, W1, WZR

0x421278 STR	W1, [SP, #100]

0x42127c BL	403890

0x421280 ORR	W21, WZR, W0

0x421284 BL	4038c0

0x421288 UDIV	W2, W27, W21

0x42128c ORR	W3, WZR, W0

0x421290 MSUB	W4, W2, W21, W27

0x421294 CMP	W0, W4

0x421298 B.CC	421568

(244) 0x42129c MADD	W16, W2, W3, W4

(244) 0x4212a0 ADD	W5, W2, W16

(244) 0x4212a4 STR	W5, [SP, #104]

(244) 0x4212a8 CMP	W16, W5

(244) 0x4212ac B.CS	421550

(244) 0x4212b0 LDR	W6, [SP, #100]

(244) 0x4212b4 STP	X25, X26, [SP, #64]

(244) 0x4212b8 LDP	X26, X27, [X20]

(244) 0x4212bc UDIV	W7, W16, W6

(244) 0x4212c0 LDP	X24, X25, [X20, #16]

(244) 0x4212c4 STR	W28, [SP, #108]

(244) 0x4212c8 MSUB	W11, W7, W6, W16

(244) 0x4212cc ADD	W8, W7, W22

(244) 0x4212d0 SBFM	X4, X8, #0, #31

(244) 0x4212d4 ADD	W11, W11, W28

(244) 0x4212d8 SUB	W19, W19, W11

(244) 0x4212dc HINT	#0

  (245) 0x4212e0 CMP	W2, W19

  (245) 0x4212e4 CSEL	W2, W2, W19, #9

  (245) 0x4212e8 ADD	W20, W16, W2

  (245) 0x4212ec CMP	W16, W20

  (245) 0x4212f0 B.CS	421530

  (245) 0x4212f4 LDR	X14, [X24]

  (245) 0x4212f8 LDR	X13, [X25]

  (245) 0x4212fc LDR	X10, [X26]

  (245) 0x421300 MADD	X14, X4, X14, XZR

  (245) 0x421304 LDR	X17, [X27]

  (245) 0x421308 MADD	X13, X4, X13, XZR

  (245) 0x42130c LDR	X22, [X24, #16]

  (245) 0x421310 MADD	X10, X4, X10, XZR

  (245) 0x421314 LDR	X16, [X25, #16]

  (245) 0x421318 MADD	X17, X4, X17, XZR

  (245) 0x42131c LDR	X19, [X26, #16]

  (245) 0x421320 LDR	X21, [X27, #16]

  (245) 0x421324 CMP	W2, #1

  (245) 0x421328 B.EQ	4214e8

  (245) 0x42132c UBFM	W12, W2, #1, #31

  (245) 0x421330 SBFM	X3, X11, #0, #31

  (245) 0x421334 UBFM	X12, X12, #60, #59

  (245) 0x421338 ADD	X15, X13, X3

  (245) 0x42133c SUB	X9, X12, #16

  (245) 0x421340 UBFM	X15, X15, #61, #60

  (245) 0x421344 UBFM	X18, X9, #4, #63

  (245) 0x421348 ADD	X5, X10, X3

  (245) 0x42134c ADD	X28, X18, #1

  (245) 0x421350 SUB	X30, X15, #8

  (245) 0x421354 ADD	X1, X19, X5,LSL #3

  (245) 0x421358 ANDS	X9, X28, #4160

  (245) 0x42135c ADD	X28, X14, X3

  (245) 0x421360 ADD	X3, X17, X3

  (245) 0x421364 ADD	X7, X22, X28,LSL #3

  (245) 0x421368 UBFM	X18, X5, #61, #60

  (245) 0x42136c MOVZ	X0, #0

  (245) 0x421370 ADD	X5, X21, X3,LSL #3

  (245) 0x421374 ADD	X6, X16, X30

  (245) 0x421378 ADD	X8, X16, X15

  (245) 0x42137c UBFM	X28, X28, #61, #60

  (245) 0x421380 UBFM	X3, X3, #61, #60

  (245) 0x421384 B.EQ	421424

  (245) 0x421388 CMP	X9, #1

  (245) 0x42138c B.EQ	4213f0

  (245) 0x421390 CMP	X9, #2

  (245) 0x421394 B.EQ	4213c4

  (245) 0x421398 LDR	Q28, [X16, X15]

  (245) 0x42139c MOVZ	X0, #16

  (245) 0x4213a0 LDR	Q30, [X19, X18]

  (245) 0x4213a4 LDR	Q0, [X22, X28]

  (245) 0x4213a8 FNEG	V1.2D, V28.2D

  (245) 0x4213ac LDR	Q31, [X16, X30]

  (245) 0x4213b0 LDR	Q29, [X21, X3]

  (245) 0x4213b4 FMLA	V1.2D, V30.2D, V0.2D

  (245) 0x4213b8 FADD	V2.2D, V1.2D, V31.2D

  (245) 0x4213bc FDIV	V3.2D, V2.2D, V29.2D

  (245) 0x4213c0 STR	Q3, [X19, X18]

  (245) 0x4213c4 LDR	Q24, [X8, X0]

  (245) 0x4213c8 LDR	Q26, [X1, X0]

  (245) 0x4213cc LDR	Q4, [X7, X0]

  (245) 0x4213d0 FNEG	V5.2D, V24.2D

  (245) 0x4213d4 LDR	Q27, [X6, X0]

  (245) 0x4213d8 LDR	Q25, [X5, X0]

  (245) 0x4213dc FMLA	V5.2D, V26.2D, V4.2D

  (245) 0x4213e0 FADD	V6.2D, V5.2D, V27.2D

  (245) 0x4213e4 FDIV	V7.2D, V6.2D, V25.2D

  (245) 0x4213e8 STR	Q7, [X1, X0]

  (245) 0x4213ec ADD	X0, X0, #16

  (245) 0x4213f0 LDR	Q20, [X8, X0]

  (245) 0x4213f4 LDR	Q22, [X1, X0]

  (245) 0x4213f8 LDR	Q16, [X7, X0]

  (245) 0x4213fc FNEG	V17.2D, V20.2D

  (245) 0x421400 LDR	Q23, [X6, X0]

  (245) 0x421404 LDR	Q21, [X5, X0]

  (245) 0x421408 FMLA	V17.2D, V22.2D, V16.2D

  (245) 0x42140c FADD	V18.2D, V17.2D, V23.2D

  (245) 0x421410 FDIV	V19.2D, V18.2D, V21.2D

  (245) 0x421414 STR	Q19, [X1, X0]

  (245) 0x421418 ADD	X0, X0, #16

  (245) 0x42141c CMP	X12, X0

  (245) 0x421420 B.EQ	4214dc

    (246) 0x421424 LDR	Q28, [X8, X0]

    (246) 0x421428 ADD	X30, X0, #16

    (246) 0x42142c ADD	X15, X0, #32

    (246) 0x421430 ADD	X9, X0, #48

    (246) 0x421434 LDR	Q30, [X1, X0]

    (246) 0x421438 LDR	Q0, [X7, X0]

    (246) 0x42143c FNEG	V1.2D, V28.2D

    (246) 0x421440 LDR	Q31, [X6, X0]

    (246) 0x421444 LDR	Q29, [X5, X0]

    (246) 0x421448 FMLA	V1.2D, V30.2D, V0.2D

    (246) 0x42144c FADD	V2.2D, V1.2D, V31.2D

    (246) 0x421450 FDIV	V3.2D, V2.2D, V29.2D

    (246) 0x421454 STR	Q3, [X1, X0]

    (246) 0x421458 ADD	X0, X0, #64

    (246) 0x42145c LDR	Q24, [X8, X30]

    (246) 0x421460 LDR	Q26, [X1, X30]

    (246) 0x421464 LDR	Q4, [X7, X30]

    (246) 0x421468 FNEG	V5.2D, V24.2D

    (246) 0x42146c LDR	Q27, [X6, X30]

    (246) 0x421470 LDR	Q25, [X5, X30]

    (246) 0x421474 FMLA	V5.2D, V26.2D, V4.2D

    (246) 0x421478 FADD	V6.2D, V5.2D, V27.2D

    (246) 0x42147c FDIV	V7.2D, V6.2D, V25.2D

    (246) 0x421480 STR	Q7, [X1, X30]

    (246) 0x421484 LDR	Q20, [X8, X15]

    (246) 0x421488 LDR	Q22, [X1, X15]

    (246) 0x42148c LDR	Q16, [X7, X15]

    (246) 0x421490 FNEG	V17.2D, V20.2D

    (246) 0x421494 LDR	Q23, [X6, X15]

    (246) 0x421498 LDR	Q21, [X5, X15]

    (246) 0x42149c FMLA	V17.2D, V22.2D, V16.2D

    (246) 0x4214a0 FADD	V18.2D, V17.2D, V23.2D

    (246) 0x4214a4 FDIV	V19.2D, V18.2D, V21.2D

    (246) 0x4214a8 STR	Q19, [X1, X15]

    (246) 0x4214ac LDR	Q28, [X8, X9]

    (246) 0x4214b0 LDR	Q30, [X1, X9]

    (246) 0x4214b4 LDR	Q0, [X7, X9]

    (246) 0x4214b8 FNEG	V1.2D, V28.2D

    (246) 0x4214bc LDR	Q31, [X6, X9]

    (246) 0x4214c0 LDR	Q29, [X5, X9]

    (246) 0x4214c4 FMLA	V1.2D, V30.2D, V0.2D

    (246) 0x4214c8 FADD	V2.2D, V1.2D, V31.2D

    (246) 0x4214cc FDIV	V3.2D, V2.2D, V29.2D

    (246) 0x4214d0 STR	Q3, [X1, X9]

    (246) 0x4214d4 CMP	X12, X0

    (246) 0x4214d8 B.NE	421424

  (245) 0x4214dc TBZ	W2, #0, 42152c

  (245) 0x4214e0 AND	W2, W2, #1951

  (245) 0x4214e4 ADD	W11, W11, W2

  (245) 0x4214e8 SBFM	X12, X11, #0, #31

  (245) 0x4214ec SUB	W1, W11, #1

  (245) 0x4214f0 ADD	X6, X13, W1,SXTW

  (245) 0x4214f4 LDR	D24, [X16, X6,LSL #3]

  (245) 0x4214f8 ADD	X10, X10, X12

  (245) 0x4214fc ADD	X14, X14, X12

  (245) 0x421500 UBFM	X7, X10, #61, #60

  (245) 0x421504 ADD	X13, X13, X12

  (245) 0x421508 LDR	D26, [X22, X14,LSL #3]

  (245) 0x42150c ADD	X22, X17, X12

  (245) 0x421510 LDR	D4, [X19, X7]

  (245) 0x421514 LDR	D5, [X16, X13,LSL #3]

  (245) 0x421518 LDR	D27, [X21, X22,LSL #3]

  (245) 0x42151c FMADD	D25, D26, D4, D24

  (245) 0x421520 FSUB	D6, D25, S5

  (245) 0x421524 FDIV	D7, D6, D27

  (245) 0x421528 STR	D7, [X19, X7]

  (245) 0x42152c ORR	W16, WZR, W20

  (245) 0x421530 ADD	X4, X4, #1

  (245) 0x421534 CMP	W23, W4

  (245) 0x421538 B.LE	42154c

  (245) 0x42153c LDP	W20, W11, [SP, #104]

  (245) 0x421540 LDR	W19, [SP, #100]

  (245) 0x421544 SUB	W2, W20, W16

  (245) 0x421548 B	4212e0

(244) 0x42154c LDP	X25, X26, [SP, #64]

(244) 0x421550 LDP	X27, X28, [SP, #80]

(244) 0x421554 LDP	X19, X20, [SP, #16]

(244) 0x421558 LDP	X21, X22, [SP, #32]

(244) 0x42155c LDP	X23, X24, [SP, #48]

(244) 0x421560 LDP	X29, X30, [SP], #112

(244) 0x421564 RET

(244) 0x421568 ADD	W2, W2, #1

(244) 0x42156c MOVZ	W4, #0

(244) 0x421570 B	42129c

0x421574 HINT	#0

0x421578 HINT	#0

0x42157c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 46% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421228

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W23, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W19, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W23, W23, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421554 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W28, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W24, W23, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W28, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421550 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, W19, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W27, W24, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W1, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W27, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W4, W2, W21, W27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 421568 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421228

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W23, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W19, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W23, W23, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421554 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W28, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W24, W23, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W28, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421550 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, W19, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W27, W24, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W1, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W27, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W4, W2, W21, W27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 421568 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.85	3.68
▼Loop 244 - advec_mom.cpp:146-149 - exec–	0.00	0.00
▼Loop 245 - advec_mom.cpp:148-149 - exec–	0.00	0.01
○Loop 246 - advec_mom.cpp:149-149 - exec	4.85	3.65

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code