OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:85-88 [...]	Coverage (incl. loops): 1.16% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 85 - 88

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

87:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

88:           node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x420f20 STP	X29, X30, [SP, #944]!

0x420f24 ADD	X29, SP, #0

0x420f28 STP	X19, X20, [SP, #16]

0x420f2c STP	X23, X24, [SP, #48]

0x420f30 STP	X25, X26, [SP, #64]

0x420f34 LDP	W25, W19, [X0, #24]

0x420f38 LDP	W20, W23, [X0, #16]

0x420f3c ADD	W25, W25, #1

0x420f40 ADD	W19, W19, #3

0x420f44 CMP	W25, W19

0x420f48 B.GE	421208

0x420f4c SUB	W20, W20, #1

0x420f50 ADD	W23, W23, #4

0x420f54 SUB	W26, W19, W25

0x420f58 CMP	W20, W23

0x420f5c B.GE	421208

0x420f60 STP	X21, X22, [SP, #32]

0x420f64 SUB	W21, W23, W20

0x420f68 ORR	X24, XZR, X0

0x420f6c MADD	W26, W26, W21, WZR

0x420f70 BL	403890

0x420f74 ORR	W22, WZR, W0

0x420f78 BL	4038c0

0x420f7c UDIV	W1, W26, W22

0x420f80 ORR	W2, WZR, W0

0x420f84 MSUB	W3, W1, W22, W26

0x420f88 CMP	W0, W3

0x420f8c B.CC	42121c

(241) 0x420f90 MADD	W12, W1, W2, W3

(241) 0x420f94 ADD	W22, W1, W12

(241) 0x420f98 CMP	W12, W22

(241) 0x420f9c B.CS	421204

(241) 0x420fa0 UDIV	W0, W12, W21

(241) 0x420fa4 LDP	X18, X30, [X24]

(241) 0x420fa8 FMOV	D31, #0.2500000

(241) 0x420fac FMOV	V30.2D, #0.2500000

(241) 0x420fb0 MSUB	W5, W0, W21, W12

(241) 0x420fb4 ADD	W4, W0, W25

(241) 0x420fb8 SBFM	X15, X4, #0, #31

(241) 0x420fbc ADD	W5, W5, W20

(241) 0x420fc0 SUB	W17, W23, W5

  (242) 0x420fc4 CMP	W1, W17

  (242) 0x420fc8 CSEL	W1, W1, W17, #9

  (242) 0x420fcc ADD	W17, W12, W1

  (242) 0x420fd0 CMP	W12, W17

  (242) 0x420fd4 B.CS	4211e8

  (242) 0x420fd8 LDR	X13, [X18]

  (242) 0x420fdc SUB	W6, W15, #1

  (242) 0x420fe0 SBFM	X7, X6, #0, #31

  (242) 0x420fe4 LDR	X16, [X30]

  (242) 0x420fe8 LDR	X12, [X18, #16]

  (242) 0x420fec MADD	X6, X7, X13, XZR

  (242) 0x420ff0 LDR	X23, [X30, #16]

  (242) 0x420ff4 MADD	X13, X15, X13, XZR

  (242) 0x420ff8 MADD	X16, X15, X16, XZR

  (242) 0x420ffc CMP	W1, #1

  (242) 0x421000 B.EQ	4211a0

  (242) 0x421004 UBFM	W14, W1, #1, #31

  (242) 0x421008 SBFM	X8, X5, #0, #31

  (242) 0x42100c UBFM	X14, X14, #60, #59

  (242) 0x421010 ADD	X9, X6, X8

  (242) 0x421014 SUB	X10, X14, #16

  (242) 0x421018 ADD	X25, X13, X8

  (242) 0x42101c ADD	X11, X12, X9,LSL #3

  (242) 0x421020 UBFM	X26, X10, #4, #63

  (242) 0x421024 UBFM	X24, X9, #61, #60

  (242) 0x421028 ADD	X10, X12, X25,LSL #3

  (242) 0x42102c ADD	X2, X26, #1

  (242) 0x421030 UBFM	X4, X25, #61, #60

  (242) 0x421034 ANDS	X3, X2, #4160

  (242) 0x421038 ADD	X26, X24, #8

  (242) 0x42103c ADD	X2, X16, X8

  (242) 0x421040 ADD	X25, X4, #8

  (242) 0x421044 ADD	X7, X23, X2,LSL #3

  (242) 0x421048 MOVZ	X0, #0

  (242) 0x42104c ADD	X9, X12, X26

  (242) 0x421050 ADD	X8, X12, X25

  (242) 0x421054 UBFM	X2, X2, #61, #60

  (242) 0x421058 B.EQ	4210ec

  (242) 0x42105c CMP	X3, #1

  (242) 0x421060 B.EQ	4210bc

  (242) 0x421064 CMP	X3, #2

  (242) 0x421068 B.EQ	421094

  (242) 0x42106c LDR	Q6, [X12, X24]

  (242) 0x421070 MOVZ	X0, #16

  (242) 0x421074 LDR	Q5, [X12, X4]

  (242) 0x421078 LDR	Q4, [X12, X26]

  (242) 0x42107c LDR	Q3, [X12, X25]

  (242) 0x421080 FADD	V0.2D, V6.2D, V5.2D

  (242) 0x421084 FADD	V1.2D, V4.2D, V3.2D

  (242) 0x421088 FADD	V2.2D, V0.2D, V1.2D

  (242) 0x42108c FMUL	V7.2D, V2.2D, V30.2D

  (242) 0x421090 STR	Q7, [X23, X2]

  (242) 0x421094 LDR	Q16, [X11, X0]

  (242) 0x421098 LDR	Q17, [X10, X0]

  (242) 0x42109c LDR	Q18, [X9, X0]

  (242) 0x4210a0 LDR	Q28, [X8, X0]

  (242) 0x4210a4 FADD	V19.2D, V16.2D, V17.2D

  (242) 0x4210a8 FADD	V20.2D, V18.2D, V28.2D

  (242) 0x4210ac FADD	V21.2D, V19.2D, V20.2D

  (242) 0x4210b0 FMUL	V22.2D, V21.2D, V30.2D

  (242) 0x4210b4 STR	Q22, [X7, X0]

  (242) 0x4210b8 ADD	X0, X0, #16

  (242) 0x4210bc LDR	Q27, [X11, X0]

  (242) 0x4210c0 LDR	Q29, [X10, X0]

  (242) 0x4210c4 LDR	Q26, [X9, X0]

  (242) 0x4210c8 LDR	Q25, [X8, X0]

  (242) 0x4210cc FADD	V23.2D, V27.2D, V29.2D

  (242) 0x4210d0 FADD	V24.2D, V26.2D, V25.2D

  (242) 0x4210d4 FADD	V6.2D, V23.2D, V24.2D

  (242) 0x4210d8 FMUL	V5.2D, V6.2D, V30.2D

  (242) 0x4210dc STR	Q5, [X7, X0]

  (242) 0x4210e0 ADD	X0, X0, #16

  (242) 0x4210e4 CMP	X14, X0

  (242) 0x4210e8 B.EQ	421194

    (243) 0x4210ec LDR	Q4, [X11, X0]

    (243) 0x4210f0 ADD	X24, X0, #16

    (243) 0x4210f4 ADD	X4, X0, #32

    (243) 0x4210f8 ADD	X3, X0, #48

    (243) 0x4210fc LDR	Q3, [X10, X0]

    (243) 0x421100 LDR	Q0, [X9, X0]

    (243) 0x421104 LDR	Q1, [X8, X0]

    (243) 0x421108 FADD	V2.2D, V4.2D, V3.2D

    (243) 0x42110c FADD	V7.2D, V0.2D, V1.2D

    (243) 0x421110 FADD	V16.2D, V2.2D, V7.2D

    (243) 0x421114 FMUL	V17.2D, V16.2D, V30.2D

    (243) 0x421118 STR	Q17, [X7, X0]

    (243) 0x42111c ADD	X0, X0, #64

    (243) 0x421120 LDR	Q28, [X11, X24]

    (243) 0x421124 LDR	Q19, [X10, X24]

    (243) 0x421128 LDR	Q18, [X9, X24]

    (243) 0x42112c LDR	Q20, [X8, X24]

    (243) 0x421130 FADD	V21.2D, V28.2D, V19.2D

    (243) 0x421134 FADD	V22.2D, V18.2D, V20.2D

    (243) 0x421138 FADD	V27.2D, V21.2D, V22.2D

    (243) 0x42113c FMUL	V29.2D, V27.2D, V30.2D

    (243) 0x421140 STR	Q29, [X7, X24]

    (243) 0x421144 LDR	Q26, [X11, X4]

    (243) 0x421148 LDR	Q25, [X10, X4]

    (243) 0x42114c LDR	Q23, [X9, X4]

    (243) 0x421150 LDR	Q24, [X8, X4]

    (243) 0x421154 FADD	V6.2D, V26.2D, V25.2D

    (243) 0x421158 FADD	V5.2D, V23.2D, V24.2D

    (243) 0x42115c FADD	V4.2D, V6.2D, V5.2D

    (243) 0x421160 FMUL	V3.2D, V4.2D, V30.2D

    (243) 0x421164 STR	Q3, [X7, X4]

    (243) 0x421168 LDR	Q0, [X11, X3]

    (243) 0x42116c LDR	Q7, [X10, X3]

    (243) 0x421170 LDR	Q2, [X9, X3]

    (243) 0x421174 LDR	Q1, [X8, X3]

    (243) 0x421178 FADD	V16.2D, V0.2D, V7.2D

    (243) 0x42117c FADD	V17.2D, V2.2D, V1.2D

    (243) 0x421180 FADD	V28.2D, V16.2D, V17.2D

    (243) 0x421184 FMUL	V19.2D, V28.2D, V30.2D

    (243) 0x421188 STR	Q19, [X7, X3]

    (243) 0x42118c CMP	X14, X0

    (243) 0x421190 B.NE	4210ec

  (242) 0x421194 TBZ	W1, #0, 4211e4

  (242) 0x421198 AND	W1, W1, #1951

  (242) 0x42119c ADD	W5, W5, W1

  (242) 0x4211a0 ADD	W14, W5, #1

  (242) 0x4211a4 SBFM	X11, X5, #0, #31

  (242) 0x4211a8 SBFM	X10, X14, #0, #31

  (242) 0x4211ac ADD	X26, X13, X11

  (242) 0x4211b0 ADD	X25, X6, X10

  (242) 0x4211b4 ADD	X13, X13, X10

  (242) 0x4211b8 ADD	X6, X6, X11

  (242) 0x4211bc LDR	D18, [X12, X26,LSL #3]

  (242) 0x4211c0 ADD	X16, X16, X11

  (242) 0x4211c4 LDR	D20, [X12, X13,LSL #3]

  (242) 0x4211c8 LDR	D21, [X12, X25,LSL #3]

  (242) 0x4211cc LDR	D22, [X12, X6,LSL #3]

  (242) 0x4211d0 FADD	D29, D20, D21

  (242) 0x4211d4 FADD	D27, D18, D22

  (242) 0x4211d8 FADD	D26, D27, D29

  (242) 0x4211dc FMUL	D25, D26, D31

  (242) 0x4211e0 STR	D25, [X23, X16,LSL #3]

  (242) 0x4211e4 ORR	W12, WZR, W17

  (242) 0x4211e8 ADD	X15, X15, #1

  (242) 0x4211ec CMP	W19, W15

  (242) 0x4211f0 B.LE	421204

  (242) 0x4211f4 SUB	W1, W22, W12

  (242) 0x4211f8 ORR	W17, WZR, W21

  (242) 0x4211fc ORR	W5, WZR, W20

  (242) 0x421200 B	420fc4

(241) 0x421204 LDP	X21, X22, [SP, #32]

(241) 0x421208 LDP	X19, X20, [SP, #16]

(241) 0x42120c LDP	X23, X24, [SP, #48]

(241) 0x421210 LDP	X25, X26, [SP, #64]

(241) 0x421214 LDP	X29, X30, [SP], #80

(241) 0x421218 RET

(241) 0x42121c ADD	W1, W1, #1

(241) 0x421220 MOVZ	W3, #0

(241) 0x421224 B	420f90

Coverage (%)	Name	Source Location	Module
►98.97+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:85-88
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:85-88
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W23, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421208 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W23, W23, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421208 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W21, W23, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W22, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42121c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:85-88
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:85-88
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W23, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421208 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W23, W23, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 421208 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W21, W23, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W22, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42121c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.16	0.88
▼Loop 241 - advec_mom.cpp:85-88 - exec–	0.00	0.00
▼Loop 242 - advec_mom.cpp:87-88 - exec–	0.00	0.01
○Loop 243 - advec_mom.cpp:88-88 - exec	1.15	0.87

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code