OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:95-100 [...]	Coverage (incl. loops): 3.12% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 95 - 100

--------------------------------------------------------------------------------

95: #pragma omp parallel for simd collapse(2)

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x420ae0 STP	X29, X30, [SP, #768]!

0x420ae4 ADD	X29, SP, #0

0x420ae8 STP	X19, X20, [SP, #16]

0x420aec ORR	X20, XZR, X0

0x420af0 STP	X21, X22, [SP, #32]

0x420af4 LDP	W22, W1, [X0, #48]

0x420af8 LDP	W2, W0, [X0, #40]

0x420afc ADD	W3, W1, #3

0x420b00 ADD	W22, W22, #1

0x420b04 STP	W3, W2, [SP, #184]

0x420b08 CMP	W22, W3

0x420b0c B.GE	420edc

0x420b10 ADD	W19, W0, #4

0x420b14 STP	X23, X24, [SP, #48]

0x420b18 SUB	W23, W3, W22

0x420b1c CMP	W2, W19

0x420b20 B.GE	420ed8

0x420b24 SUB	W4, W19, W2

0x420b28 MADD	W24, W23, W4, WZR

0x420b2c STR	W4, [SP, #248]

0x420b30 BL	403890

0x420b34 ORR	W21, WZR, W0

0x420b38 BL	4038c0

0x420b3c UDIV	W6, W24, W21

0x420b40 ORR	W5, WZR, W0

0x420b44 MSUB	W7, W6, W21, W24

0x420b48 CMP	W0, W7

0x420b4c B.CC	420f08

  (238) 0x420b50 MADD	W16, W6, W5, W7

  (238) 0x420b54 ADD	W8, W6, W16

  (238) 0x420b58 STR	W8, [SP, #252]

  (238) 0x420b5c CMP	W16, W8

  (238) 0x420b60 B.CS	420ed8

  (238) 0x420b64 LDR	W10, [SP, #248]

  (238) 0x420b68 FMOV	D31, #0.2500000

  (238) 0x420b6c FMOV	V30.2D, #0.2500000

  (238) 0x420b70 STP	X25, X26, [SP, #64]

  (238) 0x420b74 LDR	W14, [SP, #188]

  (238) 0x420b78 UDIV	W11, W16, W10

  (238) 0x420b7c STP	X27, X28, [SP, #80]

  (238) 0x420b80 LDP	X27, X28, [X20, #16]

  (238) 0x420b84 LDP	X23, X9, [X20]

  (238) 0x420b88 ORR	X26, XZR, X27

  (238) 0x420b8c MSUB	W12, W11, W10, W16

  (238) 0x420b90 LDR	X24, [X20, #32]

  (238) 0x420b94 ADD	W13, W11, W22

  (238) 0x420b98 SBFM	X25, X13, #0, #31

  (238) 0x420b9c ORR	X27, XZR, X9

  (238) 0x420ba0 ADD	W22, W12, W14

  (238) 0x420ba4 SUB	W15, W19, W22

    (239) 0x420ba8 CMP	W6, W15

    (239) 0x420bac CSEL	W2, W6, W15, #9

    (239) 0x420bb0 ADD	W15, W16, W2

    (239) 0x420bb4 STR	W15, [SP, #116]

    (239) 0x420bb8 CMP	W16, W15

    (239) 0x420bbc B.CS	420eb4

    (239) 0x420bc0 LDR	X30, [X24]

    (239) 0x420bc4 SUB	W16, W25, #1

    (239) 0x420bc8 SBFM	X17, X16, #0, #31

    (239) 0x420bcc LDR	X18, [X23]

    (239) 0x420bd0 LDR	X20, [X26]

    (239) 0x420bd4 MADD	X1, X17, X30, XZR

    (239) 0x420bd8 LDR	X6, [X28]

    (239) 0x420bdc MADD	X21, X30, X25, XZR

    (239) 0x420be0 MADD	X19, X17, X18, XZR

    (239) 0x420be4 LDR	X11, [X26, #16]

    (239) 0x420be8 MADD	X3, X18, X25, XZR

    (239) 0x420bec MADD	X9, X25, X20, XZR

    (239) 0x420bf0 LDR	X13, [X28, #16]

    (239) 0x420bf4 MADD	X10, X25, X6, XZR

    (239) 0x420bf8 LDR	X0, [X27]

    (239) 0x420bfc LDR	X5, [X23, #16]

    (239) 0x420c00 LDR	X16, [X27, #16]

    (239) 0x420c04 MADD	X30, X25, X0, XZR

    (239) 0x420c08 LDR	X4, [X24, #16]

    (239) 0x420c0c STP	X13, X11, [SP, #120]

    (239) 0x420c10 STP	X10, X9, [SP, #136]

    (239) 0x420c14 STP	X21, X3, [SP, #152]

    (239) 0x420c18 STP	X1, X19, [SP, #168]

    (239) 0x420c1c CMP	W2, #1

    (239) 0x420c20 B.EQ	420e0c

    (239) 0x420c24 SBFM	X20, X22, #0, #31

    (239) 0x420c28 MOVZ	X0, #0

    (239) 0x420c2c ADD	X8, X1, X20

    (239) 0x420c30 ADD	X12, X3, X20

    (239) 0x420c34 ADD	X14, X21, X20

    (239) 0x420c38 ADD	X7, X19, X20

    (239) 0x420c3c ADD	X1, X5, X12,LSL #3

    (239) 0x420c40 ADD	X15, X30, X20

    (239) 0x420c44 UBFM	X19, X7, #61, #60

    (239) 0x420c48 ADD	X6, X5, X7,LSL #3

    (239) 0x420c4c UBFM	X17, X15, #61, #60

    (239) 0x420c50 UBFM	X18, X8, #61, #60

    (239) 0x420c54 ADD	X7, X4, X8,LSL #3

    (239) 0x420c58 UBFM	X8, X12, #61, #60

    (239) 0x420c5c UBFM	X12, X14, #61, #60

    (239) 0x420c60 ADD	X3, X4, X14,LSL #3

    (239) 0x420c64 SUB	X21, X17, #8

    (239) 0x420c68 SUB	X14, X19, #8

    (239) 0x420c6c SUB	X15, X18, #8

    (239) 0x420c70 STP	X8, X12, [SP, #192]

    (239) 0x420c74 SUB	X8, X8, #8

    (239) 0x420c78 SUB	X12, X12, #8

    (239) 0x420c7c ADD	X10, X10, X20

    (239) 0x420c80 STR	X21, [SP, #232]

    (239) 0x420c84 ADD	X21, X9, X20

    (239) 0x420c88 UBFM	X20, X10, #61, #60

    (239) 0x420c8c ADD	X9, X4, X15

    (239) 0x420c90 STP	X8, X12, [SP, #96]

    (239) 0x420c94 ADD	X12, X11, X21,LSL #3

    (239) 0x420c98 UBFM	X21, X21, #61, #60

    (239) 0x420c9c ADD	X8, X5, X14

    (239) 0x420ca0 STP	X14, X15, [SP, #208]

    (239) 0x420ca4 ADD	X15, X13, X10,LSL #3

    (239) 0x420ca8 SUB	X13, X17, #8

    (239) 0x420cac ADD	X14, X16, X17

    (239) 0x420cb0 ADD	X13, X16, X13

    (239) 0x420cb4 LDP	X10, X11, [SP, #96]

    (239) 0x420cb8 STR	X21, [SP, #224]

    (239) 0x420cbc UBFM	W21, W2, #1, #31

    (239) 0x420cc0 STR	X20, [SP, #240]

    (239) 0x420cc4 UBFM	X20, X21, #60, #59

    (239) 0x420cc8 ADD	X10, X5, X10

    (239) 0x420ccc ADD	X11, X4, X11

    (239) 0x420cd0 TBZ	W21, #0, 420d50

    (239) 0x420cd4 LDR	X21, [SP, #96]

    (239) 0x420cd8 LDR	Q21, [X5, X19]

    (239) 0x420cdc LDP	X0, X19, [SP, #192]

    (239) 0x420ce0 LDR	Q20, [X4, X18]

    (239) 0x420ce4 LDR	Q7, [X5, X21]

    (239) 0x420ce8 LDR	X21, [SP, #104]

    (239) 0x420cec LDR	X18, [SP, #208]

    (239) 0x420cf0 LDR	Q19, [X5, X0]

    (239) 0x420cf4 MOVZ	X0, #16

    (239) 0x420cf8 LDR	Q18, [X4, X19]

    (239) 0x420cfc LDR	Q17, [X5, X18]

    (239) 0x420d00 LDP	X18, X19, [SP, #216]

    (239) 0x420d04 FMUL	V0.2D, V19.2D, V18.2D

    (239) 0x420d08 LDR	Q6, [X4, X21]

    (239) 0x420d0c LDR	Q16, [X4, X18]

    (239) 0x420d10 FMLA	V0.2D, V21.2D, V20.2D

    (239) 0x420d14 LDR	X18, [SP, #128]

    (239) 0x420d18 LDR	X21, [SP, #120]

    (239) 0x420d1c FMUL	V1.2D, V7.2D, V6.2D

    (239) 0x420d20 FMLA	V1.2D, V17.2D, V16.2D

    (239) 0x420d24 FADD	V2.2D, V0.2D, V1.2D

    (239) 0x420d28 FMUL	V3.2D, V2.2D, V30.2D

    (239) 0x420d2c STR	Q3, [X18, X19]

    (239) 0x420d30 LDR	Q5, [X16, X17]

    (239) 0x420d34 LDP	X17, X19, [SP, #232]

    (239) 0x420d38 LDR	Q4, [X16, X17]

    (239) 0x420d3c FSUB	V22.2D, V5.2D, V4.2D

    (239) 0x420d40 FADD	V23.2D, V22.2D, V3.2D

    (239) 0x420d44 STR	Q23, [X21, X19]

    (239) 0x420d48 CMP	X20, X0

    (239) 0x420d4c B.EQ	420e00

      (240) 0x420d50 LDR	Q24, [X1, X0]

      (240) 0x420d54 ADD	X18, X0, #16

      (240) 0x420d58 LDR	Q25, [X3, X0]

      (240) 0x420d5c LDR	Q28, [X10, X0]

      (240) 0x420d60 LDR	Q27, [X11, X0]

      (240) 0x420d64 LDR	Q29, [X6, X0]

      (240) 0x420d68 FMUL	V26.2D, V24.2D, V25.2D

      (240) 0x420d6c LDR	Q21, [X7, X0]

      (240) 0x420d70 LDR	Q20, [X8, X0]

      (240) 0x420d74 FMUL	V19.2D, V28.2D, V27.2D

      (240) 0x420d78 LDR	Q18, [X9, X0]

      (240) 0x420d7c FMLA	V26.2D, V29.2D, V21.2D

      (240) 0x420d80 FMLA	V19.2D, V20.2D, V18.2D

      (240) 0x420d84 FADD	V0.2D, V26.2D, V19.2D

      (240) 0x420d88 FMUL	V17.2D, V0.2D, V30.2D

      (240) 0x420d8c STR	Q17, [X12, X0]

      (240) 0x420d90 LDR	Q7, [X14, X0]

      (240) 0x420d94 LDR	Q16, [X13, X0]

      (240) 0x420d98 FSUB	V6.2D, V7.2D, V16.2D

      (240) 0x420d9c FADD	V1.2D, V6.2D, V17.2D

      (240) 0x420da0 STR	Q1, [X15, X0]

      (240) 0x420da4 ADD	X0, X0, #32

      (240) 0x420da8 LDR	Q2, [X1, X18]

      (240) 0x420dac LDR	Q3, [X3, X18]

      (240) 0x420db0 LDR	Q5, [X10, X18]

      (240) 0x420db4 LDR	Q4, [X11, X18]

      (240) 0x420db8 LDR	Q22, [X6, X18]

      (240) 0x420dbc FMUL	V23.2D, V2.2D, V3.2D

      (240) 0x420dc0 LDR	Q24, [X7, X18]

      (240) 0x420dc4 LDR	Q25, [X8, X18]

      (240) 0x420dc8 FMUL	V28.2D, V5.2D, V4.2D

      (240) 0x420dcc LDR	Q27, [X9, X18]

      (240) 0x420dd0 FMLA	V23.2D, V22.2D, V24.2D

      (240) 0x420dd4 FMLA	V28.2D, V25.2D, V27.2D

      (240) 0x420dd8 FADD	V29.2D, V23.2D, V28.2D

      (240) 0x420ddc FMUL	V26.2D, V29.2D, V30.2D

      (240) 0x420de0 STR	Q26, [X12, X18]

      (240) 0x420de4 LDR	Q21, [X14, X18]

      (240) 0x420de8 LDR	Q20, [X13, X18]

      (240) 0x420dec FSUB	V19.2D, V21.2D, V20.2D

      (240) 0x420df0 FADD	V18.2D, V19.2D, V26.2D

      (240) 0x420df4 STR	Q18, [X15, X18]

      (240) 0x420df8 CMP	X20, X0

      (240) 0x420dfc B.NE	420d50

    (239) 0x420e00 TBZ	W2, #0, 420eb0

    (239) 0x420e04 AND	W2, W2, #1951

    (239) 0x420e08 ADD	W22, W22, W2

    (239) 0x420e0c LDR	X7, [SP, #152]

    (239) 0x420e10 SUB	W6, W22, #1

    (239) 0x420e14 SBFM	X1, X22, #0, #31

    (239) 0x420e18 LDP	X12, X9, [SP, #160]

    (239) 0x420e1c SBFM	X15, X6, #0, #31

    (239) 0x420e20 ADD	X0, X30, X15

    (239) 0x420e24 ADD	X30, X30, X1

    (239) 0x420e28 LDR	X10, [SP, #176]

    (239) 0x420e2c ADD	X3, X7, X1

    (239) 0x420e30 ADD	X13, X7, X15

    (239) 0x420e34 ADD	X20, X12, X15

    (239) 0x420e38 ADD	X17, X12, X1

    (239) 0x420e3c LDR	D17, [X4, X3,LSL #3]

    (239) 0x420e40 ADD	X8, X9, X15

    (239) 0x420e44 ADD	X14, X9, X1

    (239) 0x420e48 LDR	D7, [X4, X13,LSL #3]

    (239) 0x420e4c ADD	X11, X10, X15

    (239) 0x420e50 ADD	X21, X10, X1

    (239) 0x420e54 LDR	D6, [X5, X20,LSL #3]

    (239) 0x420e58 LDR	D2, [X5, X17,LSL #3]

    (239) 0x420e5c LDR	D0, [X4, X8,LSL #3]

    (239) 0x420e60 LDR	D16, [X4, X14,LSL #3]

    (239) 0x420e64 FMUL	D1, D7, D6

    (239) 0x420e68 LDR	D3, [X5, X11,LSL #3]

    (239) 0x420e6c FMUL	D5, D17, D2

    (239) 0x420e70 LDR	D4, [X5, X21,LSL #3]

    (239) 0x420e74 LDP	X5, X18, [SP, #128]

    (239) 0x420e78 FMADD	D22, D0, D3, D1

    (239) 0x420e7c LDR	X4, [SP, #144]

    (239) 0x420e80 FMADD	D23, D16, D4, D5

    (239) 0x420e84 ADD	X2, X18, X1

    (239) 0x420e88 LDR	X22, [SP, #120]

    (239) 0x420e8c ADD	X19, X4, X1

    (239) 0x420e90 FADD	D24, D23, D22

    (239) 0x420e94 FMUL	D28, D24, D31

    (239) 0x420e98 STR	D28, [X5, X19,LSL #3]

    (239) 0x420e9c LDR	D25, [X16, X0,LSL #3]

    (239) 0x420ea0 LDR	D27, [X16, X30,LSL #3]

    (239) 0x420ea4 FSUB	D29, D27, S25

    (239) 0x420ea8 FADD	D26, D29, D28

    (239) 0x420eac STR	D26, [X22, X2,LSL #3]

    (239) 0x420eb0 LDR	W16, [SP, #116]

    (239) 0x420eb4 ADD	X25, X25, #1

    (239) 0x420eb8 LDR	W6, [SP, #184]

    (239) 0x420ebc CMP	W6, W25

    (239) 0x420ec0 B.LE	420eec

    (239) 0x420ec4 LDR	W1, [SP, #252]

    (239) 0x420ec8 LDR	W22, [SP, #188]

    (239) 0x420ecc LDR	W15, [SP, #248]

    (239) 0x420ed0 SUB	W6, W1, W16

    (239) 0x420ed4 B	420ba8

(237) 0x420ed8 LDP	X23, X24, [SP, #48]

(237) 0x420edc LDP	X19, X20, [SP, #16]

(237) 0x420ee0 LDP	X21, X22, [SP, #32]

(237) 0x420ee4 LDP	X29, X30, [SP], #256

(237) 0x420ee8 RET

  (238) 0x420eec LDP	X23, X24, [SP, #48]

  (238) 0x420ef0 LDP	X25, X26, [SP, #64]

  (238) 0x420ef4 LDP	X27, X28, [SP, #80]

  (238) 0x420ef8 LDP	X19, X20, [SP, #16]

  (238) 0x420efc LDP	X21, X22, [SP, #32]

  (238) 0x420f00 LDP	X29, X30, [SP], #256

  (238) 0x420f04 RET

  (238) 0x420f08 ADD	W6, W6, #1

  (238) 0x420f0c MOVZ	W7, #0

  (238) 0x420f10 B	420b50

0x420f14 HINT	#0

0x420f18 HINT	#0

0x420f1c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 45% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420ae0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #768]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W2, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 420edc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W3, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 420ed8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W4, W19, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W4, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W7, W6, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 420f08 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420ae0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #768]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W2, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 420edc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W3, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 420ed8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W4, W19, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W4, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W7, W6, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 420f08 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.12	2.37
▼Loop 237 - advec_mom.cpp:95-100 - exec–	0.00	0.00
▼Loop 238 - advec_mom.cpp:95-100 - exec–	0.00	0.00
▼Loop 239 - advec_mom.cpp:97-100 - exec–	0.01	0.01
○Loop 240 - advec_mom.cpp:98-100 - exec	3.11	2.35

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code