OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:71-75 [...]	Coverage (incl. loops): 2.21% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 71 - 75

--------------------------------------------------------------------------------

71: #pragma omp parallel for simd collapse(2)

72:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

73:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

74:         post_vol(i, j) = volume(i, j);

75:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4206a0 STP	X29, X30, [SP, #896]!

0x4206a4 ADD	X29, SP, #0

0x4206a8 STP	X19, X20, [SP, #16]

0x4206ac ORR	X19, XZR, X0

0x4206b0 STP	X23, X24, [SP, #48]

0x4206b4 STP	X25, X26, [SP, #64]

0x4206b8 LDP	W25, W1, [X0, #40]

0x4206bc LDP	W0, W24, [X0, #32]

0x4206c0 SUB	W26, W25, #1

0x4206c4 ADD	W23, W1, #4

0x4206c8 CMP	W26, W23

0x4206cc B.GE	420ab4

0x4206d0 STP	X21, X22, [SP, #32]

0x4206d4 SUB	W21, W23, W26

0x4206d8 STP	X27, X28, [SP, #80]

0x4206dc SUB	W28, W0, #1

0x4206e0 ADD	W27, W24, #4

0x4206e4 CMP	W28, W27

0x4206e8 B.GE	420aac

0x4206ec SUB	W2, W27, W28

0x4206f0 MADD	W22, W21, W2, WZR

0x4206f4 STR	W2, [SP, #108]

0x4206f8 BL	403890

0x4206fc ORR	W20, WZR, W0

0x420700 BL	4038c0

0x420704 UDIV	W3, W22, W20

0x420708 ORR	W4, WZR, W0

0x42070c MSUB	W5, W3, W20, W22

0x420710 CMP	W0, W5

0x420714 B.CC	420ac8

(234) 0x420718 MADD	W17, W3, W4, W5

(234) 0x42071c ADD	W6, W3, W17

(234) 0x420720 STR	W6, [SP, #120]

(234) 0x420724 CMP	W17, W6

(234) 0x420728 B.CS	420aac

(234) 0x42072c LDR	W7, [SP, #108]

(234) 0x420730 ORR	W30, WZR, W28

(234) 0x420734 ORR	W24, WZR, W23

(234) 0x420738 LDP	X21, X22, [X19]

(234) 0x42073c LDP	X19, X20, [X19, #16]

(234) 0x420740 UDIV	W9, W17, W7

(234) 0x420744 MSUB	W8, W9, W7, W17

(234) 0x420748 ADD	W10, W9, W26

(234) 0x42074c SBFM	X7, X10, #0, #31

(234) 0x420750 ADD	W8, W8, W28

(234) 0x420754 SUB	W18, W27, W8

(234) 0x420758 HINT	#0

(234) 0x42075c HINT	#0

  (235) 0x420760 CMP	W3, W18

  (235) 0x420764 CSEL	W6, W3, W18, #9

  (235) 0x420768 ADD	W16, W17, W6

  (235) 0x42076c CMP	W17, W16

  (235) 0x420770 B.CS	420a8c

  (235) 0x420774 LDR	X12, [X21]

  (235) 0x420778 LDR	X13, [X19]

  (235) 0x42077c LDR	X11, [X20]

  (235) 0x420780 MADD	X10, X7, X12, XZR

  (235) 0x420784 LDR	X14, [X22]

  (235) 0x420788 MADD	X13, X7, X13, XZR

  (235) 0x42078c LDR	X17, [X19, #16]

  (235) 0x420790 MADD	X11, X7, X11, XZR

  (235) 0x420794 LDR	X18, [X20, #16]

  (235) 0x420798 MADD	X12, X7, X14, XZR

  (235) 0x42079c LDR	X15, [X21, #16]

  (235) 0x4207a0 LDR	X23, [X22, #16]

  (235) 0x4207a4 CMP	W6, #1

  (235) 0x4207a8 B.EQ	420a50

  (235) 0x4207ac UBFM	W25, W6, #1, #31

  (235) 0x4207b0 SBFM	X1, X8, #0, #31

  (235) 0x4207b4 UBFM	X9, X25, #60, #59

  (235) 0x4207b8 ADD	X26, X10, X1

  (235) 0x4207bc SUB	X28, X9, #16

  (235) 0x4207c0 ADD	X25, X11, X1

  (235) 0x4207c4 UBFM	X4, X28, #4, #63

  (235) 0x4207c8 ADD	X27, X26, #1

  (235) 0x4207cc ADD	X3, X4, #1

  (235) 0x4207d0 ADD	X4, X18, X25,LSL #3

  (235) 0x4207d4 UBFM	X25, X25, #61, #60

  (235) 0x4207d8 UBFM	X28, X27, #61, #60

  (235) 0x4207dc ADD	X26, X12, X1

  (235) 0x4207e0 ADD	X2, X15, X27,LSL #3

  (235) 0x4207e4 ADD	X1, X13, X1

  (235) 0x4207e8 SUB	X27, X28, #8

  (235) 0x4207ec STR	X25, [SP, #112]

  (235) 0x4207f0 ADD	X5, X23, X26,LSL #3

  (235) 0x4207f4 ANDS	X14, X3, #4224

  (235) 0x4207f8 UBFM	X25, X1, #61, #60

  (235) 0x4207fc ADD	X1, X17, X1,LSL #3

  (235) 0x420800 MOVZ	X0, #0

  (235) 0x420804 ADD	X3, X15, X27

  (235) 0x420808 UBFM	X26, X26, #61, #60

  (235) 0x42080c B.EQ	42092c

  (235) 0x420810 CMP	X14, #1

  (235) 0x420814 B.EQ	420904

  (235) 0x420818 CMP	X14, #2

  (235) 0x42081c B.EQ	4208e4

  (235) 0x420820 CMP	X14, #3

  (235) 0x420824 B.EQ	4208c4

  (235) 0x420828 CMP	X14, #4

  (235) 0x42082c B.EQ	4208a4

  (235) 0x420830 CMP	X14, #5

  (235) 0x420834 B.EQ	420884

  (235) 0x420838 CMP	X14, #6

  (235) 0x42083c B.EQ	420864

  (235) 0x420840 LDR	Q0, [X23, X26]

  (235) 0x420844 MOVZ	X0, #16

  (235) 0x420848 LDR	X14, [SP, #112]

  (235) 0x42084c STR	Q0, [X18, X14]

  (235) 0x420850 LDR	Q30, [X15, X28]

  (235) 0x420854 LDR	Q31, [X15, X27]

  (235) 0x420858 FADD	V1.2D, V30.2D, V0.2D

  (235) 0x42085c FSUB	V2.2D, V1.2D, V31.2D

  (235) 0x420860 STR	Q2, [X17, X25]

  (235) 0x420864 LDR	Q3, [X5, X0]

  (235) 0x420868 STR	Q3, [X4, X0]

  (235) 0x42086c LDR	Q28, [X2, X0]

  (235) 0x420870 LDR	Q29, [X3, X0]

  (235) 0x420874 FADD	V4.2D, V28.2D, V3.2D

  (235) 0x420878 FSUB	V5.2D, V4.2D, V29.2D

  (235) 0x42087c STR	Q5, [X1, X0]

  (235) 0x420880 ADD	X0, X0, #16

  (235) 0x420884 LDR	Q6, [X5, X0]

  (235) 0x420888 STR	Q6, [X4, X0]

  (235) 0x42088c LDR	Q26, [X2, X0]

  (235) 0x420890 LDR	Q27, [X3, X0]

  (235) 0x420894 FADD	V7.2D, V26.2D, V6.2D

  (235) 0x420898 FSUB	V16.2D, V7.2D, V27.2D

  (235) 0x42089c STR	Q16, [X1, X0]

  (235) 0x4208a0 ADD	X0, X0, #16

  (235) 0x4208a4 LDR	Q17, [X5, X0]

  (235) 0x4208a8 STR	Q17, [X4, X0]

  (235) 0x4208ac LDR	Q24, [X2, X0]

  (235) 0x4208b0 LDR	Q25, [X3, X0]

  (235) 0x4208b4 FADD	V18.2D, V24.2D, V17.2D

  (235) 0x4208b8 FSUB	V19.2D, V18.2D, V25.2D

  (235) 0x4208bc STR	Q19, [X1, X0]

  (235) 0x4208c0 ADD	X0, X0, #16

  (235) 0x4208c4 LDR	Q20, [X5, X0]

  (235) 0x4208c8 STR	Q20, [X4, X0]

  (235) 0x4208cc LDR	Q22, [X2, X0]

  (235) 0x4208d0 LDR	Q23, [X3, X0]

  (235) 0x4208d4 FADD	V21.2D, V22.2D, V20.2D

  (235) 0x4208d8 FSUB	V0.2D, V21.2D, V23.2D

  (235) 0x4208dc STR	Q0, [X1, X0]

  (235) 0x4208e0 ADD	X0, X0, #16

  (235) 0x4208e4 LDR	Q30, [X5, X0]

  (235) 0x4208e8 STR	Q30, [X4, X0]

  (235) 0x4208ec LDR	Q31, [X2, X0]

  (235) 0x4208f0 LDR	Q1, [X3, X0]

  (235) 0x4208f4 FADD	V2.2D, V31.2D, V30.2D

  (235) 0x4208f8 FSUB	V3.2D, V2.2D, V1.2D

  (235) 0x4208fc STR	Q3, [X1, X0]

  (235) 0x420900 ADD	X0, X0, #16

  (235) 0x420904 LDR	Q28, [X5, X0]

  (235) 0x420908 STR	Q28, [X4, X0]

  (235) 0x42090c LDR	Q29, [X2, X0]

  (235) 0x420910 LDR	Q4, [X3, X0]

  (235) 0x420914 FADD	V5.2D, V29.2D, V28.2D

  (235) 0x420918 FSUB	V6.2D, V5.2D, V4.2D

  (235) 0x42091c STR	Q6, [X1, X0]

  (235) 0x420920 ADD	X0, X0, #16

  (235) 0x420924 CMP	X9, X0

  (235) 0x420928 B.EQ	420a44

  (235) 0x42092c STR	W24, [SP, #112]

  (235) 0x420930 STR	W30, [SP, #124]

    (236) 0x420934 LDR	Q26, [X5, X0]

    (236) 0x420938 ADD	X14, X0, #16

    (236) 0x42093c ADD	X30, X0, #32

    (236) 0x420940 ADD	X28, X0, #48

    (236) 0x420944 ADD	X27, X0, #64

    (236) 0x420948 ADD	X26, X0, #80

    (236) 0x42094c ADD	X25, X0, #96

    (236) 0x420950 ADD	X24, X0, #112

    (236) 0x420954 STR	Q26, [X4, X0]

    (236) 0x420958 LDR	Q27, [X2, X0]

    (236) 0x42095c LDR	Q7, [X3, X0]

    (236) 0x420960 FADD	V16.2D, V27.2D, V26.2D

    (236) 0x420964 FSUB	V17.2D, V16.2D, V7.2D

    (236) 0x420968 STR	Q17, [X1, X0]

    (236) 0x42096c ADD	X0, X0, #128

    (236) 0x420970 LDR	Q24, [X5, X14]

    (236) 0x420974 STR	Q24, [X4, X14]

    (236) 0x420978 LDR	Q25, [X2, X14]

    (236) 0x42097c LDR	Q18, [X3, X14]

    (236) 0x420980 FADD	V19.2D, V25.2D, V24.2D

    (236) 0x420984 FSUB	V20.2D, V19.2D, V18.2D

    (236) 0x420988 STR	Q20, [X1, X14]

    (236) 0x42098c LDR	Q21, [X5, X30]

    (236) 0x420990 STR	Q21, [X4, X30]

    (236) 0x420994 LDR	Q22, [X2, X30]

    (236) 0x420998 LDR	Q23, [X3, X30]

    (236) 0x42099c FADD	V0.2D, V22.2D, V21.2D

    (236) 0x4209a0 FSUB	V30.2D, V0.2D, V23.2D

    (236) 0x4209a4 STR	Q30, [X1, X30]

    (236) 0x4209a8 LDR	Q31, [X5, X28]

    (236) 0x4209ac STR	Q31, [X4, X28]

    (236) 0x4209b0 LDR	Q1, [X2, X28]

    (236) 0x4209b4 LDR	Q2, [X3, X28]

    (236) 0x4209b8 FADD	V3.2D, V1.2D, V31.2D

    (236) 0x4209bc FSUB	V28.2D, V3.2D, V2.2D

    (236) 0x4209c0 STR	Q28, [X1, X28]

    (236) 0x4209c4 LDR	Q29, [X5, X27]

    (236) 0x4209c8 STR	Q29, [X4, X27]

    (236) 0x4209cc LDR	Q4, [X2, X27]

    (236) 0x4209d0 LDR	Q5, [X3, X27]

    (236) 0x4209d4 FADD	V6.2D, V4.2D, V29.2D

    (236) 0x4209d8 FSUB	V26.2D, V6.2D, V5.2D

    (236) 0x4209dc STR	Q26, [X1, X27]

    (236) 0x4209e0 LDR	Q27, [X5, X26]

    (236) 0x4209e4 STR	Q27, [X4, X26]

    (236) 0x4209e8 LDR	Q7, [X2, X26]

    (236) 0x4209ec LDR	Q16, [X3, X26]

    (236) 0x4209f0 FADD	V17.2D, V7.2D, V27.2D

    (236) 0x4209f4 FSUB	V24.2D, V17.2D, V16.2D

    (236) 0x4209f8 STR	Q24, [X1, X26]

    (236) 0x4209fc LDR	Q25, [X5, X25]

    (236) 0x420a00 STR	Q25, [X4, X25]

    (236) 0x420a04 LDR	Q18, [X2, X25]

    (236) 0x420a08 LDR	Q19, [X3, X25]

    (236) 0x420a0c FADD	V20.2D, V18.2D, V25.2D

    (236) 0x420a10 FSUB	V21.2D, V20.2D, V19.2D

    (236) 0x420a14 STR	Q21, [X1, X25]

    (236) 0x420a18 LDR	Q22, [X5, X24]

    (236) 0x420a1c STR	Q22, [X4, X24]

    (236) 0x420a20 LDR	Q23, [X2, X24]

    (236) 0x420a24 LDR	Q0, [X3, X24]

    (236) 0x420a28 FADD	V30.2D, V23.2D, V22.2D

    (236) 0x420a2c FSUB	V31.2D, V30.2D, V0.2D

    (236) 0x420a30 STR	Q31, [X1, X24]

    (236) 0x420a34 CMP	X9, X0

    (236) 0x420a38 B.NE	420934

  (235) 0x420a3c LDR	W24, [SP, #112]

  (235) 0x420a40 LDR	W30, [SP, #124]

  (235) 0x420a44 TBZ	W6, #0, 420a88

  (235) 0x420a48 AND	W6, W6, #1951

  (235) 0x420a4c ADD	W8, W8, W6

  (235) 0x420a50 SBFM	X9, X8, #0, #31

  (235) 0x420a54 ADD	W2, W8, #1

  (235) 0x420a58 ADD	X5, X10, W2,SXTW

  (235) 0x420a5c ADD	X12, X12, X9

  (235) 0x420a60 ADD	X11, X11, X9

  (235) 0x420a64 ADD	X10, X10, X9

  (235) 0x420a68 ADD	X13, X13, X9

  (235) 0x420a6c LDR	D1, [X23, X12,LSL #3]

  (235) 0x420a70 STR	D1, [X18, X11,LSL #3]

  (235) 0x420a74 LDR	D2, [X15, X5,LSL #3]

  (235) 0x420a78 LDR	D3, [X15, X10,LSL #3]

  (235) 0x420a7c FSUB	D28, D2, S3

  (235) 0x420a80 FADD	D29, D28, D1

  (235) 0x420a84 STR	D29, [X17, X13,LSL #3]

  (235) 0x420a88 ORR	W17, WZR, W16

  (235) 0x420a8c ADD	X7, X7, #1

  (235) 0x420a90 CMP	W24, W7

  (235) 0x420a94 B.LE	420aac

  (235) 0x420a98 LDR	W16, [SP, #120]

  (235) 0x420a9c ORR	W8, WZR, W30

  (235) 0x420aa0 LDR	W18, [SP, #108]

  (235) 0x420aa4 SUB	W3, W16, W17

  (235) 0x420aa8 B	420760

(234) 0x420aac LDP	X21, X22, [SP, #32]

(234) 0x420ab0 LDP	X27, X28, [SP, #80]

(234) 0x420ab4 LDP	X19, X20, [SP, #16]

(234) 0x420ab8 LDP	X23, X24, [SP, #48]

(234) 0x420abc LDP	X25, X26, [SP, #64]

(234) 0x420ac0 LDP	X29, X30, [SP], #128

(234) 0x420ac4 RET

(234) 0x420ac8 ADD	W3, W3, #1

(234) 0x420acc MOVZ	W5, #0

(234) 0x420ad0 B	420718

0x420ad4 HINT	#0

0x420ad8 HINT	#0

0x420adc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 48% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4206a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W24, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W26, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W23, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 420ab4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W21, W23, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W28, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W27, W24, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W28, W27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 420aac <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W2, W27, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W22, W21, W2, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W2, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W3, W22, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W4, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W5, W3, W20, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 420ac8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4206a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W24, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W26, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W23, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 420ab4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W21, W23, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W28, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W27, W24, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W28, W27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 420aac <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W2, W27, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W22, W21, W2, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W2, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W3, W22, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W4, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W5, W3, W20, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 420ac8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.21	1.68
▼Loop 234 - advec_mom.cpp:71-75 - exec–	0.00	0.00
▼Loop 235 - advec_mom.cpp:73-75 - exec–	0.00	0.01
○Loop 236 - advec_mom.cpp:74-75 - exec	2.21	1.67

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code