OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:62-66 [...]	Coverage (incl. loops): 2.29% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 62 - 66

--------------------------------------------------------------------------------

62: #pragma omp parallel for simd collapse(2)

63:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

64:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

65:         post_vol(i, j) = volume(i, j);

66:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x420240 STP	X29, X30, [SP, #896]!

0x420244 ADD	X29, SP, #0

0x420248 STP	X19, X20, [SP, #16]

0x42024c ORR	X19, XZR, X0

0x420250 STP	X23, X24, [SP, #48]

0x420254 LDP	W23, W1, [X0, #40]

0x420258 LDP	W0, W3, [X0, #32]

0x42025c ADD	W2, W1, #4

0x420260 SUB	W23, W23, #1

0x420264 SUB	W4, W0, #1

0x420268 STP	W2, W4, [SP, #108]

0x42026c CMP	W23, W2

0x420270 B.GE	42066c

0x420274 ADD	W24, W3, #4

0x420278 STP	X21, X22, [SP, #32]

0x42027c SUB	W21, W2, W23

0x420280 CMP	W4, W24

0x420284 B.GE	42067c

0x420288 SUB	W5, W24, W4

0x42028c MADD	W22, W21, W5, WZR

0x420290 STR	W5, [SP, #116]

0x420294 BL	403890

0x420298 ORR	W20, WZR, W0

0x42029c BL	4038c0

0x4202a0 UDIV	W7, W22, W20

0x4202a4 ORR	W6, WZR, W0

0x4202a8 MSUB	W8, W7, W20, W22

0x4202ac CMP	W0, W8

0x4202b0 B.CC	420690

  (229) 0x4202b4 MADD	W16, W7, W6, W8

  (229) 0x4202b8 ADD	W9, W7, W16

  (229) 0x4202bc STR	W9, [SP, #120]

  (229) 0x4202c0 CMP	W16, W9

  (229) 0x4202c4 B.CS	42067c

(230) 0x4202c8 LDP	W10, W11, [SP, #112]

(230) 0x4202cc STP	X25, X26, [SP, #64]

(230) 0x4202d0 STP	X27, X28, [SP, #80]

(230) 0x4202d4 UDIV	W12, W16, W11

(230) 0x4202d8 LDP	X21, X22, [X19]

(230) 0x4202dc LDP	X19, X20, [X19, #16]

(230) 0x4202e0 MSUB	W13, W12, W11, W16

(230) 0x4202e4 ADD	W14, W12, W23

(230) 0x4202e8 SBFM	X4, X14, #0, #31

(230) 0x4202ec ADD	W23, W13, W10

(230) 0x4202f0 SUB	W24, W24, W23

(230) 0x4202f4 CMP	W7, W24

(230) 0x4202f8 CSEL	W6, W7, W24, #9

(230) 0x4202fc ADD	W15, W16, W6

(230) 0x420300 CMP	W16, W15

(230) 0x420304 B.CS	420644

  (231) 0x420308 LDR	X25, [X21]

  (231) 0x42030c ADD	X24, X4, #1

  (231) 0x420310 LDR	X17, [X19]

  (231) 0x420314 LDR	X18, [X20]

  (231) 0x420318 MADD	X13, X4, X25, X25

  (231) 0x42031c LDR	X26, [X22]

  (231) 0x420320 MADD	X7, X4, X17, XZR

  (231) 0x420324 LDR	X16, [X19, #16]

  (231) 0x420328 SUB	X8, X13, X25

  (231) 0x42032c MADD	X10, X4, X18, XZR

  (231) 0x420330 LDR	X17, [X20, #16]

  (231) 0x420334 MADD	X11, X4, X26, XZR

  (231) 0x420338 LDR	X12, [X21, #16]

  (231) 0x42033c LDR	X18, [X22, #16]

  (231) 0x420340 CMP	W6, #1

  (231) 0x420344 B.EQ	4205dc

  (231) 0x420348 UBFM	W27, W6, #1, #31

  (231) 0x42034c SBFM	X1, X23, #0, #31

  (231) 0x420350 UBFM	X9, X27, #60, #59

  (231) 0x420354 ADD	X30, X11, X1

  (231) 0x420358 SUB	X3, X9, #16

  (231) 0x42035c ADD	X28, X10, X1

  (231) 0x420360 ADD	X5, X18, X30,LSL #3

  (231) 0x420364 UBFM	X2, X3, #4, #63

  (231) 0x420368 ADD	X27, X13, X1

  (231) 0x42036c ADD	X4, X17, X28,LSL #3

  (231) 0x420370 ADD	X14, X2, #1

  (231) 0x420374 ADD	X26, X8, X1

  (231) 0x420378 ADD	X3, X12, X27,LSL #3

  (231) 0x42037c ANDS	X25, X14, #4224

  (231) 0x420380 ADD	X14, X7, X1

  (231) 0x420384 ADD	X2, X12, X26,LSL #3

  (231) 0x420388 ADD	X1, X16, X14,LSL #3

  (231) 0x42038c MOVZ	X0, #0

  (231) 0x420390 UBFM	X30, X30, #61, #60

  (231) 0x420394 UBFM	X28, X28, #61, #60

  (231) 0x420398 UBFM	X27, X27, #61, #60

  (231) 0x42039c UBFM	X26, X26, #61, #60

  (231) 0x4203a0 UBFM	X14, X14, #61, #60

  (231) 0x4203a4 B.EQ	4204c0

  (231) 0x4203a8 CMP	X25, #1

  (231) 0x4203ac B.EQ	420498

  (231) 0x4203b0 CMP	X25, #2

  (231) 0x4203b4 B.EQ	420478

  (231) 0x4203b8 CMP	X25, #3

  (231) 0x4203bc B.EQ	420458

  (231) 0x4203c0 CMP	X25, #4

  (231) 0x4203c4 B.EQ	420438

  (231) 0x4203c8 CMP	X25, #5

  (231) 0x4203cc B.EQ	420418

  (231) 0x4203d0 CMP	X25, #6

  (231) 0x4203d4 B.EQ	4203f8

  (231) 0x4203d8 LDR	Q0, [X18, X30]

  (231) 0x4203dc MOVZ	X0, #16

  (231) 0x4203e0 STR	Q0, [X17, X28]

  (231) 0x4203e4 LDR	Q30, [X12, X27]

  (231) 0x4203e8 LDR	Q31, [X12, X26]

  (231) 0x4203ec FADD	V1.2D, V30.2D, V0.2D

  (231) 0x4203f0 FSUB	V2.2D, V1.2D, V31.2D

  (231) 0x4203f4 STR	Q2, [X16, X14]

  (231) 0x4203f8 LDR	Q3, [X5, X0]

  (231) 0x4203fc STR	Q3, [X4, X0]

  (231) 0x420400 LDR	Q28, [X3, X0]

  (231) 0x420404 LDR	Q29, [X2, X0]

  (231) 0x420408 FADD	V4.2D, V28.2D, V3.2D

  (231) 0x42040c FSUB	V5.2D, V4.2D, V29.2D

  (231) 0x420410 STR	Q5, [X1, X0]

  (231) 0x420414 ADD	X0, X0, #16

  (231) 0x420418 LDR	Q6, [X5, X0]

  (231) 0x42041c STR	Q6, [X4, X0]

  (231) 0x420420 LDR	Q26, [X3, X0]

  (231) 0x420424 LDR	Q27, [X2, X0]

  (231) 0x420428 FADD	V7.2D, V26.2D, V6.2D

  (231) 0x42042c FSUB	V16.2D, V7.2D, V27.2D

  (231) 0x420430 STR	Q16, [X1, X0]

  (231) 0x420434 ADD	X0, X0, #16

  (231) 0x420438 LDR	Q17, [X5, X0]

  (231) 0x42043c STR	Q17, [X4, X0]

  (231) 0x420440 LDR	Q24, [X3, X0]

  (231) 0x420444 LDR	Q25, [X2, X0]

  (231) 0x420448 FADD	V18.2D, V24.2D, V17.2D

  (231) 0x42044c FSUB	V19.2D, V18.2D, V25.2D

  (231) 0x420450 STR	Q19, [X1, X0]

  (231) 0x420454 ADD	X0, X0, #16

  (231) 0x420458 LDR	Q20, [X5, X0]

  (231) 0x42045c STR	Q20, [X4, X0]

  (231) 0x420460 LDR	Q22, [X3, X0]

  (231) 0x420464 LDR	Q23, [X2, X0]

  (231) 0x420468 FADD	V21.2D, V22.2D, V20.2D

  (231) 0x42046c FSUB	V0.2D, V21.2D, V23.2D

  (231) 0x420470 STR	Q0, [X1, X0]

  (231) 0x420474 ADD	X0, X0, #16

  (231) 0x420478 LDR	Q30, [X5, X0]

  (231) 0x42047c STR	Q30, [X4, X0]

  (231) 0x420480 LDR	Q31, [X3, X0]

  (231) 0x420484 LDR	Q1, [X2, X0]

  (231) 0x420488 FADD	V2.2D, V31.2D, V30.2D

  (231) 0x42048c FSUB	V3.2D, V2.2D, V1.2D

  (231) 0x420490 STR	Q3, [X1, X0]

  (231) 0x420494 ADD	X0, X0, #16

  (231) 0x420498 LDR	Q28, [X5, X0]

  (231) 0x42049c STR	Q28, [X4, X0]

  (231) 0x4204a0 LDR	Q29, [X3, X0]

  (231) 0x4204a4 LDR	Q4, [X2, X0]

  (231) 0x4204a8 FADD	V5.2D, V29.2D, V28.2D

  (231) 0x4204ac FSUB	V6.2D, V5.2D, V4.2D

  (231) 0x4204b0 STR	Q6, [X1, X0]

  (231) 0x4204b4 ADD	X0, X0, #16

  (231) 0x4204b8 CMP	X9, X0

  (231) 0x4204bc B.EQ	4205d0

  (231) 0x4204c0 STR	W6, [SP, #124]

    (232) 0x4204c4 LDR	Q26, [X5, X0]

    (232) 0x4204c8 ADD	X6, X0, #16

    (232) 0x4204cc ADD	X30, X0, #32

    (232) 0x4204d0 ADD	X28, X0, #48

    (232) 0x4204d4 ADD	X27, X0, #64

    (232) 0x4204d8 ADD	X26, X0, #80

    (232) 0x4204dc ADD	X25, X0, #96

    (232) 0x4204e0 ADD	X14, X0, #112

    (232) 0x4204e4 STR	Q26, [X4, X0]

    (232) 0x4204e8 LDR	Q27, [X3, X0]

    (232) 0x4204ec LDR	Q7, [X2, X0]

    (232) 0x4204f0 FADD	V16.2D, V27.2D, V26.2D

    (232) 0x4204f4 FSUB	V17.2D, V16.2D, V7.2D

    (232) 0x4204f8 STR	Q17, [X1, X0]

    (232) 0x4204fc ADD	X0, X0, #128

    (232) 0x420500 LDR	Q24, [X5, X6]

    (232) 0x420504 STR	Q24, [X4, X6]

    (232) 0x420508 LDR	Q25, [X3, X6]

    (232) 0x42050c LDR	Q18, [X2, X6]

    (232) 0x420510 FADD	V19.2D, V25.2D, V24.2D

    (232) 0x420514 FSUB	V20.2D, V19.2D, V18.2D

    (232) 0x420518 STR	Q20, [X1, X6]

    (232) 0x42051c LDR	Q21, [X5, X30]

    (232) 0x420520 STR	Q21, [X4, X30]

    (232) 0x420524 LDR	Q22, [X3, X30]

    (232) 0x420528 LDR	Q23, [X2, X30]

    (232) 0x42052c FADD	V0.2D, V22.2D, V21.2D

    (232) 0x420530 FSUB	V30.2D, V0.2D, V23.2D

    (232) 0x420534 STR	Q30, [X1, X30]

    (232) 0x420538 LDR	Q31, [X5, X28]

    (232) 0x42053c STR	Q31, [X4, X28]

    (232) 0x420540 LDR	Q1, [X3, X28]

    (232) 0x420544 LDR	Q2, [X2, X28]

    (232) 0x420548 FADD	V3.2D, V1.2D, V31.2D

    (232) 0x42054c FSUB	V28.2D, V3.2D, V2.2D

    (232) 0x420550 STR	Q28, [X1, X28]

    (232) 0x420554 LDR	Q29, [X5, X27]

    (232) 0x420558 STR	Q29, [X4, X27]

    (232) 0x42055c LDR	Q4, [X3, X27]

    (232) 0x420560 LDR	Q5, [X2, X27]

    (232) 0x420564 FADD	V6.2D, V4.2D, V29.2D

    (232) 0x420568 FSUB	V26.2D, V6.2D, V5.2D

    (232) 0x42056c STR	Q26, [X1, X27]

    (232) 0x420570 LDR	Q27, [X5, X26]

    (232) 0x420574 STR	Q27, [X4, X26]

    (232) 0x420578 LDR	Q7, [X3, X26]

    (232) 0x42057c LDR	Q16, [X2, X26]

    (232) 0x420580 FADD	V17.2D, V7.2D, V27.2D

    (232) 0x420584 FSUB	V24.2D, V17.2D, V16.2D

    (232) 0x420588 STR	Q24, [X1, X26]

    (232) 0x42058c LDR	Q25, [X5, X25]

    (232) 0x420590 STR	Q25, [X4, X25]

    (232) 0x420594 LDR	Q18, [X3, X25]

    (232) 0x420598 LDR	Q19, [X2, X25]

    (232) 0x42059c FADD	V20.2D, V18.2D, V25.2D

    (232) 0x4205a0 FSUB	V21.2D, V20.2D, V19.2D

    (232) 0x4205a4 STR	Q21, [X1, X25]

    (232) 0x4205a8 LDR	Q22, [X5, X14]

    (232) 0x4205ac STR	Q22, [X4, X14]

    (232) 0x4205b0 LDR	Q23, [X3, X14]

    (232) 0x4205b4 LDR	Q0, [X2, X14]

    (232) 0x4205b8 FADD	V30.2D, V23.2D, V22.2D

    (232) 0x4205bc FSUB	V31.2D, V30.2D, V0.2D

    (232) 0x4205c0 STR	Q31, [X1, X14]

    (232) 0x4205c4 CMP	X9, X0

    (232) 0x4205c8 B.NE	4204c4

  (231) 0x4205cc LDR	W6, [SP, #124]

  (231) 0x4205d0 TBZ	W6, #0, 420610

  (231) 0x4205d4 AND	W9, W6, #1951

  (231) 0x4205d8 ADD	W23, W23, W9

  (231) 0x4205dc SBFM	X5, X23, #0, #31

  (231) 0x4205e0 ADD	X11, X11, X5

  (231) 0x4205e4 ADD	X10, X10, X5

  (231) 0x4205e8 ADD	X13, X13, X5

  (231) 0x4205ec ADD	X8, X8, X5

  (231) 0x4205f0 LDR	D1, [X18, X11,LSL #3]

  (231) 0x4205f4 ADD	X7, X7, X5

  (231) 0x4205f8 STR	D1, [X17, X10,LSL #3]

  (231) 0x4205fc LDR	D2, [X12, X13,LSL #3]

  (231) 0x420600 LDR	D3, [X12, X8,LSL #3]

  (231) 0x420604 FADD	D28, D1, D2

  (231) 0x420608 FSUB	D29, D28, S3

  (231) 0x42060c STR	D29, [X16, X7,LSL #3]

  (231) 0x420610 ORR	W16, WZR, W15

  (231) 0x420614 LDR	W15, [SP, #108]

  (231) 0x420618 ORR	X4, XZR, X24

  (231) 0x42061c CMP	W15, W24

  (231) 0x420620 B.LE	420660

  (231) 0x420624 LDR	W17, [SP, #120]

  (231) 0x420628 LDP	W23, W24, [SP, #112]

  (231) 0x42062c SUB	W7, W17, W16

  (231) 0x420630 CMP	W7, W24

  (231) 0x420634 CSEL	W6, W7, W24, #9

  (231) 0x420638 ADD	W15, W16, W6

  (231) 0x42063c CMP	W16, W15

  (231) 0x420640 B.CC	420308

  (233) 0x420644 LDR	W15, [SP, #108]

  (233) 0x420648 ADD	X24, X4, #1

  (233) 0x42064c ORR	X4, XZR, X24

  (233) 0x420650 CMP	W15, W24

  (233) 0x420654 B.GT	420624

(230) 0x420658 HINT	#0

(230) 0x42065c HINT	#0

(230) 0x420660 LDP	X21, X22, [SP, #32]

(230) 0x420664 LDP	X25, X26, [SP, #64]

(230) 0x420668 LDP	X27, X28, [SP, #80]

(230) 0x42066c LDP	X19, X20, [SP, #16]

(230) 0x420670 LDP	X23, X24, [SP, #48]

(230) 0x420674 LDP	X29, X30, [SP], #128

(230) 0x420678 RET

  (229) 0x42067c LDP	X21, X22, [SP, #32]

  (229) 0x420680 LDP	X19, X20, [SP, #16]

  (229) 0x420684 LDP	X23, X24, [SP, #48]

  (229) 0x420688 LDP	X29, X30, [SP], #128

  (229) 0x42068c RET

  (229) 0x420690 ADD	W7, W7, #1

  (229) 0x420694 MOVZ	W8, #0

  (229) 0x420698 B	4202b4

0x42069c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.94+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:62-66
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:62-66
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420240

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W3, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W4, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42066c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x42c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W24, W3, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W21, W2, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42067c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W24, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W22, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W22, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W20, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 420690 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:62-66
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:62-66
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420240

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W3, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W4, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42066c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x42c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W24, W3, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W21, W2, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42067c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W24, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W22, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W22, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W20, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 420690 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.29	1.74
▼Loop 230 - advec_mom.cpp:62-66 - exec–	0.00	0.00
▼Loop 231 - advec_mom.cpp:64-66 - exec–	0.00	0.01
○Loop 232 - advec_mom.cpp:65-66 - exec	2.29	1.72
○Loop 233 - advec_mom.cpp:64-64 - exec	0.00	0.00
○Loop 229 - advec_mom.cpp:62-64 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code