OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:53-57 [...]	Coverage (incl. loops): 2.83% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 53 - 57

--------------------------------------------------------------------------------

53: #pragma omp parallel for simd collapse(2)

54:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

55:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

56:         post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

57:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41fe24 STP	X29, X30, [SP, #848]!

0x41fe28 ADD	X29, SP, #0

0x41fe2c STP	X19, X20, [SP, #16]

0x41fe30 ORR	X19, XZR, X0

0x41fe34 STP	X23, X24, [SP, #48]

0x41fe38 LDP	W23, W1, [X0, #48]

0x41fe3c LDP	W0, W2, [X0, #40]

0x41fe40 ADD	W3, W1, #4

0x41fe44 SUB	W23, W23, #1

0x41fe48 SUB	W4, W0, #1

0x41fe4c STP	W3, W4, [SP, #136]

0x41fe50 CMP	W23, W3

0x41fe54 B.GE	42020c

0x41fe58 STP	X21, X22, [SP, #32]

0x41fe5c ADD	W22, W2, #4

0x41fe60 SUB	W21, W3, W23

0x41fe64 CMP	W4, W22

0x41fe68 B.GE	42021c

0x41fe6c SUB	W5, W22, W4

0x41fe70 MADD	W24, W21, W5, WZR

0x41fe74 STR	W5, [SP, #144]

0x41fe78 BL	403890

0x41fe7c ORR	W20, WZR, W0

0x41fe80 BL	4038c0

0x41fe84 UDIV	W7, W24, W20

0x41fe88 ORR	W6, WZR, W0

0x41fe8c MSUB	W8, W7, W20, W24

0x41fe90 CMP	W0, W8

0x41fe94 B.CC	420230

  (224) 0x41fe98 MADD	W1, W7, W6, W8

  (224) 0x41fe9c ADD	W9, W7, W1

  (224) 0x41fea0 STR	W9, [SP, #148]

  (224) 0x41fea4 CMP	W1, W9

  (224) 0x41fea8 B.CS	42021c

(225) 0x41feac LDP	W10, W11, [SP, #140]

(225) 0x41feb0 STP	X27, X28, [SP, #80]

(225) 0x41feb4 STP	X25, X26, [SP, #64]

(225) 0x41feb8 UDIV	W12, W1, W11

(225) 0x41febc LDR	X27, [X19, #32]

(225) 0x41fec0 LDP	X25, X20, [X19]

(225) 0x41fec4 LDP	X26, X24, [X19, #16]

(225) 0x41fec8 MSUB	W13, W12, W11, W1

(225) 0x41fecc ADD	W14, W12, W23

(225) 0x41fed0 SBFM	X15, X14, #0, #31

(225) 0x41fed4 ADD	W28, W13, W10

(225) 0x41fed8 SUB	W22, W22, W28

(225) 0x41fedc CMP	W7, W22

(225) 0x41fee0 CSEL	W3, W7, W22, #9

(225) 0x41fee4 ADD	W19, W1, W3

(225) 0x41fee8 CMP	W1, W19

(225) 0x41feec B.CS	4201e0

  (226) 0x41fef0 LDR	X17, [X20]

  (226) 0x41fef4 ADD	X16, X15, #1

  (226) 0x41fef8 LDR	X30, [X27]

  (226) 0x41fefc LDR	X18, [X25]

  (226) 0x41ff00 MADD	X12, X15, X17, X17

  (226) 0x41ff04 LDR	X13, [X20, #16]

  (226) 0x41ff08 MADD	X4, X15, X30, XZR

  (226) 0x41ff0c SUB	X6, X12, X17

  (226) 0x41ff10 LDR	X22, [X24, #16]

  (226) 0x41ff14 MADD	X11, X15, X18, XZR

  (226) 0x41ff18 LDR	X14, [X25, #16]

  (226) 0x41ff1c LDR	X21, [X26, #16]

  (226) 0x41ff20 LDR	X23, [X27, #16]

  (226) 0x41ff24 STP	X16, X6, [SP, #104]

  (226) 0x41ff28 LDR	X1, [X26]

  (226) 0x41ff2c MADD	X5, X15, X1, XZR

  (226) 0x41ff30 STP	X4, X5, [SP, #120]

  (226) 0x41ff34 LDR	X2, [X24]

  (226) 0x41ff38 MADD	X30, X15, X2, XZR

  (226) 0x41ff3c CMP	W3, #1

  (226) 0x41ff40 B.EQ	42014c

  (226) 0x41ff44 SBFM	X1, X28, #0, #31

  (226) 0x41ff48 UBFM	W7, W3, #1, #31

  (226) 0x41ff4c ADD	X8, X11, X1

  (226) 0x41ff50 UBFM	X10, X7, #60, #59

  (226) 0x41ff54 ADD	X15, X8, #1

  (226) 0x41ff58 SUB	X9, X10, #16

  (226) 0x41ff5c UBFM	X16, X9, #4, #63

  (226) 0x41ff60 UBFM	X7, X15, #61, #60

  (226) 0x41ff64 ADD	X2, X14, X15,LSL #3

  (226) 0x41ff68 ADD	X4, X4, X1

  (226) 0x41ff6c ADD	X15, X6, X1

  (226) 0x41ff70 ADD	X17, X16, #1

  (226) 0x41ff74 ADD	X6, X23, X4,LSL #3

  (226) 0x41ff78 STR	X7, [SP, #152]

  (226) 0x41ff7c SUB	X7, X7, #8

  (226) 0x41ff80 ANDS	X9, X17, #4160

  (226) 0x41ff84 UBFM	X17, X4, #61, #60

  (226) 0x41ff88 ADD	X4, X13, X15,LSL #3

  (226) 0x41ff8c UBFM	X15, X15, #61, #60

  (226) 0x41ff90 ADD	X18, X5, X1

  (226) 0x41ff94 ADD	X16, X12, X1

  (226) 0x41ff98 ADD	X1, X30, X1

  (226) 0x41ff9c ADD	X8, X21, X18,LSL #3

  (226) 0x41ffa0 STP	X7, X15, [SP, #160]

  (226) 0x41ffa4 ADD	X5, X13, X16,LSL #3

  (226) 0x41ffa8 UBFM	X15, X1, #61, #60

  (226) 0x41ffac MOVZ	X0, #0

  (226) 0x41ffb0 ADD	X1, X22, X1,LSL #3

  (226) 0x41ffb4 UBFM	X18, X18, #61, #60

  (226) 0x41ffb8 UBFM	X16, X16, #61, #60

  (226) 0x41ffbc ADD	X7, X14, X7

  (226) 0x41ffc0 B.EQ	420078

  (226) 0x41ffc4 CMP	X9, #1

  (226) 0x41ffc8 B.EQ	420040

  (226) 0x41ffcc CMP	X9, #2

  (226) 0x41ffd0 B.EQ	420010

  (226) 0x41ffd4 LDR	X9, [SP, #152]

  (226) 0x41ffd8 MOVZ	X0, #16

  (226) 0x41ffdc LDR	Q1, [X21, X18]

  (226) 0x41ffe0 LDR	X18, [SP, #160]

  (226) 0x41ffe4 LDR	Q0, [X14, X9]

  (226) 0x41ffe8 LDR	Q29, [X14, X18]

  (226) 0x41ffec FADD	V2.2D, V1.2D, V0.2D

  (226) 0x41fff0 FSUB	V3.2D, V2.2D, V29.2D

  (226) 0x41fff4 STR	Q3, [X23, X17]

  (226) 0x41fff8 LDR	X17, [SP, #168]

  (226) 0x41fffc LDR	Q31, [X13, X16]

  (226) 0x420000 LDR	Q30, [X13, X17]

  (226) 0x420004 FSUB	V4.2D, V31.2D, V30.2D

  (226) 0x420008 FADD	V5.2D, V4.2D, V3.2D

  (226) 0x42000c STR	Q5, [X22, X15]

  (226) 0x420010 LDR	Q6, [X8, X0]

  (226) 0x420014 LDR	Q7, [X2, X0]

  (226) 0x420018 LDR	Q26, [X7, X0]

  (226) 0x42001c FADD	V16.2D, V6.2D, V7.2D

  (226) 0x420020 FSUB	V17.2D, V16.2D, V26.2D

  (226) 0x420024 STR	Q17, [X6, X0]

  (226) 0x420028 LDR	Q28, [X5, X0]

  (226) 0x42002c LDR	Q27, [X4, X0]

  (226) 0x420030 FSUB	V18.2D, V28.2D, V27.2D

  (226) 0x420034 FADD	V19.2D, V18.2D, V17.2D

  (226) 0x420038 STR	Q19, [X1, X0]

  (226) 0x42003c ADD	X0, X0, #16

  (226) 0x420040 LDR	Q20, [X8, X0]

  (226) 0x420044 LDR	Q21, [X2, X0]

  (226) 0x420048 LDR	Q23, [X7, X0]

  (226) 0x42004c FADD	V22.2D, V20.2D, V21.2D

  (226) 0x420050 FSUB	V1.2D, V22.2D, V23.2D

  (226) 0x420054 STR	Q1, [X6, X0]

  (226) 0x420058 LDR	Q25, [X5, X0]

  (226) 0x42005c LDR	Q24, [X4, X0]

  (226) 0x420060 FSUB	V0.2D, V25.2D, V24.2D

  (226) 0x420064 FADD	V2.2D, V0.2D, V1.2D

  (226) 0x420068 STR	Q2, [X1, X0]

  (226) 0x42006c ADD	X0, X0, #16

  (226) 0x420070 CMP	X10, X0

  (226) 0x420074 B.EQ	420140

    (227) 0x420078 LDR	Q29, [X8, X0]

    (227) 0x42007c ADD	X9, X0, #16

    (227) 0x420080 ADD	X16, X0, #32

    (227) 0x420084 ADD	X18, X0, #48

    (227) 0x420088 LDR	Q3, [X2, X0]

    (227) 0x42008c LDR	Q31, [X7, X0]

    (227) 0x420090 FADD	V30.2D, V29.2D, V3.2D

    (227) 0x420094 FSUB	V4.2D, V30.2D, V31.2D

    (227) 0x420098 STR	Q4, [X6, X0]

    (227) 0x42009c LDR	Q5, [X5, X0]

    (227) 0x4200a0 LDR	Q6, [X4, X0]

    (227) 0x4200a4 FSUB	V7.2D, V5.2D, V6.2D

    (227) 0x4200a8 FADD	V26.2D, V7.2D, V4.2D

    (227) 0x4200ac STR	Q26, [X1, X0]

    (227) 0x4200b0 ADD	X0, X0, #64

    (227) 0x4200b4 LDR	Q16, [X8, X9]

    (227) 0x4200b8 LDR	Q17, [X2, X9]

    (227) 0x4200bc LDR	Q28, [X7, X9]

    (227) 0x4200c0 FADD	V27.2D, V16.2D, V17.2D

    (227) 0x4200c4 FSUB	V18.2D, V27.2D, V28.2D

    (227) 0x4200c8 STR	Q18, [X6, X9]

    (227) 0x4200cc LDR	Q19, [X5, X9]

    (227) 0x4200d0 LDR	Q20, [X4, X9]

    (227) 0x4200d4 FSUB	V21.2D, V19.2D, V20.2D

    (227) 0x4200d8 FADD	V23.2D, V21.2D, V18.2D

    (227) 0x4200dc STR	Q23, [X1, X9]

    (227) 0x4200e0 LDR	Q22, [X8, X16]

    (227) 0x4200e4 LDR	Q1, [X2, X16]

    (227) 0x4200e8 LDR	Q25, [X7, X16]

    (227) 0x4200ec FADD	V24.2D, V22.2D, V1.2D

    (227) 0x4200f0 FSUB	V0.2D, V24.2D, V25.2D

    (227) 0x4200f4 STR	Q0, [X6, X16]

    (227) 0x4200f8 LDR	Q2, [X5, X16]

    (227) 0x4200fc LDR	Q29, [X4, X16]

    (227) 0x420100 FSUB	V3.2D, V2.2D, V29.2D

    (227) 0x420104 FADD	V31.2D, V3.2D, V0.2D

    (227) 0x420108 STR	Q31, [X1, X16]

    (227) 0x42010c LDR	Q30, [X8, X18]

    (227) 0x420110 LDR	Q4, [X2, X18]

    (227) 0x420114 LDR	Q5, [X7, X18]

    (227) 0x420118 FADD	V6.2D, V30.2D, V4.2D

    (227) 0x42011c FSUB	V7.2D, V6.2D, V5.2D

    (227) 0x420120 STR	Q7, [X6, X18]

    (227) 0x420124 LDR	Q26, [X5, X18]

    (227) 0x420128 LDR	Q16, [X4, X18]

    (227) 0x42012c FSUB	V17.2D, V26.2D, V16.2D

    (227) 0x420130 FADD	V28.2D, V17.2D, V7.2D

    (227) 0x420134 STR	Q28, [X1, X18]

    (227) 0x420138 CMP	X10, X0

    (227) 0x42013c B.NE	420078

  (226) 0x420140 TBZ	W3, #0, 4201a8

  (226) 0x420144 AND	W3, W3, #1951

  (226) 0x420148 ADD	W28, W28, W3

  (226) 0x42014c SBFM	X10, X28, #0, #31

  (226) 0x420150 ADD	W2, W28, #1

  (226) 0x420154 ADD	X8, X11, W2,SXTW

  (226) 0x420158 LDR	D27, [X14, X8,LSL #3]

  (226) 0x42015c ADD	X11, X11, X10

  (226) 0x420160 ADD	X12, X12, X10

  (226) 0x420164 ADD	X30, X30, X10

  (226) 0x420168 LDR	D18, [X14, X11,LSL #3]

  (226) 0x42016c LDR	X14, [SP, #128]

  (226) 0x420170 FSUB	D19, D27, S18

  (226) 0x420174 ADD	X6, X14, X10

  (226) 0x420178 LDR	D20, [X21, X6,LSL #3]

  (226) 0x42017c LDR	X21, [SP, #120]

  (226) 0x420180 FADD	D21, D19, D20

  (226) 0x420184 ADD	X5, X21, X10

  (226) 0x420188 STR	D21, [X23, X5,LSL #3]

  (226) 0x42018c LDR	X23, [SP, #112]

  (226) 0x420190 LDR	D23, [X13, X12,LSL #3]

  (226) 0x420194 ADD	X4, X23, X10

  (226) 0x420198 LDR	D22, [X13, X4,LSL #3]

  (226) 0x42019c FSUB	D1, D23, S22

  (226) 0x4201a0 FADD	D25, D1, D21

  (226) 0x4201a4 STR	D25, [X22, X30,LSL #3]

  (226) 0x4201a8 LDR	X15, [SP, #104]

  (226) 0x4201ac ORR	W1, WZR, W19

  (226) 0x4201b0 LDR	W19, [SP, #136]

  (226) 0x4201b4 CMP	W19, W15

  (226) 0x4201b8 B.LE	420200

  (226) 0x4201bc LDR	W13, [SP, #148]

  (226) 0x4201c0 LDR	W22, [SP, #144]

  (226) 0x4201c4 LDR	W28, [SP, #140]

  (226) 0x4201c8 SUB	W7, W13, W1

  (226) 0x4201cc CMP	W7, W22

  (226) 0x4201d0 CSEL	W3, W7, W22, #9

  (226) 0x4201d4 ADD	W19, W1, W3

  (226) 0x4201d8 CMP	W1, W19

  (226) 0x4201dc B.CC	41fef0

  (228) 0x4201e0 ADD	X15, X15, #1

  (228) 0x4201e4 LDR	W19, [SP, #136]

  (228) 0x4201e8 STR	X15, [SP, #104]

  (228) 0x4201ec LDR	X15, [SP, #104]

  (228) 0x4201f0 CMP	W19, W15

  (228) 0x4201f4 B.GT	4201bc

(225) 0x4201f8 HINT	#0

(225) 0x4201fc HINT	#0

(225) 0x420200 LDP	X21, X22, [SP, #32]

(225) 0x420204 LDP	X25, X26, [SP, #64]

(225) 0x420208 LDP	X27, X28, [SP, #80]

(225) 0x42020c LDP	X19, X20, [SP, #16]

(225) 0x420210 LDP	X23, X24, [SP, #48]

(225) 0x420214 LDP	X29, X30, [SP], #176

(225) 0x420218 RET

  (224) 0x42021c LDP	X21, X22, [SP, #32]

  (224) 0x420220 LDP	X19, X20, [SP, #16]

  (224) 0x420224 LDP	X23, X24, [SP, #48]

  (224) 0x420228 LDP	X29, X30, [SP], #176

  (224) 0x42022c RET

  (224) 0x420230 ADD	W7, W7, #1

  (224) 0x420234 MOVZ	W8, #0

  (224) 0x420238 B	41fe98

0x42023c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-57
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fe24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42020c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42021c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 420230 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-57
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fe24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42020c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42021c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 420230 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.83	2.14
▼Loop 225 - advec_mom.cpp:53-57 - exec–	0.00	0.00
▼Loop 226 - advec_mom.cpp:55-57 - exec–	0.00	0.01
○Loop 227 - advec_mom.cpp:56-57 - exec	2.82	2.13
○Loop 228 - advec_mom.cpp:55-55 - exec	0.00	0.01
○Loop 224 - advec_mom.cpp:53-55 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code