OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:44-48 [...]	Coverage (incl. loops): 2.91% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:         post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

48:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41fa00 STP	X29, X30, [SP, #848]!

0x41fa04 ADD	X29, SP, #0

0x41fa08 STP	X19, X20, [SP, #16]

0x41fa0c ORR	X19, XZR, X0

0x41fa10 STP	X23, X24, [SP, #48]

0x41fa14 LDP	W23, W1, [X0, #48]

0x41fa18 LDP	W0, W2, [X0, #40]

0x41fa1c ADD	W3, W1, #4

0x41fa20 SUB	W23, W23, #1

0x41fa24 SUB	W4, W0, #1

0x41fa28 STP	W3, W4, [SP, #136]

0x41fa2c CMP	W23, W3

0x41fa30 B.GE	41fdf4

0x41fa34 STP	X21, X22, [SP, #32]

0x41fa38 ADD	W22, W2, #4

0x41fa3c SUB	W21, W3, W23

0x41fa40 CMP	W4, W22

0x41fa44 B.GE	41fe04

0x41fa48 SUB	W5, W22, W4

0x41fa4c MADD	W24, W21, W5, WZR

0x41fa50 STR	W5, [SP, #144]

0x41fa54 BL	403890

0x41fa58 ORR	W20, WZR, W0

0x41fa5c BL	4038c0

0x41fa60 UDIV	W7, W24, W20

0x41fa64 ORR	W6, WZR, W0

0x41fa68 MSUB	W8, W7, W20, W24

0x41fa6c CMP	W0, W8

0x41fa70 B.CC	41fe18

  (219) 0x41fa74 MADD	W16, W7, W6, W8

  (219) 0x41fa78 ADD	W9, W7, W16

  (219) 0x41fa7c STR	W9, [SP, #148]

  (219) 0x41fa80 CMP	W16, W9

  (219) 0x41fa84 B.CS	41fe04

(220) 0x41fa88 LDP	W10, W11, [SP, #140]

(220) 0x41fa8c STP	X27, X28, [SP, #80]

(220) 0x41fa90 STP	X25, X26, [SP, #64]

(220) 0x41fa94 UDIV	W12, W16, W11

(220) 0x41fa98 LDR	X27, [X19, #32]

(220) 0x41fa9c LDP	X25, X20, [X19]

(220) 0x41faa0 LDP	X26, X24, [X19, #16]

(220) 0x41faa4 MSUB	W13, W12, W11, W16

(220) 0x41faa8 ADD	W14, W12, W23

(220) 0x41faac SBFM	X15, X14, #0, #31

(220) 0x41fab0 ADD	W28, W13, W10

(220) 0x41fab4 SUB	W13, W22, W28

(220) 0x41fab8 CMP	W7, W13

(220) 0x41fabc CSEL	W3, W7, W13, #9

(220) 0x41fac0 ADD	W19, W16, W3

(220) 0x41fac4 CMP	W16, W19

(220) 0x41fac8 B.CS	41fdd0

  (221) 0x41facc LDR	X30, [X27]

  (221) 0x41fad0 ADD	X16, X15, #1

  (221) 0x41fad4 LDR	X17, [X20]

  (221) 0x41fad8 LDR	X18, [X25]

  (221) 0x41fadc MADD	X4, X15, X30, XZR

  (221) 0x41fae0 LDR	X14, [X20, #16]

  (221) 0x41fae4 MADD	X12, X15, X17, X17

  (221) 0x41fae8 LDR	X22, [X24, #16]

  (221) 0x41faec MADD	X11, X15, X18, XZR

  (221) 0x41faf0 LDR	X13, [X25, #16]

  (221) 0x41faf4 SUB	X6, X12, X17

  (221) 0x41faf8 LDR	X21, [X26, #16]

  (221) 0x41fafc LDR	X23, [X27, #16]

  (221) 0x41fb00 STP	X16, X4, [SP, #104]

  (221) 0x41fb04 LDR	X1, [X26]

  (221) 0x41fb08 MADD	X5, X15, X1, XZR

  (221) 0x41fb0c STP	X6, X5, [SP, #120]

  (221) 0x41fb10 LDR	X2, [X24]

  (221) 0x41fb14 MADD	X30, X15, X2, XZR

  (221) 0x41fb18 CMP	W3, #1

  (221) 0x41fb1c B.EQ	41fd3c

  (221) 0x41fb20 SBFM	X1, X28, #0, #31

  (221) 0x41fb24 UBFM	W7, W3, #1, #31

  (221) 0x41fb28 ADD	X8, X11, X1

  (221) 0x41fb2c ADD	X18, X5, X1

  (221) 0x41fb30 ADD	X15, X8, #1

  (221) 0x41fb34 ADD	X5, X12, X1

  (221) 0x41fb38 ADD	X8, X21, X18,LSL #3

  (221) 0x41fb3c UBFM	X10, X7, #60, #59

  (221) 0x41fb40 UBFM	X7, X15, #61, #60

  (221) 0x41fb44 ADD	X2, X13, X15,LSL #3

  (221) 0x41fb48 SUB	X9, X10, #16

  (221) 0x41fb4c ADD	X15, X4, X1

  (221) 0x41fb50 ADD	X4, X14, X5,LSL #3

  (221) 0x41fb54 UBFM	X16, X9, #4, #63

  (221) 0x41fb58 STR	X7, [SP, #152]

  (221) 0x41fb5c SUB	X7, X7, #8

  (221) 0x41fb60 ADD	X17, X16, #1

  (221) 0x41fb64 ADD	X16, X6, X1

  (221) 0x41fb68 ADD	X1, X30, X1

  (221) 0x41fb6c STR	X4, [SP, #96]

  (221) 0x41fb70 ADD	X4, X13, X7

  (221) 0x41fb74 ADD	X6, X14, X16,LSL #3

  (221) 0x41fb78 STR	X7, [SP, #160]

  (221) 0x41fb7c UBFM	X7, X1, #61, #60

  (221) 0x41fb80 ANDS	X9, X17, #4160

  (221) 0x41fb84 ADD	X1, X22, X1,LSL #3

  (221) 0x41fb88 UBFM	X17, X5, #61, #60

  (221) 0x41fb8c MOVZ	X0, #0

  (221) 0x41fb90 ADD	X5, X23, X15,LSL #3

  (221) 0x41fb94 STR	X7, [SP, #168]

  (221) 0x41fb98 UBFM	X18, X18, #61, #60

  (221) 0x41fb9c UBFM	X16, X16, #61, #60

  (221) 0x41fba0 UBFM	X15, X15, #61, #60

  (221) 0x41fba4 B.EQ	41fc64

  (221) 0x41fba8 CMP	X9, #1

  (221) 0x41fbac B.EQ	41fc28

  (221) 0x41fbb0 CMP	X9, #2

  (221) 0x41fbb4 B.EQ	41fbf4

  (221) 0x41fbb8 LDR	Q1, [X21, X18]

  (221) 0x41fbbc MOVZ	X0, #16

  (221) 0x41fbc0 LDR	Q0, [X14, X17]

  (221) 0x41fbc4 LDR	Q29, [X14, X16]

  (221) 0x41fbc8 LDR	X9, [SP, #152]

  (221) 0x41fbcc FADD	V2.2D, V1.2D, V0.2D

  (221) 0x41fbd0 LDR	X18, [SP, #160]

  (221) 0x41fbd4 LDR	X17, [SP, #168]

  (221) 0x41fbd8 FSUB	V3.2D, V2.2D, V29.2D

  (221) 0x41fbdc STR	Q3, [X23, X15]

  (221) 0x41fbe0 LDR	Q31, [X13, X9]

  (221) 0x41fbe4 LDR	Q30, [X13, X18]

  (221) 0x41fbe8 FSUB	V4.2D, V31.2D, V30.2D

  (221) 0x41fbec FADD	V5.2D, V4.2D, V3.2D

  (221) 0x41fbf0 STR	Q5, [X22, X17]

  (221) 0x41fbf4 LDR	X16, [SP, #96]

  (221) 0x41fbf8 LDR	Q6, [X8, X0]

  (221) 0x41fbfc LDR	Q26, [X6, X0]

  (221) 0x41fc00 LDR	Q7, [X16, X0]

  (221) 0x41fc04 FADD	V16.2D, V6.2D, V7.2D

  (221) 0x41fc08 FSUB	V17.2D, V16.2D, V26.2D

  (221) 0x41fc0c STR	Q17, [X5, X0]

  (221) 0x41fc10 LDR	Q28, [X2, X0]

  (221) 0x41fc14 LDR	Q27, [X4, X0]

  (221) 0x41fc18 FSUB	V18.2D, V28.2D, V27.2D

  (221) 0x41fc1c FADD	V19.2D, V18.2D, V17.2D

  (221) 0x41fc20 STR	Q19, [X1, X0]

  (221) 0x41fc24 ADD	X0, X0, #16

  (221) 0x41fc28 LDR	X15, [SP, #96]

  (221) 0x41fc2c LDR	Q20, [X8, X0]

  (221) 0x41fc30 LDR	Q23, [X6, X0]

  (221) 0x41fc34 LDR	Q21, [X15, X0]

  (221) 0x41fc38 FADD	V22.2D, V20.2D, V21.2D

  (221) 0x41fc3c FSUB	V1.2D, V22.2D, V23.2D

  (221) 0x41fc40 STR	Q1, [X5, X0]

  (221) 0x41fc44 LDR	Q25, [X2, X0]

  (221) 0x41fc48 LDR	Q24, [X4, X0]

  (221) 0x41fc4c FSUB	V0.2D, V25.2D, V24.2D

  (221) 0x41fc50 FADD	V29.2D, V0.2D, V1.2D

  (221) 0x41fc54 STR	Q29, [X1, X0]

  (221) 0x41fc58 ADD	X0, X0, #16

  (221) 0x41fc5c CMP	X10, X0

  (221) 0x41fc60 B.EQ	41fd30

  (221) 0x41fc64 LDR	X7, [SP, #96]

    (222) 0x41fc68 ADD	X9, X0, #16

    (222) 0x41fc6c ADD	X17, X0, #32

    (222) 0x41fc70 LDR	Q2, [X8, X0]

    (222) 0x41fc74 ADD	X18, X0, #48

    (222) 0x41fc78 LDR	Q3, [X7, X0]

    (222) 0x41fc7c LDR	Q31, [X6, X0]

    (222) 0x41fc80 FADD	V30.2D, V2.2D, V3.2D

    (222) 0x41fc84 FSUB	V4.2D, V30.2D, V31.2D

    (222) 0x41fc88 STR	Q4, [X5, X0]

    (222) 0x41fc8c LDR	Q5, [X2, X0]

    (222) 0x41fc90 LDR	Q6, [X4, X0]

    (222) 0x41fc94 FSUB	V26.2D, V5.2D, V6.2D

    (222) 0x41fc98 FADD	V7.2D, V26.2D, V4.2D

    (222) 0x41fc9c STR	Q7, [X1, X0]

    (222) 0x41fca0 ADD	X0, X0, #64

    (222) 0x41fca4 LDR	Q16, [X8, X9]

    (222) 0x41fca8 LDR	Q17, [X7, X9]

    (222) 0x41fcac LDR	Q28, [X6, X9]

    (222) 0x41fcb0 FADD	V27.2D, V16.2D, V17.2D

    (222) 0x41fcb4 FSUB	V18.2D, V27.2D, V28.2D

    (222) 0x41fcb8 STR	Q18, [X5, X9]

    (222) 0x41fcbc LDR	Q19, [X2, X9]

    (222) 0x41fcc0 LDR	Q20, [X4, X9]

    (222) 0x41fcc4 FSUB	V23.2D, V19.2D, V20.2D

    (222) 0x41fcc8 FADD	V21.2D, V23.2D, V18.2D

    (222) 0x41fccc STR	Q21, [X1, X9]

    (222) 0x41fcd0 LDR	Q22, [X8, X17]

    (222) 0x41fcd4 LDR	Q1, [X7, X17]

    (222) 0x41fcd8 LDR	Q25, [X6, X17]

    (222) 0x41fcdc FADD	V24.2D, V22.2D, V1.2D

    (222) 0x41fce0 FSUB	V0.2D, V24.2D, V25.2D

    (222) 0x41fce4 STR	Q0, [X5, X17]

    (222) 0x41fce8 LDR	Q29, [X2, X17]

    (222) 0x41fcec LDR	Q2, [X4, X17]

    (222) 0x41fcf0 FSUB	V3.2D, V29.2D, V2.2D

    (222) 0x41fcf4 FADD	V31.2D, V3.2D, V0.2D

    (222) 0x41fcf8 STR	Q31, [X1, X17]

    (222) 0x41fcfc LDR	Q30, [X8, X18]

    (222) 0x41fd00 LDR	Q4, [X7, X18]

    (222) 0x41fd04 LDR	Q5, [X6, X18]

    (222) 0x41fd08 FADD	V6.2D, V30.2D, V4.2D

    (222) 0x41fd0c FSUB	V26.2D, V6.2D, V5.2D

    (222) 0x41fd10 STR	Q26, [X5, X18]

    (222) 0x41fd14 LDR	Q7, [X2, X18]

    (222) 0x41fd18 LDR	Q16, [X4, X18]

    (222) 0x41fd1c FSUB	V17.2D, V7.2D, V16.2D

    (222) 0x41fd20 FADD	V28.2D, V17.2D, V26.2D

    (222) 0x41fd24 STR	Q28, [X1, X18]

    (222) 0x41fd28 CMP	X10, X0

    (222) 0x41fd2c B.NE	41fc68

  (221) 0x41fd30 TBZ	W3, #0, 41fd98

  (221) 0x41fd34 AND	W3, W3, #1951

  (221) 0x41fd38 ADD	W28, W28, W3

  (221) 0x41fd3c LDR	X6, [SP, #128]

  (221) 0x41fd40 SBFM	X10, X28, #0, #31

  (221) 0x41fd44 ADD	W2, W28, #1

  (221) 0x41fd48 ADD	X8, X11, W2,SXTW

  (221) 0x41fd4c ADD	X12, X12, X10

  (221) 0x41fd50 ADD	X11, X11, X10

  (221) 0x41fd54 ADD	X30, X30, X10

  (221) 0x41fd58 LDR	D27, [X14, X12,LSL #3]

  (221) 0x41fd5c ADD	X5, X6, X10

  (221) 0x41fd60 LDR	D18, [X21, X5,LSL #3]

  (221) 0x41fd64 LDR	X21, [SP, #120]

  (221) 0x41fd68 FADD	D19, D27, D18

  (221) 0x41fd6c ADD	X4, X21, X10

  (221) 0x41fd70 LDR	D20, [X14, X4,LSL #3]

  (221) 0x41fd74 LDR	X14, [SP, #112]

  (221) 0x41fd78 FSUB	D23, D19, S20

  (221) 0x41fd7c ADD	X1, X14, X10

  (221) 0x41fd80 STR	D23, [X23, X1,LSL #3]

  (221) 0x41fd84 LDR	D21, [X13, X8,LSL #3]

  (221) 0x41fd88 LDR	D22, [X13, X11,LSL #3]

  (221) 0x41fd8c FSUB	D1, D21, S22

  (221) 0x41fd90 FADD	D25, D1, D23

  (221) 0x41fd94 STR	D25, [X22, X30,LSL #3]

  (221) 0x41fd98 LDR	X15, [SP, #104]

  (221) 0x41fd9c ORR	W16, WZR, W19

  (221) 0x41fda0 LDR	W19, [SP, #136]

  (221) 0x41fda4 CMP	W19, W15

  (221) 0x41fda8 B.LE	41fde8

  (221) 0x41fdac LDR	W22, [SP, #148]

  (221) 0x41fdb0 LDR	W13, [SP, #144]

  (221) 0x41fdb4 LDR	W28, [SP, #140]

  (221) 0x41fdb8 SUB	W7, W22, W16

  (221) 0x41fdbc CMP	W7, W13

  (221) 0x41fdc0 CSEL	W3, W7, W13, #9

  (221) 0x41fdc4 ADD	W19, W16, W3

  (221) 0x41fdc8 CMP	W16, W19

  (221) 0x41fdcc B.CC	41facc

  (223) 0x41fdd0 ADD	X15, X15, #1

  (223) 0x41fdd4 LDR	W19, [SP, #136]

  (223) 0x41fdd8 STR	X15, [SP, #104]

  (223) 0x41fddc LDR	X15, [SP, #104]

  (223) 0x41fde0 CMP	W19, W15

  (223) 0x41fde4 B.GT	41fdac

(220) 0x41fde8 LDP	X21, X22, [SP, #32]

(220) 0x41fdec LDP	X25, X26, [SP, #64]

(220) 0x41fdf0 LDP	X27, X28, [SP, #80]

(220) 0x41fdf4 LDP	X19, X20, [SP, #16]

(220) 0x41fdf8 LDP	X23, X24, [SP, #48]

(220) 0x41fdfc LDP	X29, X30, [SP], #176

(220) 0x41fe00 RET

  (219) 0x41fe04 LDP	X21, X22, [SP, #32]

  (219) 0x41fe08 LDP	X19, X20, [SP, #16]

  (219) 0x41fe0c LDP	X23, X24, [SP, #48]

  (219) 0x41fe10 LDP	X29, X30, [SP], #176

  (219) 0x41fe14 RET

  (219) 0x41fe18 ADD	W7, W7, #1

  (219) 0x41fe1c MOVZ	W8, #0

  (219) 0x41fe20 B	41fa74

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fa00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41fdf4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41fe04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41fe18 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fa00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41fdf4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41fe04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41fe18 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.91	2.21
▼Loop 220 - advec_mom.cpp:44-48 - exec–	0.00	0.01
▼Loop 221 - advec_mom.cpp:46-48 - exec–	0.00	0.01
○Loop 222 - advec_mom.cpp:47-48 - exec	2.91	2.19
○Loop 223 - advec_mom.cpp:46-46 - exec	0.00	0.01
○Loop 219 - advec_mom.cpp:44-46 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code