OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:157-202 [...]	Coverage (incl. loops): 3.66% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 157 - 202

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

[...]

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41f370 STP	X29, X30, [SP, #864]!

0x41f374 ADD	X29, SP, #0

0x41f378 STP	X19, X20, [SP, #16]

0x41f37c ORR	X20, XZR, X0

0x41f380 STP	X21, X22, [SP, #32]

0x41f384 STP	X23, X24, [SP, #48]

0x41f388 STP	X27, X28, [SP, #80]

0x41f38c LDP	W22, W24, [X0, #64]

0x41f390 LDP	W0, W2, [X0, #56]

0x41f394 ADD	W27, W22, #1

0x41f398 ADD	W28, W24, #4

0x41f39c ADD	W1, W0, #1

0x41f3a0 STR	W1, [SP, #136]

0x41f3a4 CMP	W27, W28

0x41f3a8 B.GE	41f6a8

0x41f3ac ADD	W19, W2, #2

0x41f3b0 SUB	W23, W28, W27

0x41f3b4 CMP	W1, W19

0x41f3b8 B.GE	41f6a8

0x41f3bc SUB	W3, W19, W1

0x41f3c0 MADD	W22, W23, W3, WZR

0x41f3c4 STR	W3, [SP, #140]

0x41f3c8 BL	403890

0x41f3cc ORR	W21, WZR, W0

0x41f3d0 BL	4038c0

0x41f3d4 UDIV	W7, W22, W21

0x41f3d8 ORR	W6, WZR, W0

0x41f3dc MSUB	W4, W7, W21, W22

0x41f3e0 CMP	W0, W4

0x41f3e4 B.CC	41f6c0

(214) 0x41f3e8 MADD	W22, W7, W6, W4

(214) 0x41f3ec ADD	W8, W7, W22

(214) 0x41f3f0 CMP	W22, W8

(214) 0x41f3f4 B.CS	41f6a8

(214) 0x41f3f8 LDR	W10, [SP, #140]

(214) 0x41f3fc ORR	X5, XZR, #3840

(214) 0x41f400 FMOV	D25, #1.0000000

(214) 0x41f404 FMOV	D22, #2.0000000

(214) 0x41f408 ADD	W24, W24, #2

(214) 0x41f40c STP	X25, X26, [SP, #64]

(214) 0x41f410 MOVK	X5, #16325

(214) 0x41f414 FMOV	D24, #-1.0000000

(214) 0x41f418 LDR	W15, [SP, #136]

(214) 0x41f41c UDIV	W11, W22, W10

(214) 0x41f420 LDP	X9, X1, [X20]

(214) 0x41f424 FMOV	D23, X5

(214) 0x41f428 STR	X9, [SP, #144]

(214) 0x41f42c LDP	X3, X26, [X20, #16]

(214) 0x41f430 LDP	X25, X5, [X20, #32]

(214) 0x41f434 MSUB	W13, W11, W10, W22

(214) 0x41f438 ADD	W14, W11, W27

(214) 0x41f43c SBFM	X12, X14, #0, #31

(214) 0x41f440 SUB	W16, W14, #2

(214) 0x41f444 SUB	X11, X12, #1

(214) 0x41f448 ADD	W10, W13, W15

(214) 0x41f44c LDR	X15, [X20, #48]

(214) 0x41f450 SUB	W27, W19, W10

(214) 0x41f454 STP	W28, W8, [SP, #152]

(214) 0x41f458 ADD	W28, W12, #1

(214) 0x41f45c CMP	W7, W27

(214) 0x41f460 CSEL	W17, W7, W27, #9

(214) 0x41f464 ADD	W30, W22, W17

(214) 0x41f468 CMP	W22, W30

(214) 0x41f46c B.CS	41f688

  (216) 0x41f470 SBFM	X0, X10, #0, #31

  (216) 0x41f474 SUB	W18, W17, #1

  (216) 0x41f478 LDR	X2, [X25]

  (216) 0x41f47c ADD	X6, X0, #1

  (216) 0x41f480 SBFM	X27, X16, #0, #31

  (216) 0x41f484 STR	W30, [SP, #108]

  (216) 0x41f488 LDR	X21, [X26]

  (216) 0x41f48c ADD	X13, X6, X18

  (216) 0x41f490 STR	X1, [SP, #128]

  (216) 0x41f494 LDR	X18, [SP, #144]

  (216) 0x41f498 MADD	X23, X12, X2, XZR

  (216) 0x41f49c LDR	X20, [X15]

  (216) 0x41f4a0 MADD	X14, X12, X21, XZR

  (216) 0x41f4a4 LDR	X19, [X25, #16]

  (216) 0x41f4a8 LDR	X21, [X18, #8]

  (216) 0x41f4ac MADD	X4, X12, X20, XZR

  (216) 0x41f4b0 LDR	X7, [X26, #16]

  (216) 0x41f4b4 ADD	X20, X19, X23,LSL #3

  (216) 0x41f4b8 LDR	X2, [X15, #16]

  (216) 0x41f4bc ADD	X23, X21, X12,LSL #3

  (216) 0x41f4c0 LDR	X10, [X1]

  (216) 0x41f4c4 ADD	X19, X7, X14,LSL #3

  (216) 0x41f4c8 LDR	X9, [X3]

  (216) 0x41f4cc ADD	X18, X2, X4,LSL #3

  (216) 0x41f4d0 LDR	X22, [X5]

  (216) 0x41f4d4 LDR	X17, [X5, #16]

  (216) 0x41f4d8 LDR	X8, [X3, #16]

  (216) 0x41f4dc LDR	X7, [X1, #16]

  (216) 0x41f4e0 STP	X25, X5, [SP, #112]

  (216) 0x41f4e4 B	41f4ec

    (215) 0x41f4e8 ADD	X6, X6, #1

    (215) 0x41f4ec LDR	D21, [X20, X0,LSL #3]

    (215) 0x41f4f0 ORR	X1, XZR, X11

    (215) 0x41f4f4 ORR	X2, XZR, X27

    (215) 0x41f4f8 ORR	X25, XZR, X12

    (215) 0x41f4fc ORR	X30, XZR, X11

    (215) 0x41f500 FCMPE	D21, #0

    (215) 0x41f504 B.GT	41f520

    (215) 0x41f508 CMP	W24, W28

    (215) 0x41f50c CSEL	W5, W24, W28, #13

    (215) 0x41f510 SBFM	X30, X5, #0, #31

    (215) 0x41f514 ORR	X25, XZR, X11

    (215) 0x41f518 ORR	X1, XZR, X12

    (215) 0x41f51c ORR	X2, XZR, X30

    (215) 0x41f520 MADD	X4, X22, X1, X0

    (215) 0x41f524 FABS	D31, D21

    (215) 0x41f528 LDR	D28, [X21, X30,LSL #3]

    (215) 0x41f52c MADD	X5, X10, X1, X0

    (215) 0x41f530 MADD	X30, X10, X25, X0

    (215) 0x41f534 LDR	D26, [X23]

    (215) 0x41f538 UBFM	X14, X4, #61, #60

    (215) 0x41f53c MADD	X4, X9, X25, X0

    (215) 0x41f540 UBFM	X5, X5, #61, #60

    (215) 0x41f544 MADD	X25, X10, X2, X0

    (215) 0x41f548 LDR	D29, [X17, X14]

    (215) 0x41f54c MADD	X1, X9, X1, X0

    (215) 0x41f550 MADD	X2, X9, X2, X0

    (215) 0x41f554 LDR	D30, [X7, X5]

    (215) 0x41f558 FDIV	D2, D26, D28

    (215) 0x41f55c LDR	D3, [X7, X30,LSL #3]

    (215) 0x41f560 LDR	D27, [X7, X25,LSL #3]

    (215) 0x41f564 FDIV	D0, D31, D29

    (215) 0x41f568 FSUB	D4, D3, S30

    (215) 0x41f56c FSUB	D1, D30, S27

    (215) 0x41f570 FCMPE	D4, #0

    (215) 0x41f574 FABS	D5, D4

    (215) 0x41f578 FMUL	D6, D4, D1

    (215) 0x41f57c FABS	D20, D1

    (215) 0x41f580 FMINNM	D18, D5, D20

    (215) 0x41f584 FCSEL	D7, D24, D25, #9

    (215) 0x41f588 FCMPE	D6, #0

    (215) 0x41f58c FADD	D16, D0, D25

    (215) 0x41f590 FSUB	D19, D25, S0

    (215) 0x41f594 FSUB	D17, D22, S0

    (215) 0x41f598 FMUL	D31, D2, D16

    (215) 0x41f59c B.LS	41f5b8

    (215) 0x41f5a0 FMUL	D28, D5, D17

    (215) 0x41f5a4 FMADD	D29, D20, D31, D28

    (215) 0x41f5a8 FMUL	D27, D29, D23

    (215) 0x41f5ac FMINNM	D0, D27, D18

    (215) 0x41f5b0 FMUL	D1, D0, D19

    (215) 0x41f5b4 FMADD	D30, D1, D7, D30

    (215) 0x41f5b8 FMUL	D26, D30, D21

    (215) 0x41f5bc STR	D26, [X19, X0,LSL #3]

    (215) 0x41f5c0 FABS	D21, D26

    (215) 0x41f5c4 LDR	D27, [X8, X1,LSL #3]

    (215) 0x41f5c8 LDR	D19, [X8, X4,LSL #3]

    (215) 0x41f5cc LDR	D20, [X8, X2,LSL #3]

    (215) 0x41f5d0 FSUB	D2, D19, S27

    (215) 0x41f5d4 FSUB	D3, D27, S20

    (215) 0x41f5d8 FABS	D4, D2

    (215) 0x41f5dc FCMPE	D2, #0

    (215) 0x41f5e0 FMUL	D6, D2, D3

    (215) 0x41f5e4 FABS	D5, D3

    (215) 0x41f5e8 FMINNM	D18, D4, D5

    (215) 0x41f5ec FMUL	D7, D4, D17

    (215) 0x41f5f0 FCSEL	D16, D24, D25, #9

    (215) 0x41f5f4 FCMPE	D6, #0

    (215) 0x41f5f8 FMADD	D17, D5, D31, D7

    (215) 0x41f5fc B.LS	41f624

    (215) 0x41f600 LDR	D31, [X17, X14]

    (215) 0x41f604 FMUL	D29, D17, D23

    (215) 0x41f608 FMINNM	D1, D29, D18

    (215) 0x41f60c LDR	D28, [X7, X5]

    (215) 0x41f610 FMUL	D0, D31, D28

    (215) 0x41f614 FDIV	D30, D21, D0

    (215) 0x41f618 FSUB	D21, D25, S30

    (215) 0x41f61c FMUL	D19, D21, D1

    (215) 0x41f620 FMADD	D27, D16, D19, D27

    (215) 0x41f624 FMUL	D26, D27, D26

    (215) 0x41f628 STR	D26, [X18, X0,LSL #3]

    (215) 0x41f62c ORR	X0, XZR, X6

    (215) 0x41f630 CMP	X6, X13

    (215) 0x41f634 B.NE	41f4e8

  (216) 0x41f638 LDR	W6, [SP, #152]

  (216) 0x41f63c ADD	X12, X12, #1

  (216) 0x41f640 ADD	X11, X11, #1

  (216) 0x41f644 LDP	X25, X5, [SP, #112]

  (216) 0x41f648 ADD	W16, W16, #1

  (216) 0x41f64c LDR	X1, [SP, #128]

  (216) 0x41f650 LDR	W28, [SP, #108]

  (216) 0x41f654 CMP	W6, W12

  (216) 0x41f658 B.LE	41f6a4

  (216) 0x41f65c ORR	W22, WZR, W28

  (216) 0x41f660 LDR	W13, [SP, #156]

  (216) 0x41f664 LDR	W27, [SP, #140]

  (216) 0x41f668 LDR	W10, [SP, #136]

  (216) 0x41f66c SUB	W7, W13, W28

  (216) 0x41f670 ADD	W28, W12, #1

  (216) 0x41f674 CMP	W7, W27

  (216) 0x41f678 CSEL	W17, W7, W27, #9

  (216) 0x41f67c ADD	W30, W22, W17

  (216) 0x41f680 CMP	W22, W30

  (216) 0x41f684 B.CC	41f470

  (217) 0x41f688 LDR	W6, [SP, #152]

  (217) 0x41f68c ADD	X12, X12, #1

  (217) 0x41f690 ORR	W28, WZR, W22

  (217) 0x41f694 ADD	X11, X11, #1

  (217) 0x41f698 ADD	W16, W16, #1

  (217) 0x41f69c CMP	W6, W12

  (217) 0x41f6a0 B.GT	41f65c

(214) 0x41f6a4 LDP	X25, X26, [SP, #64]

(214) 0x41f6a8 LDP	X19, X20, [SP, #16]

(214) 0x41f6ac LDP	X21, X22, [SP, #32]

(214) 0x41f6b0 LDP	X23, X24, [SP, #48]

(214) 0x41f6b4 LDP	X27, X28, [SP, #80]

(214) 0x41f6b8 LDP	X29, X30, [SP], #160

(214) 0x41f6bc RET

(214) 0x41f6c0 ADD	W7, W7, #1

(214) 0x41f6c4 MOVZ	W4, #0

(214) 0x41f6c8 B	41f3e8

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-163,169-202
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 45% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.04 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f370

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W24, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W27, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W28, W24, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR W1, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W27, W28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f6a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W28, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f6a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W3, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W22, W23, W3, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W3, [SP, #140]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W4, W7, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41f6c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-163,169-202
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.04 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f370

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W24, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W27, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W28, W24, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR W1, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W27, W28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f6a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W28, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f6a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W3, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W22, W23, W3, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W3, [SP, #140]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W4, W7, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41f6c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.66	2.78
▼Loop 214 - advec_cell.cpp:157-202 - exec–	0.00	0.00
▼Loop 216 - advec_cell.cpp:159-202 - exec–	0.00	0.01
○Loop 215 - advec_cell.cpp:163-202 - exec	3.66	2.76
○Loop 217 - advec_cell.cpp:159-159 - exec	0.00	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code