OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:65-110 [...]	Coverage (incl. loops): 3.20% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 65 - 110

--------------------------------------------------------------------------------

65: #pragma omp parallel for simd collapse(2)

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41e948 STP	X29, X30, [SP, #672]!

0x41e94c ADD	X29, SP, #0

0x41e950 STP	X21, X22, [SP, #32]

0x41e954 ORR	X21, XZR, X0

0x41e958 STP	X23, X24, [SP, #48]

0x41e95c LDP	W23, W1, [X0, #64]

0x41e960 LDP	W0, W22, [X0, #56]

0x41e964 ADD	W23, W23, #1

0x41e968 ADD	W14, W1, #2

0x41e96c ADD	W2, W0, #1

0x41e970 STR	W2, [SP, #300]

0x41e974 CMP	W23, W14

0x41e978 B.GE	41f2f8

0x41e97c STP	X19, X20, [SP, #16]

0x41e980 ADD	W19, W22, #4

0x41e984 SUB	W24, W14, W23

0x41e988 STR	W14, [SP, #168]

0x41e98c CMP	W2, W19

0x41e990 B.GE	41f2f4

0x41e994 SUB	W3, W19, W2

0x41e998 MADD	W24, W24, W3, WZR

0x41e99c STR	W3, [SP, #304]

0x41e9a0 BL	403890

0x41e9a4 ORR	W20, WZR, W0

0x41e9a8 BL	4038c0

0x41e9ac UDIV	W7, W24, W20

0x41e9b0 LDR	W6, [SP, #168]

0x41e9b4 ORR	W4, WZR, W0

0x41e9b8 MSUB	W5, W7, W20, W24

0x41e9bc CMP	W0, W5

0x41e9c0 B.CC	41f364

0x41e9c4 MADD	W4, W7, W4, W5

0x41e9c8 ADD	W8, W7, W4

0x41e9cc STR	W8, [SP, #308]

0x41e9d0 CMP	W4, W8

0x41e9d4 B.CS	41f2f4

0x41e9d8 LDR	W11, [SP, #304]

0x41e9dc ORR	X9, XZR, #3840

0x41e9e0 ADD	W10, W22, #2

0x41e9e4 FMOV	V29.2D, #1.0000000

0x41e9e8 FMOV	V5.2D, #-1.0000000

0x41e9ec MOVK	X9, #16325

0x41e9f0 STP	X25, X26, [SP, #64]

0x41e9f4 FMOV	S30, W10

0x41e9f8 UDIV	W12, W4, W11

0x41e9fc FMOV	D31, X9

0x41ea00 STP	X27, X28, [SP, #80]

0x41ea04 STP	D8, D9, [SP, #96]

0x41ea08 FMOV	D9, #1.0000000

0x41ea0c FMOV	D8, #-1.0000000

0x41ea10 STP	D10, D11, [SP, #112]

0x41ea14 MOVI	V11.4S, #4

0x41ea18 STP	D12, D13, [SP, #128]

0x41ea1c MVNI	V12.4S, #0

0x41ea20 MVNI	V13.4S, #1

0x41ea24 STP	D14, D15, [SP, #144]

0x41ea28 FMOV	V15.2D, #2.0000000

0x41ea2c MOVI	V14.4S, #1

0x41ea30 STR	X9, [SP, #336]

0x41ea34 DUP	V16.2S, V30.S[0]

0x41ea38 DUP	V10.4S, V30.S[0]

0x41ea3c STR	W10, [SP, #348]

0x41ea40 DUP	V6.2D, V31.D[0]

0x41ea44 LDP	X13, X27, [X21]

0x41ea48 ADD	W15, W12, W23

0x41ea4c MSUB	W16, W12, W11, W4

0x41ea50 SBFM	X25, X15, #0, #31

0x41ea54 LDR	W18, [SP, #300]

0x41ea58 STR	X13, [SP, #312]

0x41ea5c LDR	X28, [X21, #48]

0x41ea60 LDP	X17, X15, [X21, #32]

0x41ea64 ADD	W26, W16, W18

0x41ea68 SUB	W19, W19, W26

0x41ea6c LDP	X13, X14, [X21, #16]

0x41ea70 STR	X17, [SP, #320]

0x41ea74 STR	D16, [SP, #328]

0x41ea78 STR	W6, [SP, #344]

0x41ea7c HINT	#0

      (212) 0x41ea80 CMP	W7, W19

      (212) 0x41ea84 CSEL	W1, W7, W19, #9

      (212) 0x41ea88 ADD	W30, W4, W1

      (212) 0x41ea8c STR	W30, [SP, #196]

      (212) 0x41ea90 CMP	W4, W30

      (212) 0x41ea94 B.CS	41f2d0

    (211) 0x41ea98 LDR	X19, [SP, #320]

    (211) 0x41ea9c SUB	W21, W1, #1

    (211) 0x41eaa0 LDR	X20, [X14]

    (211) 0x41eaa4 LDR	X22, [X27]

    (211) 0x41eaa8 LDR	X10, [X28, #16]

    (211) 0x41eaac MADD	X8, X25, X20, XZR

    (211) 0x41eab0 LDR	X12, [X14, #16]

    (211) 0x41eab4 MADD	X6, X25, X22, XZR

    (211) 0x41eab8 LDR	X4, [SP, #312]

    (211) 0x41eabc STR	X10, [SP, #184]

    (211) 0x41eac0 LDR	X23, [X15]

    (211) 0x41eac4 LDR	X0, [X13]

    (211) 0x41eac8 LDR	X2, [X28]

    (211) 0x41eacc MADD	X30, X25, X23, XZR

    (211) 0x41ead0 LDR	X24, [X19]

    (211) 0x41ead4 MADD	X3, X25, X0, XZR

    (211) 0x41ead8 LDR	X16, [X4, #8]

    (211) 0x41eadc MADD	X23, X25, X2, XZR

    (211) 0x41eae0 LDR	X9, [X15, #16]

    (211) 0x41eae4 MADD	X18, X25, X24, XZR

    (211) 0x41eae8 LDR	X22, [X19, #16]

    (211) 0x41eaec LDR	X5, [X13, #16]

    (211) 0x41eaf0 LDR	X4, [X27, #16]

    (211) 0x41eaf4 STP	X12, X8, [SP, #168]

    (211) 0x41eaf8 CMP	W21, #2

    (211) 0x41eafc B.LS	41f358

    (211) 0x41eb00 SBFM	X17, X26, #0, #31

    (211) 0x41eb04 UBFM	W0, W1, #2, #31

    (211) 0x41eb08 ADD	X7, X9, X30,LSL #3

    (211) 0x41eb0c DUP	V2.4S, W26

    (211) 0x41eb10 ADD	X2, X18, X17

    (211) 0x41eb14 ADD	X19, X8, X17

    (211) 0x41eb18 ADD	X21, X16, X17,LSL #3

    (211) 0x41eb1c ADD	X8, X23, X17

    (211) 0x41eb20 ADRP	X17,

    (211) 0x41eb24 ADD	X20, X22, X2,LSL #3

    (211) 0x41eb28 STR	W26, [SP, #200]

    (211) 0x41eb2c UBFM	X24, X0, #59, #58

    (211) 0x41eb30 ADD	X2, X5, X3,LSL #3

    (211) 0x41eb34 MOVZ	X11, #0

    (211) 0x41eb38 STP	X22, X15, [SP, #208]

    (211) 0x41eb3c ADD	X0, X4, X6,LSL #3

    (211) 0x41eb40 ADD	X19, X12, X19,LSL #3

    (211) 0x41eb44 MOVZ	X12, #16

    (211) 0x41eb48 LDR	Q0, [X17, #1216]

    (211) 0x41eb4c ADD	X17, X10, X8,LSL #3

    (211) 0x41eb50 STP	X27, X14, [SP, #224]

    (211) 0x41eb54 STP	X13, X18, [SP, #240]

    (211) 0x41eb58 ADD	V2.4S, V2.4S, V0.4S

    (211) 0x41eb5c STP	X28, X4, [SP, #256]

    (211) 0x41eb60 STP	X6, X9, [SP, #272]

    (211) 0x41eb64 STR	X3, [SP, #288]

    (211) 0x41eb68 STR	W1, [SP, #296]

      (213) 0x41eb6c LDR	Q3, [X20, X11]

      (213) 0x41eb70 ORR	V1.16B, V2.16B, V2.16B

      (213) 0x41eb74 ADD	V2.4S, V2.4S, V11.4S

      (213) 0x41eb78 LDR	Q4, [X20, X12]

      (213) 0x41eb7c ADD	V24.4S, V1.4S, V12.4S

      (213) 0x41eb80 SSHLL	V28.2D, V1.2S, #32

      (213) 0x41eb84 LDR	Q27, [X21, X11]

      (213) 0x41eb88 ADD	V7.4S, V1.4S, V14.4S

      (213) 0x41eb8c ADD	V26.4S, V1.4S, V13.4S

      (213) 0x41eb90 FCMGT	V25.2D, V3.2D, #0

      (213) 0x41eb94 SSHLL2	V31.2D, V1.4S, #32

      (213) 0x41eb98 FABS	V18.2D, V3.2D

      (213) 0x41eb9c SSHLL	V20.2D, V24.2S, #32

      (213) 0x41eba0 SMIN	V17.4S, V7.4S, V10.4S

      (213) 0x41eba4 SSHLL	V23.2D, V26.2S, #32

      (213) 0x41eba8 FCMGT	V22.2D, V4.2D, #0

      (213) 0x41ebac SSHLL2	V0.2D, V24.4S, #32

      (213) 0x41ebb0 ORR	V19.16B, V25.16B, V25.16B

      (213) 0x41ebb4 SSHLL2	V1.2D, V26.4S, #32

      (213) 0x41ebb8 SSHLL	V21.2D, V17.2S, #32

      (213) 0x41ebbc SSHLL2	V30.2D, V17.4S, #32

      (213) 0x41ebc0 BSL	V19.16B, V20.16B, V28.16B

      (213) 0x41ebc4 BIF	V28.16B, V20.16B, V25.16B

      (213) 0x41ebc8 BIF	V23.16B, V21.16B, V25.16B

      (213) 0x41ebcc ORR	V16.16B, V22.16B, V22.16B

      (213) 0x41ebd0 FMOV	X26, D19

      (213) 0x41ebd4 MOV	D7, V19.D[1]

      (213) 0x41ebd8 FMOV	X27, D28

      (213) 0x41ebdc MOV	D28, V28.D[1]

      (213) 0x41ebe0 FMOV	X3, D23

      (213) 0x41ebe4 BSL	V25.16B, V20.16B, V21.16B

      (213) 0x41ebe8 BSL	V16.16B, V0.16B, V31.16B

      (213) 0x41ebec FMOV	X13, D7

      (213) 0x41ebf0 BIF	V31.16B, V0.16B, V22.16B

      (213) 0x41ebf4 FMOV	X15, D28

      (213) 0x41ebf8 MOV	D17, V23.D[1]

      (213) 0x41ebfc BIF	V1.16B, V30.16B, V22.16B

      (213) 0x41ec00 UBFM	X9, X26, #61, #60

      (213) 0x41ec04 FMOV	X28, D16

      (213) 0x41ec08 MOV	D20, V16.D[1]

      (213) 0x41ec0c MOV	D24, V31.D[1]

      (213) 0x41ec10 UBFM	X26, X27, #61, #60

      (213) 0x41ec14 LDR	D26, [X7, X9]

      (213) 0x41ec18 BIT	V30.16B, V0.16B, V22.16B

      (213) 0x41ec1c FMOV	X1, D31

      (213) 0x41ec20 MOV	D22, V1.D[1]

      (213) 0x41ec24 FABS	V0.2D, V4.2D

      (213) 0x41ec28 LDR	D21, [X9, X0]

      (213) 0x41ec2c UBFM	X14, X13, #61, #60

      (213) 0x41ec30 UBFM	X13, X3, #61, #60

      (213) 0x41ec34 ADD	X3, X7, X14

      (213) 0x41ec38 LDR	D23, [X0, X26]

      (213) 0x41ec3c UBFM	X4, X15, #61, #60

      (213) 0x41ec40 FMOV	X6, D20

      (213) 0x41ec44 UBFM	X8, X28, #61, #60

      (213) 0x41ec48 FMOV	D31, D26

      (213) 0x41ec4c MOV	X28, V25.D[1]

      (213) 0x41ec50 FMOV	X15, D1

      (213) 0x41ec54 LDR	D19, [X7, X8]

      (213) 0x41ec58 UBFM	X1, X1, #61, #60

      (213) 0x41ec5c FMOV	X22, D24

      (213) 0x41ec60 LD1	{V31.D[1]}, [X3]

      (213) 0x41ec64 ADD	X3, X14, X0

      (213) 0x41ec68 FMOV	X18, D17

      (213) 0x41ec6c LD1	{V21.D[1]}, [X3]

      (213) 0x41ec70 ADD	X3, X0, X4

      (213) 0x41ec74 UBFM	X10, X6, #61, #60

      (213) 0x41ec78 MOV	X27, V30.D[1]

      (213) 0x41ec7c LD1	{V23.D[1]}, [X3]

      (213) 0x41ec80 UBFM	X6, X15, #61, #60

      (213) 0x41ec84 FMOV	X3, D25

      (213) 0x41ec88 LDR	D16, [X16, X28,LSL #3]

      (213) 0x41ec8c UBFM	X22, X22, #61, #60

      (213) 0x41ec90 FMOV	X28, D30

      (213) 0x41ec94 FMOV	X15, D22

      (213) 0x41ec98 LDR	D22, [X8, X0]

      (213) 0x41ec9c FDIV	V18.2D, V18.2D, V31.2D

      (213) 0x41eca0 UBFM	X18, X18, #61, #60

      (213) 0x41eca4 LDR	D25, [X0, X1]

      (213) 0x41eca8 LDR	D7, [X16, X3,LSL #3]

      (213) 0x41ecac ADD	X3, X7, X10

      (213) 0x41ecb0 FSUB	V28.2D, V23.2D, V21.2D

      (213) 0x41ecb4 FADD	V1.2D, V18.2D, V29.2D

      (213) 0x41ecb8 LD1	{V19.D[1]}, [X3]

      (213) 0x41ecbc ADD	X3, X10, X0

      (213) 0x41ecc0 UBFM	X15, X15, #61, #60

      (213) 0x41ecc4 FSUB	V26.2D, V15.2D, V18.2D

      (213) 0x41ecc8 LDR	D30, [X0, X13]

      (213) 0x41eccc FSUB	V18.2D, V29.2D, V18.2D

      (213) 0x41ecd0 LD1	{V22.D[1]}, [X3]

      (213) 0x41ecd4 ADD	X3, X0, X22

      (213) 0x41ecd8 MOV	V7.D[1], V16.D[0]

      (213) 0x41ecdc LDR	D20, [X16, X28,LSL #3]

      (213) 0x41ece0 ADD	X28, X0, X15

      (213) 0x41ece4 LDR	D31, [X0, X6]

      (213) 0x41ece8 FDIV	V23.2D, V27.2D, V7.2D

      (213) 0x41ecec FDIV	V24.2D, V0.2D, V19.2D

      (213) 0x41ecf0 FABS	V0.2D, V28.2D

      (213) 0x41ecf4 LD1	{V25.D[1]}, [X3]

      (213) 0x41ecf8 ADD	X3, X14, X0

      (213) 0x41ecfc LDR	D19, [X16, X27,LSL #3]

      (213) 0x41ed00 ADD	X27, X0, X18

      (213) 0x41ed04 FMOV	D27, D20

      (213) 0x41ed08 FMUL	V23.2D, V23.2D, V1.2D

      (213) 0x41ed0c LD1	{V30.D[1]}, [X27]

      (213) 0x41ed10 ADD	X27, X10, X0

      (213) 0x41ed14 FADD	V20.2D, V24.2D, V29.2D

      (213) 0x41ed18 LD1	{V31.D[1]}, [X28]

      (213) 0x41ed1c LDR	Q17, [X21, X12]

      (213) 0x41ed20 MOV	V27.D[1], V19.D[0]

      (213) 0x41ed24 FSUB	V25.2D, V25.2D, V22.2D

      (213) 0x41ed28 FMUL	V19.2D, V26.2D, V0.2D

      (213) 0x41ed2c FSUB	V30.2D, V21.2D, V30.2D

      (213) 0x41ed30 FDIV	V1.2D, V17.2D, V27.2D

      (213) 0x41ed34 FSUB	V27.2D, V15.2D, V24.2D

      (213) 0x41ed38 FSUB	V31.2D, V22.2D, V31.2D

      (213) 0x41ed3c FABS	V16.2D, V25.2D

      (213) 0x41ed40 FMUL	V17.2D, V1.2D, V20.2D

      (213) 0x41ed44 FABS	V7.2D, V30.2D

      (213) 0x41ed48 FMUL	V30.2D, V30.2D, V28.2D

      (213) 0x41ed4c FMUL	V20.2D, V27.2D, V16.2D

      (213) 0x41ed50 FABS	V1.2D, V31.2D

      (213) 0x41ed54 FMLA	V19.2D, V23.2D, V7.2D

      (213) 0x41ed58 FMLA	V20.2D, V17.2D, V1.2D

      (213) 0x41ed5c FCMLE	V28.2D, V28.2D, #0

      (213) 0x41ed60 FMUL	V31.2D, V31.2D, V25.2D

      (213) 0x41ed64 FCMLE	V25.2D, V25.2D, #0

      (213) 0x41ed68 FMINNM	V0.2D, V7.2D, V0.2D

      (213) 0x41ed6c FMINNM	V16.2D, V1.2D, V16.2D

      (213) 0x41ed70 FMUL	V19.2D, V19.2D, V6.2D

      (213) 0x41ed74 FCMGT	V7.2D, V30.2D, #0

      (213) 0x41ed78 BSL	V28.16B, V5.16B, V29.16B

      (213) 0x41ed7c FMUL	V30.2D, V20.2D, V6.2D

      (213) 0x41ed80 FSUB	V24.2D, V29.2D, V24.2D

      (213) 0x41ed84 BSL	V25.16B, V5.16B, V29.16B

      (213) 0x41ed88 FMUL	V18.2D, V18.2D, V28.2D

      (213) 0x41ed8c FMINNM	V28.2D, V19.2D, V0.2D

      (213) 0x41ed90 FMINNM	V20.2D, V30.2D, V16.2D

      (213) 0x41ed94 ORR	V0.16B, V21.16B, V21.16B

      (213) 0x41ed98 ORR	V16.16B, V22.16B, V22.16B

      (213) 0x41ed9c FMUL	V24.2D, V24.2D, V25.2D

      (213) 0x41eda0 FCMGT	V1.2D, V31.2D, #0

      (213) 0x41eda4 FMLA	V0.2D, V18.2D, V28.2D

      (213) 0x41eda8 FMLA	V16.2D, V24.2D, V20.2D

      (213) 0x41edac BSL	V7.16B, V0.16B, V21.16B

      (213) 0x41edb0 BSL	V1.16B, V16.16B, V22.16B

      (213) 0x41edb4 FMUL	V30.2D, V3.2D, V7.2D

      (213) 0x41edb8 FMUL	V31.2D, V4.2D, V1.2D

      (213) 0x41edbc STR	Q30, [X19, X11]

      (213) 0x41edc0 FABS	V3.2D, V30.2D

      (213) 0x41edc4 STR	Q31, [X19, X12]

      (213) 0x41edc8 LDR	D4, [X9, X0]

      (213) 0x41edcc LDR	D7, [X8, X0]

      (213) 0x41edd0 LDR	D25, [X7, X9]

      (213) 0x41edd4 LDR	D22, [X7, X14]

      (213) 0x41edd8 LD1	{V4.D[1]}, [X3]

      (213) 0x41eddc LDR	D18, [X7, X8]

      (213) 0x41ede0 LD1	{V7.D[1]}, [X27]

      (213) 0x41ede4 MOV	V25.D[1], V22.D[0]

      (213) 0x41ede8 LDR	D21, [X14, X2]

      (213) 0x41edec LDR	D20, [X9, X2]

      (213) 0x41edf0 ADD	X9, X10, X2

      (213) 0x41edf4 FMUL	V19.2D, V4.2D, V25.2D

      (213) 0x41edf8 LDR	D1, [X4, X2]

      (213) 0x41edfc LDR	D0, [X26, X2]

      (213) 0x41ee00 MOV	V20.D[1], V21.D[0]

      (213) 0x41ee04 LDR	D21, [X8, X2]

      (213) 0x41ee08 FDIV	V16.2D, V3.2D, V19.2D

      (213) 0x41ee0c LDR	D28, [X22, X2]

      (213) 0x41ee10 LDR	D24, [X1, X2]

      (213) 0x41ee14 MOV	V0.D[1], V1.D[0]

      (213) 0x41ee18 FSUB	V19.2D, V29.2D, V16.2D

      (213) 0x41ee1c LDR	D3, [X18, X2]

      (213) 0x41ee20 LDR	D25, [X13, X2]

      (213) 0x41ee24 FSUB	V22.2D, V0.2D, V20.2D

      (213) 0x41ee28 LD1	{V21.D[1]}, [X9]

      (213) 0x41ee2c MOV	V24.D[1], V28.D[0]

      (213) 0x41ee30 LDR	D1, [X15, X2]

      (213) 0x41ee34 LDR	D0, [X6, X2]

      (213) 0x41ee38 MOV	V25.D[1], V3.D[0]

      (213) 0x41ee3c FABS	V4.2D, V22.2D

      (213) 0x41ee40 FSUB	V25.2D, V20.2D, V25.2D

      (213) 0x41ee44 FSUB	V24.2D, V24.2D, V21.2D

      (213) 0x41ee48 MOV	V0.D[1], V1.D[0]

      (213) 0x41ee4c LDR	D1, [X7, X10]

      (213) 0x41ee50 FMUL	V26.2D, V26.2D, V4.2D

      (213) 0x41ee54 FSUB	V28.2D, V21.2D, V0.2D

      (213) 0x41ee58 FABS	V3.2D, V24.2D

      (213) 0x41ee5c FABS	V16.2D, V25.2D

      (213) 0x41ee60 MOV	V18.D[1], V1.D[0]

      (213) 0x41ee64 FMUL	V0.2D, V25.2D, V22.2D

      (213) 0x41ee68 FCMLE	V22.2D, V22.2D, #0

      (213) 0x41ee6c FMUL	V27.2D, V27.2D, V3.2D

      (213) 0x41ee70 FMLA	V26.2D, V23.2D, V16.2D

      (213) 0x41ee74 FABS	V23.2D, V28.2D

      (213) 0x41ee78 FMINNM	V4.2D, V16.2D, V4.2D

      (213) 0x41ee7c FMUL	V28.2D, V28.2D, V24.2D

      (213) 0x41ee80 FMLA	V27.2D, V17.2D, V23.2D

      (213) 0x41ee84 FMINNM	V17.2D, V23.2D, V3.2D

      (213) 0x41ee88 FMUL	V26.2D, V26.2D, V6.2D

      (213) 0x41ee8c FMUL	V7.2D, V7.2D, V18.2D

      (213) 0x41ee90 FCMLE	V18.2D, V24.2D, #0

      (213) 0x41ee94 FABS	V3.2D, V31.2D

      (213) 0x41ee98 BSL	V22.16B, V5.16B, V29.16B

      (213) 0x41ee9c FMUL	V24.2D, V27.2D, V6.2D

      (213) 0x41eea0 FMINNM	V16.2D, V26.2D, V4.2D

      (213) 0x41eea4 FDIV	V1.2D, V3.2D, V7.2D

      (213) 0x41eea8 BSL	V18.16B, V5.16B, V29.16B

      (213) 0x41eeac FCMGT	V25.2D, V0.2D, #0

      (213) 0x41eeb0 FMINNM	V27.2D, V24.2D, V17.2D

      (213) 0x41eeb4 FSUB	V23.2D, V29.2D, V1.2D

      (213) 0x41eeb8 FMUL	V4.2D, V16.2D, V22.2D

      (213) 0x41eebc ORR	V22.16B, V20.16B, V20.16B

      (213) 0x41eec0 FCMGT	V0.2D, V28.2D, #0

      (213) 0x41eec4 FMUL	V28.2D, V27.2D, V18.2D

      (213) 0x41eec8 FMLA	V22.2D, V4.2D, V19.2D

      (213) 0x41eecc ORR	V19.16B, V21.16B, V21.16B

      (213) 0x41eed0 FMLA	V19.2D, V23.2D, V28.2D

      (213) 0x41eed4 BSL	V25.16B, V22.16B, V20.16B

      (213) 0x41eed8 FMUL	V30.2D, V30.2D, V25.2D

      (213) 0x41eedc BSL	V0.16B, V19.16B, V21.16B

      (213) 0x41eee0 FMUL	V31.2D, V31.2D, V0.2D

      (213) 0x41eee4 STR	Q30, [X17, X11]

      (213) 0x41eee8 ADD	X11, X11, #32

      (213) 0x41eeec STR	Q31, [X17, X12]

      (213) 0x41eef0 ADD	X12, X12, #32

      (213) 0x41eef4 CMP	X24, X11

      (213) 0x41eef8 B.NE	41eb6c

    (211) 0x41eefc LDR	W1, [SP, #296]

    (211) 0x41ef00 LDP	X22, X15, [SP, #208]

    (211) 0x41ef04 LDP	X27, X14, [SP, #224]

    (211) 0x41ef08 AND	W8, W1, #1886

    (211) 0x41ef0c LDP	X13, X18, [SP, #240]

    (211) 0x41ef10 LDP	X28, X4, [SP, #256]

    (211) 0x41ef14 LDP	X6, X9, [SP, #272]

    (211) 0x41ef18 LDR	W26, [SP, #200]

    (211) 0x41ef1c LDR	X3, [SP, #288]

    (211) 0x41ef20 ADD	W7, W8, W26

    (211) 0x41ef24 ANDS	XZR, X1, #4160

    (211) 0x41ef28 B.EQ	41f2cc

    (211) 0x41ef2c SUB	W1, W1, W8

    (211) 0x41ef30 CMP	W1, #1

    (211) 0x41ef34 B.EQ	41f178

    (211) 0x41ef38 FMOV	S2, W7

    (211) 0x41ef3c SBFM	X2, X26, #0, #31

    (211) 0x41ef40 ADD	W24, W7, #1

    (211) 0x41ef44 MVNI	V20.2S, #0

    (211) 0x41ef48 ADD	X21, X9, X30,LSL #3

    (211) 0x41ef4c ADD	X20, X18, X2

    (211) 0x41ef50 MOVI	V26.2S, #1

    (211) 0x41ef54 LDR	D23, [SP, #328]

    (211) 0x41ef58 ADD	X17, X2, X8

    (211) 0x41ef5c ADD	X12, X4, X6,LSL #3

    (211) 0x41ef60 ADD	X0, X20, X8

    (211) 0x41ef64 MVNI	V24.2S, #1

    (211) 0x41ef68 UBFM	X10, X17, #61, #60

    (211) 0x41ef6c ADD	X19, X5, X3,LSL #3

    (211) 0x41ef70 UBFM	X26, X0, #61, #60

    (211) 0x41ef74 LDR	X17, [SP, #176]

    (211) 0x41ef78 LDR	Q17, [X22, X26]

    (211) 0x41ef7c LDR	Q18, [X16, X10]

    (211) 0x41ef80 ADD	X10, X17, X2

    (211) 0x41ef84 ADD	X2, X23, X2

    (211) 0x41ef88 MOV	V2.S[1], W24

    (211) 0x41ef8c ADD	X24, SP, #200

    (211) 0x41ef90 FCMGT	V16.2D, V17.2D, #0

    (211) 0x41ef94 FABS	V19.2D, V17.2D

    (211) 0x41ef98 ORR	V1.16B, V16.16B, V16.16B

    (211) 0x41ef9c ADD	V21.2S, V2.2S, V20.2S

    (211) 0x41efa0 SSHLL	V25.2D, V2.2S, #32

    (211) 0x41efa4 ADD	V7.2S, V2.2S, V26.2S

    (211) 0x41efa8 ADD	V3.2S, V2.2S, V24.2S

    (211) 0x41efac SSHLL	V0.2D, V21.2S, #32

    (211) 0x41efb0 SMIN	V22.2S, V7.2S, V23.2S

    (211) 0x41efb4 SSHLL	V27.2D, V3.2S, #32

    (211) 0x41efb8 BSL	V1.16B, V0.16B, V25.16B

    (211) 0x41efbc BIF	V25.16B, V0.16B, V16.16B

    (211) 0x41efc0 SSHLL	V30.2D, V22.2S, #32

    (211) 0x41efc4 FMOV	X11, D1

    (211) 0x41efc8 MOV	D4, V1.D[1]

    (211) 0x41efcc MOV	D28, V25.D[1]

    (211) 0x41efd0 FMOV	X0, D25

    (211) 0x41efd4 BIF	V27.16B, V30.16B, V16.16B

    (211) 0x41efd8 BSL	V16.16B, V0.16B, V30.16B

    (211) 0x41efdc FMOV	X17, D4

    (211) 0x41efe0 FMOV	X20, D28

    (211) 0x41efe4 MOV	D20, V27.D[1]

    (211) 0x41efe8 UBFM	X11, X11, #61, #60

    (211) 0x41efec ST1	{V16.D[1]}, [X24]

    (211) 0x41eff0 LDR	D31, [X21, X11]

    (211) 0x41eff4 UBFM	X17, X17, #61, #60

    (211) 0x41eff8 FMOV	X24, D20

    (211) 0x41effc UBFM	X26, X20, #61, #60

    (211) 0x41f000 LDR	D2, [X11, X12]

    (211) 0x41f004 ADD	X20, X10, X8

    (211) 0x41f008 ADD	X10, X21, X17

    (211) 0x41f00c ADD	X8, X2, X8

    (211) 0x41f010 UBFM	X20, X20, #61, #60

    (211) 0x41f014 UBFM	X2, X8, #61, #60

    (211) 0x41f018 UBFM	X8, X0, #61, #60

    (211) 0x41f01c LD1	{V31.D[1]}, [X10]

    (211) 0x41f020 FMOV	X10, D16

    (211) 0x41f024 FMOV	X0, D27

    (211) 0x41f028 LDR	D21, [X12, X8]

    (211) 0x41f02c UBFM	X24, X24, #61, #60

    (211) 0x41f030 LDR	D7, [X16, X10,LSL #3]

    (211) 0x41f034 ADD	X10, X17, X12

    (211) 0x41f038 UBFM	X0, X0, #61, #60

    (211) 0x41f03c FDIV	V25.2D, V19.2D, V31.2D

    (211) 0x41f040 LD1	{V2.D[1]}, [X10]

    (211) 0x41f044 ADD	X10, X12, X26

    (211) 0x41f048 LD1	{V21.D[1]}, [X10]

    (211) 0x41f04c FADD	V16.2D, V25.2D, V29.2D

    (211) 0x41f050 LDR	X10, [SP, #200]

    (211) 0x41f054 FSUB	V0.2D, V15.2D, V25.2D

    (211) 0x41f058 FSUB	V27.2D, V29.2D, V25.2D

    (211) 0x41f05c LDR	D26, [X12, X0]

    (211) 0x41f060 LDR	D24, [X16, X10,LSL #3]

    (211) 0x41f064 ADD	X10, X12, X24

    (211) 0x41f068 FSUB	V3.2D, V21.2D, V2.2D

    (211) 0x41f06c LD1	{V26.D[1]}, [X10]

    (211) 0x41f070 LDR	X10, [SP, #168]

    (211) 0x41f074 MOV	V7.D[1], V24.D[0]

    (211) 0x41f078 FABS	V1.2D, V3.2D

    (211) 0x41f07c FCMLE	V4.2D, V3.2D, #0

    (211) 0x41f080 FDIV	V18.2D, V18.2D, V7.2D

    (211) 0x41f084 FSUB	V28.2D, V2.2D, V26.2D

    (211) 0x41f088 FMUL	V23.2D, V0.2D, V1.2D

    (211) 0x41f08c FMUL	V7.2D, V18.2D, V16.2D

    (211) 0x41f090 ORR	V30.16B, V4.16B, V4.16B

    (211) 0x41f094 FABS	V22.2D, V28.2D

    (211) 0x41f098 BSL	V30.16B, V5.16B, V29.16B

    (211) 0x41f09c FMUL	V19.2D, V28.2D, V3.2D

    (211) 0x41f0a0 ORR	V3.16B, V2.16B, V2.16B

    (211) 0x41f0a4 FMLA	V23.2D, V7.2D, V22.2D

    (211) 0x41f0a8 FMINNM	V20.2D, V22.2D, V1.2D

    (211) 0x41f0ac FMUL	V21.2D, V27.2D, V30.2D

    (211) 0x41f0b0 FCMGT	V26.2D, V19.2D, #0

    (211) 0x41f0b4 FMUL	V31.2D, V23.2D, V6.2D

    (211) 0x41f0b8 FMINNM	V25.2D, V31.2D, V20.2D

    (211) 0x41f0bc FMLA	V3.2D, V21.2D, V25.2D

    (211) 0x41f0c0 BSL	V26.16B, V3.16B, V2.16B

    (211) 0x41f0c4 FMUL	V17.2D, V17.2D, V26.2D

    (211) 0x41f0c8 STR	Q17, [X10, X20]

    (211) 0x41f0cc FABS	V2.2D, V17.2D

    (211) 0x41f0d0 LDR	D16, [X11, X19]

    (211) 0x41f0d4 LDR	D1, [X26, X19]

    (211) 0x41f0d8 ADD	X26, X17, X19

    (211) 0x41f0dc LDR	D23, [X8, X19]

    (211) 0x41f0e0 LD1	{V16.D[1]}, [X26]

    (211) 0x41f0e4 LDR	D24, [X24, X19]

    (211) 0x41f0e8 LDR	D4, [X0, X19]

    (211) 0x41f0ec MOV	V23.D[1], V1.D[0]

    (211) 0x41f0f0 LDR	D28, [X17, X12]

    (211) 0x41f0f4 LDR	D20, [X21, X11]

    (211) 0x41f0f8 FSUB	V18.2D, V23.2D, V16.2D

    (211) 0x41f0fc MOV	V4.D[1], V24.D[0]

    (211) 0x41f100 LDR	D22, [X21, X17]

    (211) 0x41f104 LDR	D27, [X11, X12]

    (211) 0x41f108 FSUB	V30.2D, V16.2D, V4.2D

    (211) 0x41f10c LDR	X21, [SP, #184]

    (211) 0x41f110 FABS	V19.2D, V18.2D

    (211) 0x41f114 MOV	V20.D[1], V22.D[0]

    (211) 0x41f118 FCMLE	V21.2D, V18.2D, #0

    (211) 0x41f11c MOV	V27.D[1], V28.D[0]

    (211) 0x41f120 ORR	V28.16B, V16.16B, V16.16B

    (211) 0x41f124 FMUL	V0.2D, V0.2D, V19.2D

    (211) 0x41f128 FABS	V31.2D, V30.2D

    (211) 0x41f12c FMUL	V3.2D, V30.2D, V18.2D

    (211) 0x41f130 FMUL	V26.2D, V27.2D, V20.2D

    (211) 0x41f134 ORR	V25.16B, V21.16B, V21.16B

    (211) 0x41f138 FMLA	V0.2D, V7.2D, V31.2D

    (211) 0x41f13c FDIV	V7.2D, V2.2D, V26.2D

    (211) 0x41f140 FMINNM	V2.2D, V31.2D, V19.2D

    (211) 0x41f144 BSL	V25.16B, V5.16B, V29.16B

    (211) 0x41f148 FCMGT	V1.2D, V3.2D, #0

    (211) 0x41f14c FSUB	V4.2D, V29.2D, V7.2D

    (211) 0x41f150 FMUL	V24.2D, V0.2D, V6.2D

    (211) 0x41f154 FMINNM	V23.2D, V24.2D, V2.2D

    (211) 0x41f158 FMUL	V27.2D, V23.2D, V25.2D

    (211) 0x41f15c FMLA	V28.2D, V27.2D, V4.2D

    (211) 0x41f160 BSL	V1.16B, V28.16B, V16.16B

    (211) 0x41f164 FMUL	V17.2D, V17.2D, V1.2D

    (211) 0x41f168 STR	Q17, [X21, X2]

    (211) 0x41f16c TBZ	W1, #0, 41f2cc

  (210) 0x41f170 AND	W1, W1, #1951

  (210) 0x41f174 ADD	W7, W7, W1

  (210) 0x41f178 SBFM	X19, X7, #0, #31

  (210) 0x41f17c SUB	W12, W7, #1

  (210) 0x41f180 ADD	X18, X18, X19

  (210) 0x41f184 LDR	D16, [X22, X18,LSL #3]

  (210) 0x41f188 FCMPE	D16, #0

  (210) 0x41f18c B.LS	41f308

  (210) 0x41f190 SBFM	X2, X12, #0, #31

  (210) 0x41f194 SUB	W24, W7, #2

  (210) 0x41f198 SBFM	X17, X24, #0, #31

  (210) 0x41f19c ORR	X0, XZR, X2

  (210) 0x41f1a0 ORR	X20, XZR, X19

  (210) 0x41f1a4 ADD	X30, X30, X2

  (210) 0x41f1a8 FABS	D18, D16

  (210) 0x41f1ac ADD	X10, X6, X2

  (210) 0x41f1b0 LDR	D20, [X16, X0,LSL #3]

  (210) 0x41f1b4 FMOV	D4, #2.0000000

  (210) 0x41f1b8 UBFM	X26, X30, #61, #60

  (210) 0x41f1bc UBFM	X21, X10, #61, #60

  (210) 0x41f1c0 LDR	D22, [X16, X19,LSL #3]

  (210) 0x41f1c4 ADD	X16, X6, X20

  (210) 0x41f1c8 ADD	X6, X6, X17

  (210) 0x41f1cc LDR	D30, [X9, X26]

  (210) 0x41f1d0 LDR	D19, [X4, X21]

  (210) 0x41f1d4 LDR	D21, [X4, X16,LSL #3]

  (210) 0x41f1d8 FDIV	D0, D22, D20

  (210) 0x41f1dc LDR	D26, [X4, X6,LSL #3]

  (210) 0x41f1e0 FDIV	D3, D18, D30

  (210) 0x41f1e4 FSUB	D31, D21, S19

  (210) 0x41f1e8 FSUB	D7, D19, S26

  (210) 0x41f1ec FCMPE	D31, #0

  (210) 0x41f1f0 FMUL	D2, D7, D31

  (210) 0x41f1f4 FCSEL	D25, D8, D9, #9

  (210) 0x41f1f8 FCMPE	D2, #0

  (210) 0x41f1fc FADD	D1, D3, D9

  (210) 0x41f200 FSUB	D28, D4, S3

  (210) 0x41f204 FMUL	D17, D0, D1

  (210) 0x41f208 B.LS	41f238

  (210) 0x41f20c FABS	D24, D31

  (210) 0x41f210 FABS	D27, D7

  (210) 0x41f214 LDR	D30, [SP, #336]

  (210) 0x41f218 FMINNM	D23, D27, D24

  (210) 0x41f21c FSUB	D18, D9, S3

  (210) 0x41f220 FMUL	D20, D24, D28

  (210) 0x41f224 FMADD	D22, D27, D17, D20

  (210) 0x41f228 FMUL	D21, D22, D30

  (210) 0x41f22c FMINNM	D0, D21, D23

  (210) 0x41f230 FMUL	D26, D0, D18

  (210) 0x41f234 FMADD	D19, D25, D26, D19

  (210) 0x41f238 ADD	X1, X3, X2

  (210) 0x41f23c ADD	X12, X3, X20

  (210) 0x41f240 FMUL	D16, D16, D19

  (210) 0x41f244 ADD	X7, X3, X17

  (210) 0x41f248 LDP	X3, X18, [SP, #168]

  (210) 0x41f24c ADD	X22, X18, X19

  (210) 0x41f250 STR	D16, [X3, X22,LSL #3]

  (210) 0x41f254 LDR	D19, [X5, X1,LSL #3]

  (210) 0x41f258 LDR	D3, [X5, X12,LSL #3]

  (210) 0x41f25c LDR	D7, [X5, X7,LSL #3]

  (210) 0x41f260 FSUB	D31, D3, S19

  (210) 0x41f264 FSUB	D2, D19, S7

  (210) 0x41f268 FCMPE	D31, #0

  (210) 0x41f26c FMUL	D25, D2, D31

  (210) 0x41f270 FCSEL	D1, D8, D9, #9

  (210) 0x41f274 FCMPE	D25, #0

  (210) 0x41f278 B.LS	41f2bc

  (210) 0x41f27c LDR	D4, [X4, X21]

  (210) 0x41f280 FABS	D24, D16

  (210) 0x41f284 FABS	D23, D31

  (210) 0x41f288 FABS	D27, D2

  (210) 0x41f28c FMINNM	D20, D27, D23

  (210) 0x41f290 LDR	D18, [X9, X26]

  (210) 0x41f294 FMUL	D28, D23, D28

  (210) 0x41f298 LDR	D0, [SP, #336]

  (210) 0x41f29c FMUL	D22, D4, D18

  (210) 0x41f2a0 FMADD	D17, D27, D17, D28

  (210) 0x41f2a4 FDIV	D21, D24, D22

  (210) 0x41f2a8 FMUL	D26, D17, D0

  (210) 0x41f2ac FMINNM	D3, D26, D20

  (210) 0x41f2b0 FSUB	D7, D9, S21

  (210) 0x41f2b4 FMUL	D31, D7, D3

  (210) 0x41f2b8 FMADD	D19, D1, D31, D19

  (210) 0x41f2bc FMUL	D16, D19, D16

  (210) 0x41f2c0 LDR	X5, [SP, #184]

  (210) 0x41f2c4 ADD	X23, X23, X19

  (210) 0x41f2c8 STR	D16, [X5, X23,LSL #3]

    (211) 0x41f2cc LDR	W4, [SP, #196]

      (212) 0x41f2d0 ADD	X25, X25, #1

      (212) 0x41f2d4 LDR	W9, [SP, #344]

      (212) 0x41f2d8 CMP	W9, W25

      (212) 0x41f2dc B.LE	41f32c

      (212) 0x41f2e0 LDR	W20, [SP, #308]

      (212) 0x41f2e4 LDR	W26, [SP, #300]

      (212) 0x41f2e8 LDR	W19, [SP, #304]

      (212) 0x41f2ec SUB	W7, W20, W4

      (212) 0x41f2f0 B	41ea80

0x41f2f4 LDP	X19, X20, [SP, #16]

0x41f2f8 LDP	X21, X22, [SP, #32]

0x41f2fc LDP	X23, X24, [SP, #48]

0x41f300 LDP	X29, X30, [SP], #352

0x41f304 RET

(209) 0x41f308 LDR	W11, [SP, #348]

(209) 0x41f30c ADD	W22, W7, #1

(209) 0x41f310 SBFM	X20, X12, #0, #31

(209) 0x41f314 ORR	X2, XZR, X19

(209) 0x41f318 CMP	W22, W11

(209) 0x41f31c CSEL	W8, W22, W11, #13

(209) 0x41f320 SBFM	X0, X8, #0, #31

(209) 0x41f324 ORR	X17, XZR, X0

(209) 0x41f328 B	41f1a4

    (211) 0x41f32c LDP	D8, D9, [SP, #96]

    (211) 0x41f330 LDP	X19, X20, [SP, #16]

    (211) 0x41f334 LDP	X25, X26, [SP, #64]

    (211) 0x41f338 LDP	X27, X28, [SP, #80]

    (211) 0x41f33c LDP	X21, X22, [SP, #32]

    (211) 0x41f340 LDP	X23, X24, [SP, #48]

    (211) 0x41f344 LDP	D10, D11, [SP, #112]

    (211) 0x41f348 LDP	D12, D13, [SP, #128]

    (211) 0x41f34c LDP	D14, D15, [SP, #144]

    (211) 0x41f350 LDP	X29, X30, [SP], #352

    (211) 0x41f354 RET

    (211) 0x41f358 MOVZ	X8, #0

    (211) 0x41f35c ORR	W7, WZR, W26

    (211) 0x41f360 B	41ef2c

0x41f364 ADD	W7, W7, #1

0x41f368 MOVZ	W5, #0

0x41f36c B	41e9c4

Coverage (%)	Name	Source Location	Module
►98.94+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

13% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
20% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
25% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 148 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	86
loop length	344
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.50	5.50	5.33	5.33	6.00	5.33	4.75	4.75	4.75	4.75	11.00	11.00	11.00	7.50	7.50
cycles	4.00	4.00	5.50	5.50	5.33	5.33	6.00	5.33	4.75	4.75	4.75	4.75	11.00	11.00	11.00	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	10.63
Overall L1	11.00-25.00

Vectorization ratios

INT

all	10%
load	0%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	16%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

INT+FP

all	13%
load	0%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

6% of peak load performance is reached (5.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e948

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #672]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W22, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W14, W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W2, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W2, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W23, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f2f8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W19, W22, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W24, W14, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W14, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f2f4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W3, W19, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W24, W3, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W3, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR W6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W4, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W5, W7, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41f364 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W4, W7, W4, W5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W8, W7, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W4, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41f2f4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W11, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W10, W22, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV V29.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMOV V5.2D, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVK X9, #16325	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
FMOV S30, W10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UDIV W12, W4, W11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
FMOV D31, X9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FMOV D9, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D8, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVI V11.4S, #4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MVNI V12.4S, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V13.4S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FMOV V15.2D, #2.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVI V14.4S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X9, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
DUP V16.2S, V30.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V10.4S, V30.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR W10, [SP, #348]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
DUP V6.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDP X13, X27, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD W15, W12, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W16, W12, W11, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SBFM X25, X15, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W18, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X28, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X17, X15, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD W26, W16, W18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W19, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X13, X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X17, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D16, [SP, #328]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STR W6, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																					N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #352	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W5, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 41e9c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

13% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
20% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
25% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 148 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	86
loop length	344
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.50	5.50	5.33	5.33	6.00	5.33	4.75	4.75	4.75	4.75	11.00	11.00	11.00	7.50	7.50
cycles	4.00	4.00	5.50	5.50	5.33	5.33	6.00	5.33	4.75	4.75	4.75	4.75	11.00	11.00	11.00	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	10.63
Overall L1	11.00-25.00

Vectorization ratios

INT

all	10%
load	0%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	16%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

INT+FP

all	13%
load	0%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

6% of peak load performance is reached (5.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e948

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #672]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W22, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W14, W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W2, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W2, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W23, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f2f8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W19, W22, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W24, W14, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W14, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f2f4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W3, W19, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W24, W3, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W3, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR W6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W4, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W5, W7, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41f364 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W4, W7, W4, W5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W8, W7, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W4, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41f2f4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W11, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W10, W22, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV V29.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMOV V5.2D, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVK X9, #16325	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
FMOV S30, W10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UDIV W12, W4, W11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
FMOV D31, X9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FMOV D9, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D8, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVI V11.4S, #4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MVNI V12.4S, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V13.4S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FMOV V15.2D, #2.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVI V14.4S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X9, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
DUP V16.2S, V30.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V10.4S, V30.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR W10, [SP, #348]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
DUP V6.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDP X13, X27, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD W15, W12, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W16, W12, W11, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SBFM X25, X15, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W18, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X28, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X17, X15, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD W26, W16, W18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W19, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X13, X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X17, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D16, [SP, #328]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STR W6, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																					N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #352	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W5, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 41e9c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.20	2.43
▼Loop 209 - context.h:46-69 - exec–	0.00	0.00
▼Loop 210 - advec_cell.cpp:65-110 - exec–	0.00	0.00
▼Loop 211 - advec_cell.cpp:65-110 - exec–	0.00	0.01
○Loop 213 - advec_cell.cpp:71-110 - exec	3.19	2.41
○Loop 212 - advec_cell.cpp:67-110 - exec	0.00	0.01

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code