OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:208-216 [...]	Coverage (incl. loops): 4.22% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 208 - 216

--------------------------------------------------------------------------------

208: #pragma omp parallel for simd collapse(2)

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41e520 STP	X29, X30, [SP, #784]!

0x41e524 ADD	X29, SP, #0

0x41e528 STP	X19, X20, [SP, #16]

0x41e52c ORR	X20, XZR, X0

0x41e530 STP	X21, X22, [SP, #32]

0x41e534 LDP	W22, W2, [X0, #56]

0x41e538 LDP	W1, W0, [X0, #48]

0x41e53c ADD	W3, W2, #2

0x41e540 ADD	W22, W22, #1

0x41e544 ADD	W4, W1, #1

0x41e548 STP	W3, W4, [SP, #168]

0x41e54c CMP	W22, W3

0x41e550 B.GE	41e910

0x41e554 ADD	W19, W0, #2

0x41e558 STP	X23, X24, [SP, #48]

0x41e55c SUB	W23, W3, W22

0x41e560 CMP	W4, W19

0x41e564 B.GE	41e90c

0x41e568 SUB	W5, W19, W4

0x41e56c MADD	W24, W23, W5, WZR

0x41e570 STR	W5, [SP, #200]

0x41e574 BL	403890

0x41e578 ORR	W21, WZR, W0

0x41e57c BL	4038c0

0x41e580 UDIV	W7, W24, W21

0x41e584 ORR	W6, WZR, W0

0x41e588 MSUB	W8, W7, W21, W24

0x41e58c CMP	W0, W8

0x41e590 B.CC	41e93c

  (206) 0x41e594 MADD	W21, W7, W6, W8

  (206) 0x41e598 ADD	W9, W7, W21

  (206) 0x41e59c STR	W9, [SP, #204]

  (206) 0x41e5a0 CMP	W21, W9

  (206) 0x41e5a4 B.CS	41e90c

  (206) 0x41e5a8 LDR	W12, [SP, #200]

  (206) 0x41e5ac STP	X25, X26, [SP, #64]

  (206) 0x41e5b0 STP	X27, X28, [SP, #80]

  (206) 0x41e5b4 UDIV	W13, W21, W12

  (206) 0x41e5b8 LDP	X10, X11, [X20]

  (206) 0x41e5bc LDR	W16, [SP, #172]

  (206) 0x41e5c0 STP	X10, X11, [SP, #208]

  (206) 0x41e5c4 LDP	X30, X18, [X20, #16]

  (206) 0x41e5c8 MSUB	W14, W13, W12, W21

  (206) 0x41e5cc ADD	W15, W13, W22

  (206) 0x41e5d0 SBFM	X22, X15, #0, #31

  (206) 0x41e5d4 ADD	W17, W14, W16

  (206) 0x41e5d8 SUB	W4, W19, W17

  (206) 0x41e5dc STR	X18, [SP, #232]

  (206) 0x41e5e0 LDP	X23, X25, [X20, #32]

  (206) 0x41e5e4 STR	W17, [SP, #112]

  (206) 0x41e5e8 STR	X25, [SP, #224]

    (207) 0x41e5ec CMP	W7, W4

    (207) 0x41e5f0 CSEL	W4, W7, W4, #9

    (207) 0x41e5f4 ADD	W26, W21, W4

    (207) 0x41e5f8 STR	W26, [SP, #116]

    (207) 0x41e5fc CMP	W21, W26

    (207) 0x41e600 B.CS	41e8e4

    (207) 0x41e604 LDP	X28, X2, [SP, #224]

    (207) 0x41e608 LDP	X20, X19, [SP, #208]

    (207) 0x41e60c LDR	X27, [X30]

    (207) 0x41e610 LDR	X1, [X28]

    (207) 0x41e614 LDR	X0, [X2]

    (207) 0x41e618 MADD	X14, X27, X22, XZR

    (207) 0x41e61c LDR	X5, [X20]

    (207) 0x41e620 LDR	X9, [X19]

    (207) 0x41e624 ADD	X24, X27, X14

    (207) 0x41e628 MADD	X27, X0, X22, XZR

    (207) 0x41e62c LDR	X3, [X23]

    (207) 0x41e630 MADD	X7, X22, X5, XZR

    (207) 0x41e634 LDR	X12, [X28, #16]

    (207) 0x41e638 MADD	X28, X1, X22, XZR

    (207) 0x41e63c ADD	X21, X0, X27

    (207) 0x41e640 MADD	X10, X22, X9, XZR

    (207) 0x41e644 LDR	X15, [X23, #16]

    (207) 0x41e648 MADD	X8, X22, X3, XZR

    (207) 0x41e64c ADD	X6, X1, X28

    (207) 0x41e650 STR	X21, [SP, #104]

    (207) 0x41e654 LDR	X13, [X30, #16]

    (207) 0x41e658 LDR	X11, [X2, #16]

    (207) 0x41e65c LDR	X20, [X20, #16]

    (207) 0x41e660 LDR	X19, [X19, #16]

    (207) 0x41e664 STP	X15, X6, [SP, #120]

    (207) 0x41e668 STP	X10, X24, [SP, #136]

    (207) 0x41e66c STP	X8, X7, [SP, #152]

    (207) 0x41e670 CMP	W4, #1

    (207) 0x41e674 B.EQ	41e844

    (207) 0x41e678 UBFM	W18, W4, #1, #31

    (207) 0x41e67c MOVZ	X0, #0

    (207) 0x41e680 LDRSW	X1, [SP, #112]

    (207) 0x41e684 ADD	X3, X14, X1

    (207) 0x41e688 ADD	X26, X8, X1

    (207) 0x41e68c UBFM	X21, X3, #61, #60

    (207) 0x41e690 ADD	X8, X13, X3,LSL #3

    (207) 0x41e694 LDR	X3, [SP, #104]

    (207) 0x41e698 ADD	X5, X6, X1

    (207) 0x41e69c ADD	X17, X7, X1

    (207) 0x41e6a0 ADD	X7, X15, X26,LSL #3

    (207) 0x41e6a4 UBFM	X15, X5, #61, #60

    (207) 0x41e6a8 ADD	X6, X27, X1

    (207) 0x41e6ac ADD	X16, X10, X1

    (207) 0x41e6b0 ADD	X2, X20, X17,LSL #3

    (207) 0x41e6b4 STR	X15, [SP, #176]

    (207) 0x41e6b8 UBFM	X15, X6, #61, #60

    (207) 0x41e6bc ADD	X24, X24, X1

    (207) 0x41e6c0 ADD	X5, X12, X5,LSL #3

    (207) 0x41e6c4 ADD	X25, X28, X1

    (207) 0x41e6c8 ADD	X9, X13, X24,LSL #3

    (207) 0x41e6cc UBFM	X17, X17, #61, #60

    (207) 0x41e6d0 ADD	X1, X3, X1

    (207) 0x41e6d4 STR	X15, [SP, #184]

    (207) 0x41e6d8 ADD	X10, X12, X25,LSL #3

    (207) 0x41e6dc UBFM	X26, X26, #61, #60

    (207) 0x41e6e0 UBFM	X15, X1, #61, #60

    (207) 0x41e6e4 ADD	X3, X19, X16,LSL #3

    (207) 0x41e6e8 UBFM	X24, X24, #61, #60

    (207) 0x41e6ec ADD	X6, X11, X6,LSL #3

    (207) 0x41e6f0 UBFM	X25, X25, #61, #60

    (207) 0x41e6f4 UBFM	X16, X16, #61, #60

    (207) 0x41e6f8 STR	X15, [SP, #192]

    (207) 0x41e6fc ADD	X1, X11, X1,LSL #3

    (207) 0x41e700 UBFM	X15, X18, #60, #59

    (207) 0x41e704 TBZ	W18, #0, 41e780

    (207) 0x41e708 LDR	X0, [SP, #120]

    (207) 0x41e70c LDR	X18, [SP, #176]

    (207) 0x41e710 LDR	Q30, [X20, X17]

    (207) 0x41e714 LDR	Q31, [X0, X26]

    (207) 0x41e718 MOVZ	X0, #16

    (207) 0x41e71c LDR	X26, [SP, #184]

    (207) 0x41e720 LDR	Q0, [X12, X25]

    (207) 0x41e724 LDR	Q29, [X12, X18]

    (207) 0x41e728 FMUL	V3.2D, V30.2D, V31.2D

    (207) 0x41e72c LDR	Q2, [X13, X24]

    (207) 0x41e730 LDR	Q27, [X11, X26]

    (207) 0x41e734 LDR	Q28, [X13, X21]

    (207) 0x41e738 FSUB	V4.2D, V0.2D, V29.2D

    (207) 0x41e73c LDR	X21, [SP, #192]

    (207) 0x41e740 FSUB	V5.2D, V3.2D, V2.2D

    (207) 0x41e744 LDR	Q1, [X19, X16]

    (207) 0x41e748 FADD	V16.2D, V27.2D, V31.2D

    (207) 0x41e74c LDR	Q26, [X11, X21]

    (207) 0x41e750 FADD	V6.2D, V5.2D, V28.2D

    (207) 0x41e754 FMLA	V4.2D, V3.2D, V1.2D

    (207) 0x41e758 FSUB	V17.2D, V16.2D, V26.2D

    (207) 0x41e75c FDIV	V18.2D, V6.2D, V17.2D

    (207) 0x41e760 FDIV	V7.2D, V4.2D, V6.2D

    (207) 0x41e764 STR	Q18, [X20, X17]

    (207) 0x41e768 STR	Q7, [X19, X16]

    (207) 0x41e76c CMP	X15, X0

    (207) 0x41e770 B.EQ	41e830

    (207) 0x41e774 HINT	#0

    (207) 0x41e778 HINT	#0

    (207) 0x41e77c HINT	#0

      (208) 0x41e780 LDR	Q19, [X7, X0]

      (208) 0x41e784 ADD	X17, X0, #16

      (208) 0x41e788 LDR	Q20, [X2, X0]

      (208) 0x41e78c LDR	Q21, [X10, X0]

      (208) 0x41e790 LDR	Q22, [X5, X0]

      (208) 0x41e794 LDR	Q23, [X6, X0]

      (208) 0x41e798 FMUL	V24.2D, V20.2D, V19.2D

      (208) 0x41e79c LDR	Q25, [X9, X0]

      (208) 0x41e7a0 LDR	Q30, [X3, X0]

      (208) 0x41e7a4 FSUB	V0.2D, V21.2D, V22.2D

      (208) 0x41e7a8 LDR	Q1, [X1, X0]

      (208) 0x41e7ac FADD	V28.2D, V23.2D, V19.2D

      (208) 0x41e7b0 LDR	Q31, [X8, X0]

      (208) 0x41e7b4 FSUB	V2.2D, V24.2D, V25.2D

      (208) 0x41e7b8 FMLA	V0.2D, V24.2D, V30.2D

      (208) 0x41e7bc FSUB	V29.2D, V28.2D, V1.2D

      (208) 0x41e7c0 FADD	V3.2D, V2.2D, V31.2D

      (208) 0x41e7c4 FDIV	V4.2D, V3.2D, V29.2D

      (208) 0x41e7c8 FDIV	V5.2D, V0.2D, V3.2D

      (208) 0x41e7cc STR	Q4, [X2, X0]

      (208) 0x41e7d0 STR	Q5, [X3, X0]

      (208) 0x41e7d4 ADD	X0, X0, #32

      (208) 0x41e7d8 LDR	Q6, [X7, X17]

      (208) 0x41e7dc LDR	Q7, [X2, X17]

      (208) 0x41e7e0 LDR	Q27, [X10, X17]

      (208) 0x41e7e4 LDR	Q16, [X5, X17]

      (208) 0x41e7e8 LDR	Q26, [X6, X17]

      (208) 0x41e7ec FMUL	V17.2D, V7.2D, V6.2D

      (208) 0x41e7f0 LDR	Q18, [X9, X17]

      (208) 0x41e7f4 LDR	Q19, [X3, X17]

      (208) 0x41e7f8 FSUB	V23.2D, V27.2D, V16.2D

      (208) 0x41e7fc LDR	Q20, [X1, X17]

      (208) 0x41e800 FADD	V21.2D, V26.2D, V6.2D

      (208) 0x41e804 LDR	Q22, [X8, X17]

      (208) 0x41e808 FSUB	V24.2D, V17.2D, V18.2D

      (208) 0x41e80c FMLA	V23.2D, V17.2D, V19.2D

      (208) 0x41e810 FSUB	V25.2D, V21.2D, V20.2D

      (208) 0x41e814 FADD	V30.2D, V24.2D, V22.2D

      (208) 0x41e818 FDIV	V0.2D, V30.2D, V25.2D

      (208) 0x41e81c FDIV	V1.2D, V23.2D, V30.2D

      (208) 0x41e820 STR	Q0, [X2, X17]

      (208) 0x41e824 STR	Q1, [X3, X17]

      (208) 0x41e828 CMP	X15, X0

      (208) 0x41e82c B.NE	41e780

    (207) 0x41e830 TBZ	W4, #0, 41e8e0

    (207) 0x41e834 LDR	W2, [SP, #112]

    (207) 0x41e838 AND	W4, W4, #1951

    (207) 0x41e83c ADD	W7, W2, W4

    (207) 0x41e840 STR	W7, [SP, #112]

    (207) 0x41e844 LDR	X6, [SP, #128]

    (207) 0x41e848 LDRSW	X8, [SP, #112]

    (207) 0x41e84c LDR	X10, [SP, #160]

    (207) 0x41e850 LDR	X5, [SP, #152]

    (207) 0x41e854 ADD	X28, X28, X8

    (207) 0x41e858 ADD	X1, X6, X8

    (207) 0x41e85c LDR	X24, [SP, #120]

    (207) 0x41e860 ADD	X14, X14, X8

    (207) 0x41e864 ADD	X27, X27, X8

    (207) 0x41e868 ADD	X25, X10, X8

    (207) 0x41e86c LDR	D2, [X12, X28,LSL #3]

    (207) 0x41e870 UBFM	X3, X25, #61, #60

    (207) 0x41e874 ADD	X16, X5, X8

    (207) 0x41e878 LDR	D5, [X12, X1,LSL #3]

    (207) 0x41e87c LDR	X12, [SP, #144]

    (207) 0x41e880 LDR	D31, [X24, X16,LSL #3]

    (207) 0x41e884 LDR	D3, [X20, X3]

    (207) 0x41e888 FSUB	D7, D2, S5

    (207) 0x41e88c ADD	X15, X12, X8

    (207) 0x41e890 LDR	D28, [X13, X14,LSL #3]

    (207) 0x41e894 LDR	D27, [X13, X15,LSL #3]

    (207) 0x41e898 LDR	X13, [SP, #136]

    (207) 0x41e89c FMUL	D4, D31, D3

    (207) 0x41e8a0 LDR	X9, [SP, #104]

    (207) 0x41e8a4 LDR	D29, [X11, X27,LSL #3]

    (207) 0x41e8a8 ADD	X18, X13, X8

    (207) 0x41e8ac UBFM	X26, X18, #61, #60

    (207) 0x41e8b0 FSUB	D16, D4, S27

    (207) 0x41e8b4 ADD	X0, X9, X8

    (207) 0x41e8b8 LDR	D18, [X19, X26]

    (207) 0x41e8bc LDR	D26, [X11, X0,LSL #3]

    (207) 0x41e8c0 FADD	D6, D31, D29

    (207) 0x41e8c4 FADD	D17, D16, D28

    (207) 0x41e8c8 FMADD	D19, D18, D4, D7

    (207) 0x41e8cc FSUB	D23, D6, S26

    (207) 0x41e8d0 FDIV	D20, D17, D23

    (207) 0x41e8d4 FDIV	D21, D19, D17

    (207) 0x41e8d8 STR	D20, [X20, X3]

    (207) 0x41e8dc STR	D21, [X19, X26]

    (207) 0x41e8e0 LDR	W21, [SP, #116]

    (207) 0x41e8e4 ADD	X22, X22, #1

    (207) 0x41e8e8 LDR	W11, [SP, #168]

    (207) 0x41e8ec CMP	W11, W22

    (207) 0x41e8f0 B.LE	41e920

    (207) 0x41e8f4 LDR	W20, [SP, #172]

    (207) 0x41e8f8 LDR	W19, [SP, #204]

    (207) 0x41e8fc LDR	W4, [SP, #200]

    (207) 0x41e900 STR	W20, [SP, #112]

    (207) 0x41e904 SUB	W7, W19, W21

    (207) 0x41e908 B	41e5ec

(205) 0x41e90c LDP	X23, X24, [SP, #48]

(205) 0x41e910 LDP	X19, X20, [SP, #16]

(205) 0x41e914 LDP	X21, X22, [SP, #32]

(205) 0x41e918 LDP	X29, X30, [SP], #240

(205) 0x41e91c RET

  (206) 0x41e920 LDP	X23, X24, [SP, #48]

  (206) 0x41e924 LDP	X25, X26, [SP, #64]

  (206) 0x41e928 LDP	X27, X28, [SP, #80]

  (206) 0x41e92c LDP	X19, X20, [SP, #16]

  (206) 0x41e930 LDP	X21, X22, [SP, #32]

  (206) 0x41e934 LDP	X29, X30, [SP], #240

  (206) 0x41e938 RET

  (206) 0x41e93c ADD	W7, W7, #1

  (206) 0x41e940 MOVZ	W8, #0

  (206) 0x41e944 B	41e594

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #784]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e910 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W3, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e90c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41e93c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #784]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e910 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W3, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e90c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41e93c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.22	3.20
▼Loop 205 - advec_cell.cpp:208-216 - exec–	0.00	0.00
▼Loop 206 - advec_cell.cpp:208-216 - exec–	0.00	0.00
▼Loop 207 - advec_cell.cpp:210-216 - exec–	0.00	0.01
○Loop 208 - advec_cell.cpp:211-216 - exec	4.22	3.18

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code