OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:146-150 [...]	Coverage (incl. loops): 1.13% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 146 - 150

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

148:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

149:           pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

150:           post_vol(i, j) = volume(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41e1c8 STP	X29, X30, [SP, #912]!

0x41e1cc ADD	X29, SP, #0

0x41e1d0 STP	X19, X20, [SP, #16]

0x41e1d4 ORR	X20, XZR, X0

0x41e1d8 STP	X21, X22, [SP, #32]

0x41e1dc STP	X23, X24, [SP, #48]

0x41e1e0 LDP	W22, W1, [X0, #40]

0x41e1e4 LDP	W0, W2, [X0, #32]

0x41e1e8 SUB	W22, W22, #1

0x41e1ec ADD	W24, W1, #4

0x41e1f0 SUB	W3, W0, #1

0x41e1f4 STR	W3, [SP, #96]

0x41e1f8 CMP	W22, W24

0x41e1fc B.GE	41e4f8

0x41e200 ADD	W19, W2, #4

0x41e204 SUB	W23, W24, W22

0x41e208 CMP	W3, W19

0x41e20c B.GE	41e4f8

0x41e210 SUB	W4, W19, W3

0x41e214 MADD	W23, W23, W4, WZR

0x41e218 STR	W4, [SP, #100]

0x41e21c BL	403890

0x41e220 ORR	W21, WZR, W0

0x41e224 BL	4038c0

0x41e228 UDIV	W6, W23, W21

0x41e22c ORR	W5, WZR, W0

0x41e230 MSUB	W7, W6, W21, W23

0x41e234 CMP	W0, W7

0x41e238 B.CC	41e50c

(201) 0x41e23c MADD	W23, W6, W5, W7

(201) 0x41e240 ADD	W8, W6, W23

(201) 0x41e244 STR	W8, [SP, #104]

(201) 0x41e248 CMP	W23, W8

(201) 0x41e24c B.CS	41e4f8

(201) 0x41e250 LDR	W9, [SP, #100]

(201) 0x41e254 STP	X25, X26, [SP, #64]

(201) 0x41e258 LDR	W13, [SP, #96]

(201) 0x41e25c UDIV	W10, W23, W9

(201) 0x41e260 STP	X27, X28, [SP, #80]

(201) 0x41e264 LDP	X27, X28, [X20]

(201) 0x41e268 LDP	X25, X26, [X20, #16]

(201) 0x41e26c STR	W24, [SP, #108]

(201) 0x41e270 MSUB	W11, W10, W9, W23

(201) 0x41e274 ADD	W12, W10, W22

(201) 0x41e278 SBFM	X9, X12, #0, #31

(201) 0x41e27c ADD	W5, W11, W13

(201) 0x41e280 SUB	W21, W19, W5

(201) 0x41e284 CMP	W6, W21

(201) 0x41e288 CSEL	W3, W6, W21, #9

(201) 0x41e28c ADD	W22, W23, W3

(201) 0x41e290 CMP	W23, W22

(201) 0x41e294 B.CS	41e4dc

(201) 0x41e298 HINT	#0

(201) 0x41e29c HINT	#0

  (202) 0x41e2a0 LDR	X15, [X26]

  (202) 0x41e2a4 ADD	X30, X9, #1

  (202) 0x41e2a8 LDR	X17, [X28]

  (202) 0x41e2ac LDR	X16, [X27]

  (202) 0x41e2b0 MADD	X4, X9, X15, XZR

  (202) 0x41e2b4 LDR	X14, [X25]

  (202) 0x41e2b8 MADD	X15, X9, X17, X17

  (202) 0x41e2bc LDR	X24, [X25, #16]

  (202) 0x41e2c0 MADD	X11, X9, X16, XZR

  (202) 0x41e2c4 LDR	X23, [X26, #16]

  (202) 0x41e2c8 SUB	X12, X15, X17

  (202) 0x41e2cc MADD	X14, X9, X14, XZR

  (202) 0x41e2d0 LDR	X21, [X27, #16]

  (202) 0x41e2d4 LDR	X16, [X28, #16]

  (202) 0x41e2d8 CMP	W3, #1

  (202) 0x41e2dc B.EQ	41e468

  (202) 0x41e2e0 UBFM	W18, W3, #1, #31

  (202) 0x41e2e4 SBFM	X2, X5, #0, #31

  (202) 0x41e2e8 UBFM	X13, X18, #60, #59

  (202) 0x41e2ec ADD	X6, X11, X2

  (202) 0x41e2f0 SUB	X19, X13, #16

  (202) 0x41e2f4 ADD	X20, X15, X2

  (202) 0x41e2f8 ADD	X1, X21, X6,LSL #3

  (202) 0x41e2fc UBFM	X7, X19, #4, #63

  (202) 0x41e300 ADD	X18, X14, X2

  (202) 0x41e304 ADD	X9, X16, X20,LSL #3

  (202) 0x41e308 ADD	X10, X7, #1

  (202) 0x41e30c ADD	X19, X12, X2

  (202) 0x41e310 ADD	X7, X24, X18,LSL #3

  (202) 0x41e314 ADD	X2, X4, X2

  (202) 0x41e318 ANDS	X10, X10, #4160

  (202) 0x41e31c ADD	X8, X16, X19,LSL #3

  (202) 0x41e320 UBFM	X17, X6, #61, #60

  (202) 0x41e324 MOVZ	X0, #0

  (202) 0x41e328 ADD	X6, X23, X2,LSL #3

  (202) 0x41e32c UBFM	X20, X20, #61, #60

  (202) 0x41e330 UBFM	X19, X19, #61, #60

  (202) 0x41e334 UBFM	X18, X18, #61, #60

  (202) 0x41e338 UBFM	X2, X2, #61, #60

  (202) 0x41e33c B.EQ	41e3c4

  (202) 0x41e340 CMP	X10, #1

  (202) 0x41e344 B.EQ	41e398

  (202) 0x41e348 CMP	X10, #2

  (202) 0x41e34c B.EQ	41e374

  (202) 0x41e350 LDR	Q0, [X21, X17]

  (202) 0x41e354 MOVZ	X0, #16

  (202) 0x41e358 LDR	Q30, [X16, X20]

  (202) 0x41e35c LDR	Q31, [X16, X19]

  (202) 0x41e360 FADD	V1.2D, V0.2D, V30.2D

  (202) 0x41e364 FSUB	V2.2D, V1.2D, V31.2D

  (202) 0x41e368 STR	Q2, [X24, X18]

  (202) 0x41e36c LDR	Q3, [X21, X17]

  (202) 0x41e370 STR	Q3, [X23, X2]

  (202) 0x41e374 LDR	Q4, [X1, X0]

  (202) 0x41e378 LDR	Q28, [X9, X0]

  (202) 0x41e37c LDR	Q29, [X8, X0]

  (202) 0x41e380 FADD	V5.2D, V4.2D, V28.2D

  (202) 0x41e384 FSUB	V6.2D, V5.2D, V29.2D

  (202) 0x41e388 STR	Q6, [X7, X0]

  (202) 0x41e38c LDR	Q7, [X1, X0]

  (202) 0x41e390 STR	Q7, [X6, X0]

  (202) 0x41e394 ADD	X0, X0, #16

  (202) 0x41e398 LDR	Q16, [X1, X0]

  (202) 0x41e39c LDR	Q26, [X9, X0]

  (202) 0x41e3a0 LDR	Q27, [X8, X0]

  (202) 0x41e3a4 FADD	V17.2D, V16.2D, V26.2D

  (202) 0x41e3a8 FSUB	V18.2D, V17.2D, V27.2D

  (202) 0x41e3ac STR	Q18, [X7, X0]

  (202) 0x41e3b0 LDR	Q19, [X1, X0]

  (202) 0x41e3b4 STR	Q19, [X6, X0]

  (202) 0x41e3b8 ADD	X0, X0, #16

  (202) 0x41e3bc CMP	X0, X13

  (202) 0x41e3c0 B.EQ	41e45c

    (203) 0x41e3c4 LDR	Q20, [X1, X0]

    (203) 0x41e3c8 ADD	X20, X0, #16

    (203) 0x41e3cc ADD	X17, X0, #32

    (203) 0x41e3d0 ADD	X10, X0, #48

    (203) 0x41e3d4 LDR	Q21, [X9, X0]

    (203) 0x41e3d8 LDR	Q22, [X8, X0]

    (203) 0x41e3dc FADD	V23.2D, V20.2D, V21.2D

    (203) 0x41e3e0 FSUB	V24.2D, V23.2D, V22.2D

    (203) 0x41e3e4 STR	Q24, [X7, X0]

    (203) 0x41e3e8 LDR	Q25, [X1, X0]

    (203) 0x41e3ec STR	Q25, [X6, X0]

    (203) 0x41e3f0 ADD	X0, X0, #64

    (203) 0x41e3f4 LDR	Q0, [X1, X20]

    (203) 0x41e3f8 LDR	Q30, [X9, X20]

    (203) 0x41e3fc LDR	Q31, [X8, X20]

    (203) 0x41e400 FADD	V1.2D, V0.2D, V30.2D

    (203) 0x41e404 FSUB	V2.2D, V1.2D, V31.2D

    (203) 0x41e408 STR	Q2, [X7, X20]

    (203) 0x41e40c LDR	Q3, [X1, X20]

    (203) 0x41e410 STR	Q3, [X6, X20]

    (203) 0x41e414 LDR	Q4, [X1, X17]

    (203) 0x41e418 LDR	Q28, [X9, X17]

    (203) 0x41e41c LDR	Q29, [X8, X17]

    (203) 0x41e420 FADD	V5.2D, V4.2D, V28.2D

    (203) 0x41e424 FSUB	V6.2D, V5.2D, V29.2D

    (203) 0x41e428 STR	Q6, [X7, X17]

    (203) 0x41e42c LDR	Q7, [X1, X17]

    (203) 0x41e430 STR	Q7, [X6, X17]

    (203) 0x41e434 LDR	Q16, [X1, X10]

    (203) 0x41e438 LDR	Q26, [X9, X10]

    (203) 0x41e43c LDR	Q27, [X8, X10]

    (203) 0x41e440 FADD	V17.2D, V16.2D, V26.2D

    (203) 0x41e444 FSUB	V18.2D, V17.2D, V27.2D

    (203) 0x41e448 STR	Q18, [X7, X10]

    (203) 0x41e44c LDR	Q19, [X1, X10]

    (203) 0x41e450 STR	Q19, [X6, X10]

    (203) 0x41e454 CMP	X0, X13

    (203) 0x41e458 B.NE	41e3c4

  (202) 0x41e45c TBZ	W3, #0, 41e4a4

  (202) 0x41e460 AND	W3, W3, #1951

  (202) 0x41e464 ADD	W5, W5, W3

  (202) 0x41e468 SBFM	X13, X5, #0, #31

  (202) 0x41e46c ADD	X11, X11, X13

  (202) 0x41e470 ADD	X15, X15, X13

  (202) 0x41e474 UBFM	X1, X11, #61, #60

  (202) 0x41e478 ADD	X12, X12, X13

  (202) 0x41e47c LDR	D20, [X16, X15,LSL #3]

  (202) 0x41e480 ADD	X14, X14, X13

  (202) 0x41e484 ADD	X4, X4, X13

  (202) 0x41e488 LDR	D21, [X21, X1]

  (202) 0x41e48c LDR	D22, [X16, X12,LSL #3]

  (202) 0x41e490 FADD	D23, D20, D21

  (202) 0x41e494 FSUB	D24, D23, S22

  (202) 0x41e498 STR	D24, [X24, X14,LSL #3]

  (202) 0x41e49c LDR	D25, [X21, X1]

  (202) 0x41e4a0 STR	D25, [X23, X4,LSL #3]

  (202) 0x41e4a4 ORR	W23, WZR, W22

  (202) 0x41e4a8 LDR	W22, [SP, #108]

  (202) 0x41e4ac ORR	X9, XZR, X30

  (202) 0x41e4b0 CMP	W22, W30

  (202) 0x41e4b4 B.LE	41e4f0

  (202) 0x41e4b8 LDR	W30, [SP, #104]

  (202) 0x41e4bc LDR	W21, [SP, #100]

  (202) 0x41e4c0 LDR	W5, [SP, #96]

  (202) 0x41e4c4 SUB	W6, W30, W23

  (202) 0x41e4c8 CMP	W6, W21

  (202) 0x41e4cc CSEL	W3, W6, W21, #9

  (202) 0x41e4d0 ADD	W22, W23, W3

  (202) 0x41e4d4 CMP	W23, W22

  (202) 0x41e4d8 B.CC	41e2a0

  (204) 0x41e4dc LDR	W22, [SP, #108]

  (204) 0x41e4e0 ADD	X30, X9, #1

  (204) 0x41e4e4 ORR	X9, XZR, X30

  (204) 0x41e4e8 CMP	W22, W30

  (204) 0x41e4ec B.GT	41e4b8

(201) 0x41e4f0 LDP	X25, X26, [SP, #64]

(201) 0x41e4f4 LDP	X27, X28, [SP, #80]

(201) 0x41e4f8 LDP	X19, X20, [SP, #16]

(201) 0x41e4fc LDP	X21, X22, [SP, #32]

(201) 0x41e500 LDP	X23, X24, [SP, #48]

(201) 0x41e504 LDP	X29, X30, [SP], #112

(201) 0x41e508 RET

(201) 0x41e50c ADD	W6, W6, #1

(201) 0x41e510 MOVZ	W7, #0

(201) 0x41e514 B	41e23c

0x41e518 HINT	#0

0x41e51c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.97+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.02+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:146	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:81	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:146-150
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146-150
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 42% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e1c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W24, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W3, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e4f8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W24, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W3, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e4f8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W4, W19, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W23, W23, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W4, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W7, W6, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 41e50c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:146-150
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146-150
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e1c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W24, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W3, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e4f8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W24, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W3, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e4f8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W4, W19, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W23, W23, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W4, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W7, W6, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 41e50c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.13	0.86
▼Loop 201 - advec_cell.cpp:146-150 - exec–	0.00	0.00
▼Loop 202 - advec_cell.cpp:148-150 - exec–	0.00	0.00
○Loop 203 - advec_cell.cpp:149-150 - exec	1.13	0.85
○Loop 204 - advec_cell.cpp:148-148 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code