OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:136-140 [...]	Coverage (incl. loops): 1.42% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 136 - 140

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41dd20 STP	X29, X30, [SP, #848]!

0x41dd24 ADD	X29, SP, #0

0x41dd28 STP	X19, X20, [SP, #16]

0x41dd2c ORR	X19, XZR, X0

0x41dd30 STP	X23, X24, [SP, #48]

0x41dd34 LDP	W23, W1, [X0, #48]

0x41dd38 LDP	W0, W2, [X0, #40]

0x41dd3c ADD	W3, W1, #4

0x41dd40 SUB	W23, W23, #1

0x41dd44 SUB	W4, W0, #1

0x41dd48 STP	W3, W4, [SP, #136]

0x41dd4c CMP	W23, W3

0x41dd50 B.GE	41e198

0x41dd54 STP	X21, X22, [SP, #32]

0x41dd58 ADD	W22, W2, #4

0x41dd5c SUB	W21, W3, W23

0x41dd60 CMP	W4, W22

0x41dd64 B.GE	41e1a8

0x41dd68 SUB	W5, W22, W4

0x41dd6c MADD	W24, W21, W5, WZR

0x41dd70 STR	W5, [SP, #144]

0x41dd74 BL	403890

0x41dd78 ORR	W20, WZR, W0

0x41dd7c BL	4038c0

0x41dd80 UDIV	W6, W24, W20

0x41dd84 ORR	W7, WZR, W0

0x41dd88 MSUB	W8, W6, W20, W24

0x41dd8c CMP	W0, W8

0x41dd90 B.CC	41e1bc

  (196) 0x41dd94 MADD	W5, W6, W7, W8

  (196) 0x41dd98 ADD	W9, W6, W5

  (196) 0x41dd9c STR	W9, [SP, #148]

  (196) 0x41dda0 CMP	W5, W9

  (196) 0x41dda4 B.CS	41e1a8

(197) 0x41dda8 LDP	W10, W11, [SP, #140]

(197) 0x41ddac STP	X27, X28, [SP, #80]

(197) 0x41ddb0 STP	X25, X26, [SP, #64]

(197) 0x41ddb4 UDIV	W12, W5, W11

(197) 0x41ddb8 LDR	X27, [X19, #32]

(197) 0x41ddbc LDP	X24, X25, [X19]

(197) 0x41ddc0 LDP	X26, X4, [X19, #16]

(197) 0x41ddc4 MSUB	W13, W12, W11, W5

(197) 0x41ddc8 ADD	W14, W12, W23

(197) 0x41ddcc SBFM	X0, X14, #0, #31

(197) 0x41ddd0 ADD	W28, W13, W10

(197) 0x41ddd4 SUB	W14, W22, W28

(197) 0x41ddd8 CMP	W6, W14

(197) 0x41dddc CSEL	W6, W6, W14, #9

(197) 0x41dde0 ADD	W20, W5, W6

(197) 0x41dde4 CMP	W5, W20

(197) 0x41dde8 B.CS	41e174

  (198) 0x41ddec LDR	X17, [X4]

  (198) 0x41ddf0 ADD	X16, X0, #1

  (198) 0x41ddf4 LDR	X19, [X26]

  (198) 0x41ddf8 LDR	X30, [X25]

  (198) 0x41ddfc MADD	X18, X0, X17, XZR

  (198) 0x41de00 LDR	X23, [X4, #16]

  (198) 0x41de04 MADD	X12, X0, X19, X19

  (198) 0x41de08 LDR	X21, [X24, #16]

  (198) 0x41de0c MADD	X13, X0, X30, XZR

  (198) 0x41de10 LDR	X15, [X25, #16]

  (198) 0x41de14 SUB	X3, X12, X19

  (198) 0x41de18 LDR	X14, [X26, #16]

  (198) 0x41de1c LDR	X22, [X27, #16]

  (198) 0x41de20 STP	X16, X18, [SP, #104]

  (198) 0x41de24 LDR	X1, [X24]

  (198) 0x41de28 MADD	X7, X0, X1, XZR

  (198) 0x41de2c STP	X3, X7, [SP, #120]

  (198) 0x41de30 LDR	X2, [X27]

  (198) 0x41de34 MADD	X30, X0, X2, XZR

  (198) 0x41de38 CMP	W6, #1

  (198) 0x41de3c B.EQ	41e0cc

  (198) 0x41de40 SBFM	X8, X28, #0, #31

  (198) 0x41de44 UBFM	W5, W6, #1, #31

  (198) 0x41de48 ADD	X9, X13, X8

  (198) 0x41de4c UBFM	X11, X5, #60, #59

  (198) 0x41de50 ADD	X16, X9, #1

  (198) 0x41de54 SUB	X10, X11, #16

  (198) 0x41de58 ADD	X5, X15, X16,LSL #3

  (198) 0x41de5c UBFM	X2, X16, #61, #60

  (198) 0x41de60 UBFM	X17, X10, #4, #63

  (198) 0x41de64 ADD	X1, X30, X8

  (198) 0x41de68 ADD	X7, X7, X8

  (198) 0x41de6c ADD	X19, X17, #1

  (198) 0x41de70 ADD	X16, X12, X8

  (198) 0x41de74 STR	X2, [SP, #152]

  (198) 0x41de78 ADD	X9, X21, X7,LSL #3

  (198) 0x41de7c STR	X5, [SP, #96]

  (198) 0x41de80 SUB	X5, X2, #8

  (198) 0x41de84 ADD	X17, X3, X8

  (198) 0x41de88 ADD	X2, X14, X16,LSL #3

  (198) 0x41de8c ADD	X18, X18, X8

  (198) 0x41de90 ADD	X8, X15, X5

  (198) 0x41de94 ADD	X3, X14, X17,LSL #3

  (198) 0x41de98 STR	X5, [SP, #160]

  (198) 0x41de9c UBFM	X5, X1, #61, #60

  (198) 0x41dea0 ANDS	X10, X19, #4160

  (198) 0x41dea4 ADD	X1, X22, X1,LSL #3

  (198) 0x41dea8 UBFM	X19, X7, #61, #60

  (198) 0x41deac MOVZ	X0, #0

  (198) 0x41deb0 ADD	X7, X23, X18,LSL #3

  (198) 0x41deb4 STR	X5, [SP, #168]

  (198) 0x41deb8 UBFM	X18, X18, #61, #60

  (198) 0x41debc UBFM	X16, X16, #61, #60

  (198) 0x41dec0 UBFM	X17, X17, #61, #60

  (198) 0x41dec4 B.EQ	41dfb4

  (198) 0x41dec8 CMP	X10, #1

  (198) 0x41decc B.EQ	41df68

  (198) 0x41ded0 CMP	X10, #2

  (198) 0x41ded4 B.EQ	41df24

  (198) 0x41ded8 LDR	Q3, [X21, X19]

  (198) 0x41dedc MOVZ	X0, #16

  (198) 0x41dee0 LDR	Q2, [X14, X16]

  (198) 0x41dee4 LDR	X10, [SP, #152]

  (198) 0x41dee8 LDR	X19, [SP, #160]

  (198) 0x41deec LDR	Q0, [X14, X17]

  (198) 0x41def0 FADD	V4.2D, V3.2D, V2.2D

  (198) 0x41def4 LDR	Q1, [X15, X10]

  (198) 0x41def8 LDR	Q30, [X15, X19]

  (198) 0x41defc FADD	V5.2D, V4.2D, V1.2D

  (198) 0x41df00 FADD	V6.2D, V0.2D, V30.2D

  (198) 0x41df04 FSUB	V7.2D, V5.2D, V6.2D

  (198) 0x41df08 STR	Q7, [X23, X18]

  (198) 0x41df0c LDR	Q29, [X14, X17]

  (198) 0x41df10 LDR	Q31, [X14, X16]

  (198) 0x41df14 LDR	X18, [SP, #168]

  (198) 0x41df18 FSUB	V16.2D, V29.2D, V31.2D

  (198) 0x41df1c FADD	V17.2D, V16.2D, V7.2D

  (198) 0x41df20 STR	Q17, [X22, X18]

  (198) 0x41df24 LDR	Q18, [X9, X0]

  (198) 0x41df28 LDR	Q19, [X2, X0]

  (198) 0x41df2c LDR	X16, [SP, #96]

  (198) 0x41df30 LDR	Q20, [X3, X0]

  (198) 0x41df34 LDR	Q27, [X8, X0]

  (198) 0x41df38 FADD	V21.2D, V18.2D, V19.2D

  (198) 0x41df3c LDR	Q23, [X16, X0]

  (198) 0x41df40 FADD	V22.2D, V20.2D, V27.2D

  (198) 0x41df44 FADD	V24.2D, V21.2D, V23.2D

  (198) 0x41df48 FSUB	V25.2D, V24.2D, V22.2D

  (198) 0x41df4c STR	Q25, [X7, X0]

  (198) 0x41df50 LDR	Q26, [X3, X0]

  (198) 0x41df54 LDR	Q28, [X2, X0]

  (198) 0x41df58 FSUB	V3.2D, V26.2D, V28.2D

  (198) 0x41df5c FADD	V2.2D, V3.2D, V25.2D

  (198) 0x41df60 STR	Q2, [X1, X0]

  (198) 0x41df64 ADD	X0, X0, #16

  (198) 0x41df68 LDR	Q0, [X9, X0]

  (198) 0x41df6c LDR	Q4, [X2, X0]

  (198) 0x41df70 LDR	X17, [SP, #96]

  (198) 0x41df74 LDR	Q1, [X3, X0]

  (198) 0x41df78 LDR	Q5, [X8, X0]

  (198) 0x41df7c FADD	V30.2D, V0.2D, V4.2D

  (198) 0x41df80 LDR	Q7, [X17, X0]

  (198) 0x41df84 FADD	V6.2D, V1.2D, V5.2D

  (198) 0x41df88 FADD	V29.2D, V30.2D, V7.2D

  (198) 0x41df8c FSUB	V31.2D, V29.2D, V6.2D

  (198) 0x41df90 STR	Q31, [X7, X0]

  (198) 0x41df94 LDR	Q16, [X3, X0]

  (198) 0x41df98 LDR	Q17, [X2, X0]

  (198) 0x41df9c FSUB	V18.2D, V16.2D, V17.2D

  (198) 0x41dfa0 FADD	V19.2D, V18.2D, V31.2D

  (198) 0x41dfa4 STR	Q19, [X1, X0]

  (198) 0x41dfa8 ADD	X0, X0, #16

  (198) 0x41dfac CMP	X11, X0

  (198) 0x41dfb0 B.EQ	41e0c0

  (198) 0x41dfb4 LDR	X5, [SP, #96]

    (199) 0x41dfb8 ADD	X10, X0, #16

    (199) 0x41dfbc ADD	X18, X0, #32

    (199) 0x41dfc0 LDR	Q20, [X9, X0]

    (199) 0x41dfc4 ADD	X19, X0, #48

    (199) 0x41dfc8 LDR	Q27, [X2, X0]

    (199) 0x41dfcc LDR	Q21, [X5, X0]

    (199) 0x41dfd0 LDR	Q22, [X3, X0]

    (199) 0x41dfd4 LDR	Q23, [X8, X0]

    (199) 0x41dfd8 FADD	V24.2D, V20.2D, V27.2D

    (199) 0x41dfdc FADD	V26.2D, V22.2D, V23.2D

    (199) 0x41dfe0 FADD	V25.2D, V24.2D, V21.2D

    (199) 0x41dfe4 FSUB	V28.2D, V25.2D, V26.2D

    (199) 0x41dfe8 STR	Q28, [X7, X0]

    (199) 0x41dfec LDR	Q3, [X3, X0]

    (199) 0x41dff0 LDR	Q2, [X2, X0]

    (199) 0x41dff4 FSUB	V0.2D, V3.2D, V2.2D

    (199) 0x41dff8 FADD	V4.2D, V0.2D, V28.2D

    (199) 0x41dffc STR	Q4, [X1, X0]

    (199) 0x41e000 ADD	X0, X0, #64

    (199) 0x41e004 LDR	Q1, [X9, X10]

    (199) 0x41e008 LDR	Q5, [X2, X10]

    (199) 0x41e00c LDR	Q30, [X5, X10]

    (199) 0x41e010 LDR	Q6, [X3, X10]

    (199) 0x41e014 LDR	Q7, [X8, X10]

    (199) 0x41e018 FADD	V29.2D, V1.2D, V5.2D

    (199) 0x41e01c FADD	V31.2D, V6.2D, V7.2D

    (199) 0x41e020 FADD	V16.2D, V29.2D, V30.2D

    (199) 0x41e024 FSUB	V17.2D, V16.2D, V31.2D

    (199) 0x41e028 STR	Q17, [X7, X10]

    (199) 0x41e02c LDR	Q18, [X3, X10]

    (199) 0x41e030 LDR	Q19, [X2, X10]

    (199) 0x41e034 FSUB	V20.2D, V18.2D, V19.2D

    (199) 0x41e038 FADD	V27.2D, V20.2D, V17.2D

    (199) 0x41e03c STR	Q27, [X1, X10]

    (199) 0x41e040 LDR	Q21, [X9, X18]

    (199) 0x41e044 LDR	Q22, [X2, X18]

    (199) 0x41e048 LDR	Q23, [X5, X18]

    (199) 0x41e04c LDR	Q24, [X3, X18]

    (199) 0x41e050 LDR	Q25, [X8, X18]

    (199) 0x41e054 FADD	V26.2D, V21.2D, V22.2D

    (199) 0x41e058 FADD	V28.2D, V24.2D, V25.2D

    (199) 0x41e05c FADD	V3.2D, V26.2D, V23.2D

    (199) 0x41e060 FSUB	V2.2D, V3.2D, V28.2D

    (199) 0x41e064 STR	Q2, [X7, X18]

    (199) 0x41e068 LDR	Q0, [X3, X18]

    (199) 0x41e06c LDR	Q4, [X2, X18]

    (199) 0x41e070 FSUB	V1.2D, V0.2D, V4.2D

    (199) 0x41e074 FADD	V5.2D, V1.2D, V2.2D

    (199) 0x41e078 STR	Q5, [X1, X18]

    (199) 0x41e07c LDR	Q30, [X9, X19]

    (199) 0x41e080 LDR	Q6, [X2, X19]

    (199) 0x41e084 LDR	Q7, [X5, X19]

    (199) 0x41e088 LDR	Q29, [X3, X19]

    (199) 0x41e08c LDR	Q31, [X8, X19]

    (199) 0x41e090 FADD	V16.2D, V30.2D, V6.2D

    (199) 0x41e094 FADD	V17.2D, V29.2D, V31.2D

    (199) 0x41e098 FADD	V18.2D, V16.2D, V7.2D

    (199) 0x41e09c FSUB	V19.2D, V18.2D, V17.2D

    (199) 0x41e0a0 STR	Q19, [X7, X19]

    (199) 0x41e0a4 LDR	Q20, [X3, X19]

    (199) 0x41e0a8 LDR	Q27, [X2, X19]

    (199) 0x41e0ac FSUB	V21.2D, V20.2D, V27.2D

    (199) 0x41e0b0 FADD	V22.2D, V21.2D, V19.2D

    (199) 0x41e0b4 STR	Q22, [X1, X19]

    (199) 0x41e0b8 CMP	X11, X0

    (199) 0x41e0bc B.NE	41dfb8

  (198) 0x41e0c0 TBZ	W6, #0, 41e13c

  (198) 0x41e0c4 AND	W6, W6, #1951

  (198) 0x41e0c8 ADD	W28, W28, W6

  (198) 0x41e0cc SBFM	X11, X28, #0, #31

  (198) 0x41e0d0 ADD	W9, W28, #1

  (198) 0x41e0d4 ADD	X7, X13, W9,SXTW

  (198) 0x41e0d8 LDR	D23, [X15, X7,LSL #3]

  (198) 0x41e0dc ADD	X13, X13, X11

  (198) 0x41e0e0 ADD	X12, X12, X11

  (198) 0x41e0e4 UBFM	X8, X12, #61, #60

  (198) 0x41e0e8 ADD	X30, X30, X11

  (198) 0x41e0ec LDR	D25, [X15, X13,LSL #3]

  (198) 0x41e0f0 LDR	X15, [SP, #128]

  (198) 0x41e0f4 LDR	D24, [X14, X8]

  (198) 0x41e0f8 ADD	X2, X15, X11

  (198) 0x41e0fc LDR	D26, [X21, X2,LSL #3]

  (198) 0x41e100 LDP	X21, X3, [SP, #112]

  (198) 0x41e104 ADD	X1, X3, X11

  (198) 0x41e108 FADD	D28, D26, D24

  (198) 0x41e10c ADD	X17, X21, X11

  (198) 0x41e110 UBFM	X16, X1, #61, #60

  (198) 0x41e114 LDR	D2, [X14, X16]

  (198) 0x41e118 FSUB	D3, D28, S25

  (198) 0x41e11c FSUB	D0, D23, S2

  (198) 0x41e120 FADD	D4, D3, D0

  (198) 0x41e124 STR	D4, [X23, X17,LSL #3]

  (198) 0x41e128 LDR	D1, [X14, X16]

  (198) 0x41e12c LDR	D5, [X14, X8]

  (198) 0x41e130 FSUB	D30, D1, S5

  (198) 0x41e134 FADD	D6, D30, D4

  (198) 0x41e138 STR	D6, [X22, X30,LSL #3]

  (198) 0x41e13c LDR	X0, [SP, #104]

  (198) 0x41e140 ORR	W5, WZR, W20

  (198) 0x41e144 LDR	W20, [SP, #136]

  (198) 0x41e148 CMP	W20, W0

  (198) 0x41e14c B.LE	41e18c

  (198) 0x41e150 LDR	W23, [SP, #148]

  (198) 0x41e154 LDR	W14, [SP, #144]

  (198) 0x41e158 LDR	W28, [SP, #140]

  (198) 0x41e15c SUB	W6, W23, W5

  (198) 0x41e160 CMP	W6, W14

  (198) 0x41e164 CSEL	W6, W6, W14, #9

  (198) 0x41e168 ADD	W20, W5, W6

  (198) 0x41e16c CMP	W5, W20

  (198) 0x41e170 B.CC	41ddec

  (200) 0x41e174 ADD	X15, X0, #1

  (200) 0x41e178 LDR	W20, [SP, #136]

  (200) 0x41e17c STR	X15, [SP, #104]

  (200) 0x41e180 LDR	X0, [SP, #104]

  (200) 0x41e184 CMP	W20, W0

  (200) 0x41e188 B.GT	41e150

(197) 0x41e18c LDP	X21, X22, [SP, #32]

(197) 0x41e190 LDP	X25, X26, [SP, #64]

(197) 0x41e194 LDP	X27, X28, [SP, #80]

(197) 0x41e198 LDP	X19, X20, [SP, #16]

(197) 0x41e19c LDP	X23, X24, [SP, #48]

(197) 0x41e1a0 LDP	X29, X30, [SP], #176

(197) 0x41e1a4 RET

  (196) 0x41e1a8 LDP	X21, X22, [SP, #32]

  (196) 0x41e1ac LDP	X19, X20, [SP, #16]

  (196) 0x41e1b0 LDP	X23, X24, [SP, #48]

  (196) 0x41e1b4 LDP	X29, X30, [SP], #176

  (196) 0x41e1b8 RET

  (196) 0x41e1bc ADD	W6, W6, #1

  (196) 0x41e1c0 MOVZ	W8, #0

  (196) 0x41e1c4 B	41dd94

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:136	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

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Value

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Value

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The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41dd20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e198 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e1a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W7, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W6, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41e1bc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41dd20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e198 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41e1a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W7, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W6, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41e1bc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.42	1.07
▼Loop 197 - advec_cell.cpp:136-140 - exec–	0.00	0.00
▼Loop 198 - advec_cell.cpp:138-140 - exec–	0.00	0.01
○Loop 199 - advec_cell.cpp:139-140 - exec	1.41	1.07
○Loop 200 - advec_cell.cpp:138-138 - exec	0.00	0.01
○Loop 196 - advec_cell.cpp:136-138 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code