OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-125 [...]	Coverage (incl. loops): 3.95% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 117 - 125

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41d90c STP	X29, X30, [SP, #800]!

0x41d910 ADD	X29, SP, #0

0x41d914 STP	X19, X20, [SP, #16]

0x41d918 ORR	X20, XZR, X0

0x41d91c STP	X21, X22, [SP, #32]

0x41d920 LDP	W22, W2, [X0, #56]

0x41d924 LDP	W1, W0, [X0, #48]

0x41d928 ADD	W3, W2, #2

0x41d92c ADD	W22, W22, #1

0x41d930 ADD	W4, W1, #1

0x41d934 STP	W3, W4, [SP, #168]

0x41d938 CMP	W22, W3

0x41d93c B.GE	41dce0

0x41d940 ADD	W19, W0, #2

0x41d944 STP	X23, X24, [SP, #48]

0x41d948 SUB	W23, W3, W22

0x41d94c CMP	W4, W19

0x41d950 B.GE	41dcdc

0x41d954 SUB	W5, W19, W4

0x41d958 MADD	W24, W23, W5, WZR

0x41d95c STR	W5, [SP, #216]

0x41d960 BL	403890

0x41d964 ORR	W21, WZR, W0

0x41d968 BL	4038c0

0x41d96c UDIV	W7, W24, W21

0x41d970 ORR	W6, WZR, W0

0x41d974 MSUB	W8, W7, W21, W24

0x41d978 CMP	W0, W8

0x41d97c B.CC	41dd0c

  (193) 0x41d980 MADD	W5, W7, W6, W8

  (193) 0x41d984 ADD	W9, W7, W5

  (193) 0x41d988 STR	W9, [SP, #220]

  (193) 0x41d98c CMP	W5, W9

  (193) 0x41d990 B.CS	41dcdc

  (193) 0x41d994 LDR	W12, [SP, #216]

  (193) 0x41d998 STP	X25, X26, [SP, #64]

  (193) 0x41d99c LDR	W16, [SP, #172]

  (193) 0x41d9a0 UDIV	W13, W5, W12

  (193) 0x41d9a4 STP	X27, X28, [SP, #80]

  (193) 0x41d9a8 LDP	X10, X11, [X20]

  (193) 0x41d9ac LDP	X25, X28, [X20, #32]

  (193) 0x41d9b0 LDP	X24, X17, [X20, #16]

  (193) 0x41d9b4 MSUB	W14, W13, W12, W5

  (193) 0x41d9b8 ADD	W15, W13, W22

  (193) 0x41d9bc ORR	X22, XZR, X10

  (193) 0x41d9c0 ORR	X23, XZR, X25

  (193) 0x41d9c4 SBFM	X27, X15, #0, #31

  (193) 0x41d9c8 ORR	X25, XZR, X11

  (193) 0x41d9cc ADD	W26, W14, W16

  (193) 0x41d9d0 SUB	W19, W19, W26

  (193) 0x41d9d4 HINT	#0

  (193) 0x41d9d8 HINT	#0

  (193) 0x41d9dc HINT	#0

    (194) 0x41d9e0 CMP	W7, W19

    (194) 0x41d9e4 CSEL	W4, W7, W19, #9

    (194) 0x41d9e8 ADD	W18, W5, W4

    (194) 0x41d9ec STR	W18, [SP, #116]

    (194) 0x41d9f0 CMP	W5, W18

    (194) 0x41d9f4 B.CS	41dcb8

    (194) 0x41d9f8 LDR	X30, [X22]

    (194) 0x41d9fc LDR	X2, [X23]

    (194) 0x41da00 LDR	X1, [X24]

    (194) 0x41da04 MADD	X21, X27, X30, XZR

    (194) 0x41da08 LDR	X3, [X25]

    (194) 0x41da0c MADD	X9, X27, X2, XZR

    (194) 0x41da10 LDR	X6, [X28]

    (194) 0x41da14 MADD	X5, X27, X1, XZR

    (194) 0x41da18 LDR	X8, [X23, #16]

    (194) 0x41da1c MADD	X11, X27, X3, XZR

    (194) 0x41da20 LDR	X0, [X17]

    (194) 0x41da24 MADD	X7, X27, X6, XZR

    (194) 0x41da28 LDR	X12, [X17, #16]

    (194) 0x41da2c LDR	X20, [X22, #16]

    (194) 0x41da30 MADD	X30, X27, X0, XZR

    (194) 0x41da34 LDR	X14, [X24, #16]

    (194) 0x41da38 LDR	X19, [X25, #16]

    (194) 0x41da3c LDR	X13, [X28, #16]

    (194) 0x41da40 STP	X8, X7, [SP, #120]

    (194) 0x41da44 STP	X11, X5, [SP, #136]

    (194) 0x41da48 STP	X9, X21, [SP, #152]

    (194) 0x41da4c CMP	W4, #1

    (194) 0x41da50 B.EQ	41dc1c

    (194) 0x41da54 SBFM	X2, X26, #0, #31

    (194) 0x41da58 UBFM	W18, W4, #1, #31

    (194) 0x41da5c ADD	X10, X5, X2

    (194) 0x41da60 ADD	X16, X7, X2

    (194) 0x41da64 UBFM	X1, X10, #61, #60

    (194) 0x41da68 ADD	X5, X14, X10,LSL #3

    (194) 0x41da6c UBFM	X10, X16, #61, #60

    (194) 0x41da70 ADD	X6, X13, X16,LSL #3

    (194) 0x41da74 ADD	X16, X21, X2

    (194) 0x41da78 ADD	X21, X9, X2

    (194) 0x41da7c ADD	X9, X1, #8

    (194) 0x41da80 ADD	X3, X30, X2

    (194) 0x41da84 STP	X1, X10, [SP, #176]

    (194) 0x41da88 ADD	X8, X8, X21,LSL #3

    (194) 0x41da8c UBFM	X15, X3, #61, #60

    (194) 0x41da90 ADD	X7, X12, X3,LSL #3

    (194) 0x41da94 ADD	X3, X11, X2

    (194) 0x41da98 ADD	X1, X15, #8

    (194) 0x41da9c ADD	X2, X10, #8

    (194) 0x41daa0 STR	X9, [SP, #104]

    (194) 0x41daa4 ADD	X11, X12, X1

    (194) 0x41daa8 ADD	X10, X13, X2

    (194) 0x41daac LDR	X9, [SP, #104]

    (194) 0x41dab0 MOVZ	X0, #0

    (194) 0x41dab4 UBFM	X21, X21, #61, #60

    (194) 0x41dab8 STP	X15, X2, [SP, #192]

    (194) 0x41dabc ADD	X2, X19, X3,LSL #3

    (194) 0x41dac0 UBFM	X15, X18, #60, #59

    (194) 0x41dac4 UBFM	X3, X3, #61, #60

    (194) 0x41dac8 STR	X1, [SP, #208]

    (194) 0x41dacc ADD	X1, X20, X16,LSL #3

    (194) 0x41dad0 UBFM	X16, X16, #61, #60

    (194) 0x41dad4 ADD	X9, X14, X9

    (194) 0x41dad8 TBZ	W18, #0, 41db60

    (194) 0x41dadc LDR	X0, [SP, #120]

    (194) 0x41dae0 LDR	X18, [SP, #184]

    (194) 0x41dae4 LDR	Q30, [X20, X16]

    (194) 0x41dae8 LDR	Q31, [X0, X21]

    (194) 0x41daec MOVZ	X0, #16

    (194) 0x41daf0 LDR	X21, [SP, #200]

    (194) 0x41daf4 LDR	Q0, [X13, X18]

    (194) 0x41daf8 LDR	X18, [SP, #192]

    (194) 0x41dafc FMUL	V3.2D, V30.2D, V31.2D

    (194) 0x41db00 LDR	Q29, [X13, X21]

    (194) 0x41db04 LDR	X21, [SP, #104]

    (194) 0x41db08 LDR	Q27, [X12, X18]

    (194) 0x41db0c LDR	X18, [SP, #208]

    (194) 0x41db10 FSUB	V4.2D, V0.2D, V29.2D

    (194) 0x41db14 LDR	Q2, [X14, X21]

    (194) 0x41db18 LDR	X21, [SP, #176]

    (194) 0x41db1c FADD	V5.2D, V27.2D, V31.2D

    (194) 0x41db20 LDR	Q1, [X19, X3]

    (194) 0x41db24 LDR	Q26, [X12, X18]

    (194) 0x41db28 FSUB	V6.2D, V3.2D, V2.2D

    (194) 0x41db2c LDR	Q28, [X14, X21]

    (194) 0x41db30 FMLA	V4.2D, V3.2D, V1.2D

    (194) 0x41db34 FSUB	V7.2D, V5.2D, V26.2D

    (194) 0x41db38 FADD	V16.2D, V6.2D, V28.2D

    (194) 0x41db3c FDIV	V17.2D, V16.2D, V7.2D

    (194) 0x41db40 FDIV	V18.2D, V4.2D, V16.2D

    (194) 0x41db44 STR	Q17, [X20, X16]

    (194) 0x41db48 STR	Q18, [X19, X3]

    (194) 0x41db4c CMP	X15, X0

    (194) 0x41db50 B.EQ	41dc10

    (194) 0x41db54 HINT	#0

    (194) 0x41db58 HINT	#0

    (194) 0x41db5c HINT	#0

      (195) 0x41db60 LDR	Q19, [X8, X0]

      (195) 0x41db64 ADD	X16, X0, #16

      (195) 0x41db68 LDR	Q20, [X1, X0]

      (195) 0x41db6c LDR	Q21, [X6, X0]

      (195) 0x41db70 LDR	Q22, [X10, X0]

      (195) 0x41db74 LDR	Q23, [X7, X0]

      (195) 0x41db78 FMUL	V24.2D, V20.2D, V19.2D

      (195) 0x41db7c LDR	Q25, [X9, X0]

      (195) 0x41db80 LDR	Q30, [X2, X0]

      (195) 0x41db84 FSUB	V1.2D, V21.2D, V22.2D

      (195) 0x41db88 LDR	Q31, [X11, X0]

      (195) 0x41db8c FADD	V0.2D, V23.2D, V19.2D

      (195) 0x41db90 LDR	Q3, [X5, X0]

      (195) 0x41db94 FSUB	V29.2D, V24.2D, V25.2D

      (195) 0x41db98 FMLA	V1.2D, V24.2D, V30.2D

      (195) 0x41db9c FSUB	V4.2D, V0.2D, V31.2D

      (195) 0x41dba0 FADD	V27.2D, V29.2D, V3.2D

      (195) 0x41dba4 FDIV	V5.2D, V27.2D, V4.2D

      (195) 0x41dba8 FDIV	V2.2D, V1.2D, V27.2D

      (195) 0x41dbac STR	Q5, [X1, X0]

      (195) 0x41dbb0 STR	Q2, [X2, X0]

      (195) 0x41dbb4 ADD	X0, X0, #32

      (195) 0x41dbb8 LDR	Q6, [X8, X16]

      (195) 0x41dbbc LDR	Q26, [X1, X16]

      (195) 0x41dbc0 LDR	Q7, [X6, X16]

      (195) 0x41dbc4 LDR	Q28, [X10, X16]

      (195) 0x41dbc8 LDR	Q16, [X7, X16]

      (195) 0x41dbcc FMUL	V17.2D, V26.2D, V6.2D

      (195) 0x41dbd0 LDR	Q18, [X9, X16]

      (195) 0x41dbd4 LDR	Q19, [X2, X16]

      (195) 0x41dbd8 FSUB	V23.2D, V7.2D, V28.2D

      (195) 0x41dbdc LDR	Q20, [X11, X16]

      (195) 0x41dbe0 FADD	V21.2D, V16.2D, V6.2D

      (195) 0x41dbe4 LDR	Q22, [X5, X16]

      (195) 0x41dbe8 FSUB	V24.2D, V17.2D, V18.2D

      (195) 0x41dbec FMLA	V23.2D, V17.2D, V19.2D

      (195) 0x41dbf0 FSUB	V25.2D, V21.2D, V20.2D

      (195) 0x41dbf4 FADD	V30.2D, V24.2D, V22.2D

      (195) 0x41dbf8 FDIV	V1.2D, V30.2D, V25.2D

      (195) 0x41dbfc FDIV	V31.2D, V23.2D, V30.2D

      (195) 0x41dc00 STR	Q1, [X1, X16]

      (195) 0x41dc04 STR	Q31, [X2, X16]

      (195) 0x41dc08 CMP	X15, X0

      (195) 0x41dc0c B.NE	41db60

    (194) 0x41dc10 TBZ	W4, #0, 41dcb4

    (194) 0x41dc14 AND	W4, W4, #1951

    (194) 0x41dc18 ADD	W26, W26, W4

    (194) 0x41dc1c LDR	X1, [SP, #160]

    (194) 0x41dc20 ADD	W5, W26, #1

    (194) 0x41dc24 SBFM	X8, X26, #0, #31

    (194) 0x41dc28 SBFM	X11, X5, #0, #31

    (194) 0x41dc2c LDP	X10, X7, [SP, #120]

    (194) 0x41dc30 ADD	X6, X30, X8

    (194) 0x41dc34 ADD	X30, X30, X11

    (194) 0x41dc38 LDR	X3, [SP, #152]

    (194) 0x41dc3c ADD	X15, X1, X8

    (194) 0x41dc40 UBFM	X9, X15, #61, #60

    (194) 0x41dc44 ADD	X2, X7, X11

    (194) 0x41dc48 LDR	D0, [X12, X6,LSL #3]

    (194) 0x41dc4c LDR	D4, [X12, X30,LSL #3]

    (194) 0x41dc50 LDP	X12, X18, [SP, #136]

    (194) 0x41dc54 ADD	X0, X3, X8

    (194) 0x41dc58 LDR	D3, [X20, X9]

    (194) 0x41dc5c ADD	X21, X12, X8

    (194) 0x41dc60 ADD	X4, X18, X8

    (194) 0x41dc64 LDR	D29, [X10, X0,LSL #3]

    (194) 0x41dc68 UBFM	X16, X21, #61, #60

    (194) 0x41dc6c ADD	X26, X18, X11

    (194) 0x41dc70 ADD	X8, X7, X8

    (194) 0x41dc74 LDR	D27, [X13, X2,LSL #3]

    (194) 0x41dc78 LDR	D26, [X19, X16]

    (194) 0x41dc7c FMUL	D5, D29, D3

    (194) 0x41dc80 LDR	D7, [X14, X4,LSL #3]

    (194) 0x41dc84 FADD	D2, D29, D0

    (194) 0x41dc88 LDR	D28, [X14, X26,LSL #3]

    (194) 0x41dc8c LDR	D18, [X13, X8,LSL #3]

    (194) 0x41dc90 FNMSUB	D16, D26, D5, D27

    (194) 0x41dc94 FADD	D17, D5, D7

    (194) 0x41dc98 FSUB	D6, D2, S4

    (194) 0x41dc9c FSUB	D19, D17, S28

    (194) 0x41dca0 FADD	D23, D16, D18

    (194) 0x41dca4 FDIV	D20, D19, D6

    (194) 0x41dca8 FDIV	D21, D23, D19

    (194) 0x41dcac STR	D20, [X20, X9]

    (194) 0x41dcb0 STR	D21, [X19, X16]

    (194) 0x41dcb4 LDR	W5, [SP, #116]

    (194) 0x41dcb8 ADD	X27, X27, #1

    (194) 0x41dcbc LDR	W20, [SP, #168]

    (194) 0x41dcc0 CMP	W20, W27

    (194) 0x41dcc4 B.LE	41dcf0

    (194) 0x41dcc8 LDR	W14, [SP, #220]

    (194) 0x41dccc LDR	W26, [SP, #172]

    (194) 0x41dcd0 LDR	W19, [SP, #216]

    (194) 0x41dcd4 SUB	W7, W14, W5

    (194) 0x41dcd8 B	41d9e0

(192) 0x41dcdc LDP	X23, X24, [SP, #48]

(192) 0x41dce0 LDP	X19, X20, [SP, #16]

(192) 0x41dce4 LDP	X21, X22, [SP, #32]

(192) 0x41dce8 LDP	X29, X30, [SP], #224

(192) 0x41dcec RET

  (193) 0x41dcf0 LDP	X23, X24, [SP, #48]

  (193) 0x41dcf4 LDP	X25, X26, [SP, #64]

  (193) 0x41dcf8 LDP	X27, X28, [SP, #80]

  (193) 0x41dcfc LDP	X19, X20, [SP, #16]

  (193) 0x41dd00 LDP	X21, X22, [SP, #32]

  (193) 0x41dd04 LDP	X29, X30, [SP], #224

  (193) 0x41dd08 RET

  (193) 0x41dd0c ADD	W7, W7, #1

  (193) 0x41dd10 MOVZ	W8, #0

  (193) 0x41dd14 B	41d980

0x41dd18 HINT	#0

0x41dd1c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d90c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #800]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41dce0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W3, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41dcdc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 41dd0c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d90c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #800]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41dce0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W3, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41dcdc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 41dd0c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.95	2.99
▼Loop 192 - advec_cell.cpp:117-125 - exec–	0.00	0.00
▼Loop 193 - advec_cell.cpp:117-125 - exec–	0.00	0.00
▼Loop 194 - advec_cell.cpp:119-125 - exec–	0.00	0.01
○Loop 195 - advec_cell.cpp:120-125 - exec	3.94	2.97

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code