OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:54-58 [...]	Coverage (incl. loops): 1.06% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 54 - 58

--------------------------------------------------------------------------------

54: #pragma omp parallel for simd collapse(2)

55:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

56:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

57:           pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

58:           post_vol(i, j) = volume(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41d5e8 STP	X29, X30, [SP, #896]!

0x41d5ec ADD	X29, SP, #0

0x41d5f0 STP	X19, X20, [SP, #16]

0x41d5f4 ORR	X20, XZR, X0

0x41d5f8 STP	X21, X22, [SP, #32]

0x41d5fc STP	X25, X26, [SP, #64]

0x41d600 LDP	W26, W21, [X0, #40]

0x41d604 LDP	W0, W19, [X0, #32]

0x41d608 SUB	W26, W26, #1

0x41d60c ADD	W21, W21, #4

0x41d610 CMP	W26, W21

0x41d614 B.GE	41d8ec

0x41d618 STP	X23, X24, [SP, #48]

0x41d61c SUB	W23, W21, W26

0x41d620 STP	X27, X28, [SP, #80]

0x41d624 SUB	W28, W0, #1

0x41d628 ADD	W27, W19, #4

0x41d62c CMP	W28, W27

0x41d630 B.GE	41d8e4

0x41d634 SUB	W1, W27, W28

0x41d638 MADD	W24, W23, W1, WZR

0x41d63c STR	W1, [SP, #104]

0x41d640 BL	403890

0x41d644 ORR	W22, WZR, W0

0x41d648 BL	4038c0

0x41d64c UDIV	W4, W24, W22

0x41d650 ORR	W2, WZR, W0

0x41d654 MSUB	W3, W4, W22, W24

0x41d658 CMP	W0, W3

0x41d65c B.CC	41d900

(189) 0x41d660 MADD	W18, W4, W2, W3

(189) 0x41d664 ADD	W5, W4, W18

(189) 0x41d668 STR	W5, [SP, #108]

(189) 0x41d66c CMP	W18, W5

(189) 0x41d670 B.CS	41d8e4

(189) 0x41d674 LDR	W6, [SP, #104]

(189) 0x41d678 LDP	X24, X25, [X20]

(189) 0x41d67c LDP	X22, X23, [X20, #16]

(189) 0x41d680 UDIV	W7, W18, W6

(189) 0x41d684 MSUB	W10, W7, W6, W18

(189) 0x41d688 ADD	W8, W7, W26

(189) 0x41d68c SBFM	X5, X8, #0, #31

(189) 0x41d690 ADD	W10, W10, W28

(189) 0x41d694 SUB	W26, W27, W10

(189) 0x41d698 HINT	#0

(189) 0x41d69c HINT	#0

  (190) 0x41d6a0 CMP	W4, W26

  (190) 0x41d6a4 CSEL	W4, W4, W26, #9

  (190) 0x41d6a8 ADD	W19, W18, W4

  (190) 0x41d6ac CMP	W18, W19

  (190) 0x41d6b0 B.CS	41d8c4

  (190) 0x41d6b4 LDR	X13, [X22]

  (190) 0x41d6b8 LDR	X15, [X23]

  (190) 0x41d6bc LDR	X9, [X24]

  (190) 0x41d6c0 MADD	X13, X5, X13, XZR

  (190) 0x41d6c4 LDR	X12, [X25]

  (190) 0x41d6c8 MADD	X15, X5, X15, XZR

  (190) 0x41d6cc LDR	X26, [X22, #16]

  (190) 0x41d6d0 MADD	X9, X5, X9, XZR

  (190) 0x41d6d4 LDR	X20, [X23, #16]

  (190) 0x41d6d8 MADD	X12, X5, X12, XZR

  (190) 0x41d6dc LDR	X18, [X24, #16]

  (190) 0x41d6e0 LDR	X14, [X25, #16]

  (190) 0x41d6e4 CMP	W4, #1

  (190) 0x41d6e8 B.EQ	41d880

  (190) 0x41d6ec UBFM	W11, W4, #1, #31

  (190) 0x41d6f0 SBFM	X1, X10, #0, #31

  (190) 0x41d6f4 UBFM	X11, X11, #60, #59

  (190) 0x41d6f8 ADD	X16, X12, X1

  (190) 0x41d6fc SUB	X17, X11, #16

  (190) 0x41d700 ADD	X27, X16, #1

  (190) 0x41d704 UBFM	X2, X17, #4, #63

  (190) 0x41d708 ADD	X17, X13, X1

  (190) 0x41d70c ADD	X3, X14, X27,LSL #3

  (190) 0x41d710 ADD	X6, X2, #1

  (190) 0x41d714 UBFM	X30, X27, #61, #60

  (190) 0x41d718 ANDS	X8, X6, #4160

  (190) 0x41d71c ADD	X6, X26, X17,LSL #3

  (190) 0x41d720 UBFM	X17, X17, #61, #60

  (190) 0x41d724 ADD	X16, X9, X1

  (190) 0x41d728 SUB	X27, X30, #8

  (190) 0x41d72c ADD	X1, X15, X1

  (190) 0x41d730 STR	X17, [SP, #112]

  (190) 0x41d734 ADD	X2, X18, X16,LSL #3

  (190) 0x41d738 MOVZ	X0, #0

  (190) 0x41d73c UBFM	X17, X1, #61, #60

  (190) 0x41d740 ADD	X7, X14, X27

  (190) 0x41d744 ADD	X1, X20, X1,LSL #3

  (190) 0x41d748 UBFM	X16, X16, #61, #60

  (190) 0x41d74c B.EQ	41d7dc

  (190) 0x41d750 CMP	X8, #1

  (190) 0x41d754 B.EQ	41d7b0

  (190) 0x41d758 CMP	X8, #2

  (190) 0x41d75c B.EQ	41d78c

  (190) 0x41d760 LDR	Q30, [X14, X30]

  (190) 0x41d764 MOVZ	X0, #16

  (190) 0x41d768 LDR	Q0, [X18, X16]

  (190) 0x41d76c LDR	Q31, [X14, X27]

  (190) 0x41d770 LDR	X30, [SP, #112]

  (190) 0x41d774 FADD	V1.2D, V0.2D, V30.2D

  (190) 0x41d778 FSUB	V2.2D, V1.2D, V31.2D

  (190) 0x41d77c STR	Q2, [X26, X30]

  (190) 0x41d780 LDR	Q3, [X18, X16]

  (190) 0x41d784 STR	Q3, [X20, X17]

  (190) 0x41d788 STR	Q3, [SP, #112]

  (190) 0x41d78c LDR	Q4, [X2, X0]

  (190) 0x41d790 LDR	Q28, [X3, X0]

  (190) 0x41d794 LDR	Q29, [X7, X0]

  (190) 0x41d798 FADD	V5.2D, V4.2D, V28.2D

  (190) 0x41d79c FSUB	V6.2D, V5.2D, V29.2D

  (190) 0x41d7a0 STR	Q6, [X6, X0]

  (190) 0x41d7a4 LDR	Q7, [X2, X0]

  (190) 0x41d7a8 STR	Q7, [X1, X0]

  (190) 0x41d7ac ADD	X0, X0, #16

  (190) 0x41d7b0 LDR	Q16, [X2, X0]

  (190) 0x41d7b4 LDR	Q26, [X3, X0]

  (190) 0x41d7b8 LDR	Q27, [X7, X0]

  (190) 0x41d7bc FADD	V17.2D, V16.2D, V26.2D

  (190) 0x41d7c0 FSUB	V18.2D, V17.2D, V27.2D

  (190) 0x41d7c4 STR	Q18, [X6, X0]

  (190) 0x41d7c8 LDR	Q19, [X2, X0]

  (190) 0x41d7cc STR	Q19, [X1, X0]

  (190) 0x41d7d0 ADD	X0, X0, #16

  (190) 0x41d7d4 CMP	X11, X0

  (190) 0x41d7d8 B.EQ	41d874

    (191) 0x41d7dc LDR	Q20, [X2, X0]

    (191) 0x41d7e0 ADD	X27, X0, #16

    (191) 0x41d7e4 ADD	X16, X0, #32

    (191) 0x41d7e8 ADD	X8, X0, #48

    (191) 0x41d7ec LDR	Q21, [X3, X0]

    (191) 0x41d7f0 LDR	Q22, [X7, X0]

    (191) 0x41d7f4 FADD	V23.2D, V20.2D, V21.2D

    (191) 0x41d7f8 FSUB	V24.2D, V23.2D, V22.2D

    (191) 0x41d7fc STR	Q24, [X6, X0]

    (191) 0x41d800 LDR	Q25, [X2, X0]

    (191) 0x41d804 STR	Q25, [X1, X0]

    (191) 0x41d808 ADD	X0, X0, #64

    (191) 0x41d80c LDR	Q0, [X2, X27]

    (191) 0x41d810 LDR	Q30, [X3, X27]

    (191) 0x41d814 LDR	Q31, [X7, X27]

    (191) 0x41d818 FADD	V1.2D, V0.2D, V30.2D

    (191) 0x41d81c FSUB	V2.2D, V1.2D, V31.2D

    (191) 0x41d820 STR	Q2, [X6, X27]

    (191) 0x41d824 LDR	Q3, [X2, X27]

    (191) 0x41d828 STR	Q3, [X1, X27]

    (191) 0x41d82c LDR	Q4, [X2, X16]

    (191) 0x41d830 LDR	Q28, [X3, X16]

    (191) 0x41d834 LDR	Q29, [X7, X16]

    (191) 0x41d838 FADD	V5.2D, V4.2D, V28.2D

    (191) 0x41d83c FSUB	V6.2D, V5.2D, V29.2D

    (191) 0x41d840 STR	Q6, [X6, X16]

    (191) 0x41d844 LDR	Q7, [X2, X16]

    (191) 0x41d848 STR	Q7, [X1, X16]

    (191) 0x41d84c LDR	Q16, [X2, X8]

    (191) 0x41d850 LDR	Q26, [X3, X8]

    (191) 0x41d854 LDR	Q27, [X7, X8]

    (191) 0x41d858 FADD	V17.2D, V16.2D, V26.2D

    (191) 0x41d85c FSUB	V18.2D, V17.2D, V27.2D

    (191) 0x41d860 STR	Q18, [X6, X8]

    (191) 0x41d864 LDR	Q19, [X2, X8]

    (191) 0x41d868 STR	Q19, [X1, X8]

    (191) 0x41d86c CMP	X11, X0

    (191) 0x41d870 B.NE	41d7dc

  (190) 0x41d874 TBZ	W4, #0, 41d8c0

  (190) 0x41d878 AND	W4, W4, #1951

  (190) 0x41d87c ADD	W10, W10, W4

  (190) 0x41d880 SBFM	X11, X10, #0, #31

  (190) 0x41d884 ADD	W3, W10, #1

  (190) 0x41d888 ADD	X2, X12, W3,SXTW

  (190) 0x41d88c LDR	D20, [X14, X2,LSL #3]

  (190) 0x41d890 ADD	X12, X12, X11

  (190) 0x41d894 ADD	X9, X9, X11

  (190) 0x41d898 UBFM	X7, X9, #61, #60

  (190) 0x41d89c ADD	X13, X13, X11

  (190) 0x41d8a0 LDR	D21, [X14, X12,LSL #3]

  (190) 0x41d8a4 ADD	X15, X15, X11

  (190) 0x41d8a8 LDR	D22, [X18, X7]

  (190) 0x41d8ac FSUB	D23, D20, S21

  (190) 0x41d8b0 FADD	D24, D23, D22

  (190) 0x41d8b4 STR	D24, [X26, X13,LSL #3]

  (190) 0x41d8b8 LDR	D25, [X18, X7]

  (190) 0x41d8bc STR	D25, [X20, X15,LSL #3]

  (190) 0x41d8c0 ORR	W18, WZR, W19

  (190) 0x41d8c4 ADD	X5, X5, #1

  (190) 0x41d8c8 CMP	W21, W5

  (190) 0x41d8cc B.LE	41d8e4

  (190) 0x41d8d0 LDR	W19, [SP, #108]

  (190) 0x41d8d4 ORR	W10, WZR, W28

  (190) 0x41d8d8 LDR	W26, [SP, #104]

  (190) 0x41d8dc SUB	W4, W19, W18

  (190) 0x41d8e0 B	41d6a0

(189) 0x41d8e4 LDP	X23, X24, [SP, #48]

(189) 0x41d8e8 LDP	X27, X28, [SP, #80]

(189) 0x41d8ec LDP	X19, X20, [SP, #16]

(189) 0x41d8f0 LDP	X21, X22, [SP, #32]

(189) 0x41d8f4 LDP	X25, X26, [SP, #64]

(189) 0x41d8f8 LDP	X29, X30, [SP], #128

(189) 0x41d8fc RET

(189) 0x41d900 ADD	W4, W4, #1

(189) 0x41d904 MOVZ	W3, #0

(189) 0x41d908 B	41d660

Coverage (%)	Name	Source Location	Module
►99.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:54-58
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54-58
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 48% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d5e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W21, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W19, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W26, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W21, W21, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d8ec <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W21, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W28, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W27, W19, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W28, W27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d8e4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, W27, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W1, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W24, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W4, W22, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41d900 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:54-58
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54-58
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d5e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W21, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W19, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W26, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W21, W21, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d8ec <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W21, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W28, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W27, W19, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W28, W27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d8e4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, W27, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W1, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W24, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W4, W22, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41d900 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.06	0.80
▼Loop 189 - advec_cell.cpp:54-58 - exec–	0.00	0.00
▼Loop 190 - advec_cell.cpp:56-58 - exec–	0.00	0.01
○Loop 191 - advec_cell.cpp:57-58 - exec	1.06	0.80

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code