OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:44-48 [...]	Coverage (incl. loops): 1.45% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41d140 STP	X29, X30, [SP, #848]!

0x41d144 ADD	X29, SP, #0

0x41d148 STP	X19, X20, [SP, #16]

0x41d14c ORR	X19, XZR, X0

0x41d150 STP	X23, X24, [SP, #48]

0x41d154 LDP	W23, W1, [X0, #48]

0x41d158 LDP	W0, W2, [X0, #40]

0x41d15c ADD	W3, W1, #4

0x41d160 SUB	W23, W23, #1

0x41d164 SUB	W4, W0, #1

0x41d168 STP	W3, W4, [SP, #136]

0x41d16c CMP	W23, W3

0x41d170 B.GE	41d5b8

0x41d174 STP	X21, X22, [SP, #32]

0x41d178 ADD	W22, W2, #4

0x41d17c SUB	W21, W3, W23

0x41d180 CMP	W4, W22

0x41d184 B.GE	41d5c8

0x41d188 SUB	W5, W22, W4

0x41d18c MADD	W24, W21, W5, WZR

0x41d190 STR	W5, [SP, #144]

0x41d194 BL	403890

0x41d198 ORR	W20, WZR, W0

0x41d19c BL	4038c0

0x41d1a0 UDIV	W7, W24, W20

0x41d1a4 ORR	W6, WZR, W0

0x41d1a8 MSUB	W8, W7, W20, W24

0x41d1ac CMP	W0, W8

0x41d1b0 B.CC	41d5dc

  (184) 0x41d1b4 MADD	W18, W7, W6, W8

  (184) 0x41d1b8 ADD	W9, W7, W18

  (184) 0x41d1bc STR	W9, [SP, #148]

  (184) 0x41d1c0 CMP	W18, W9

  (184) 0x41d1c4 B.CS	41d5c8

(185) 0x41d1c8 LDP	W10, W11, [SP, #140]

(185) 0x41d1cc STP	X27, X28, [SP, #80]

(185) 0x41d1d0 STP	X25, X26, [SP, #64]

(185) 0x41d1d4 UDIV	W12, W18, W11

(185) 0x41d1d8 LDR	X28, [X19, #32]

(185) 0x41d1dc LDP	X24, X25, [X19]

(185) 0x41d1e0 LDP	X26, X4, [X19, #16]

(185) 0x41d1e4 MSUB	W13, W12, W11, W18

(185) 0x41d1e8 ADD	W14, W12, W23

(185) 0x41d1ec SBFM	X0, X14, #0, #31

(185) 0x41d1f0 ADD	W27, W13, W10

(185) 0x41d1f4 SUB	W13, W22, W27

(185) 0x41d1f8 CMP	W7, W13

(185) 0x41d1fc CSEL	W5, W7, W13, #9

(185) 0x41d200 ADD	W20, W18, W5

(185) 0x41d204 CMP	W18, W20

(185) 0x41d208 B.CS	41d594

  (186) 0x41d20c LDR	X17, [X4]

  (186) 0x41d210 ADD	X16, X0, #1

  (186) 0x41d214 LDR	X30, [X26]

  (186) 0x41d218 LDR	X18, [X25]

  (186) 0x41d21c MADD	X3, X0, X17, XZR

  (186) 0x41d220 LDR	X23, [X4, #16]

  (186) 0x41d224 MADD	X14, X0, X30, X30

  (186) 0x41d228 LDR	X21, [X24, #16]

  (186) 0x41d22c MADD	X6, X0, X18, XZR

  (186) 0x41d230 LDR	X13, [X25, #16]

  (186) 0x41d234 SUB	X8, X14, X30

  (186) 0x41d238 LDR	X15, [X26, #16]

  (186) 0x41d23c LDR	X22, [X28, #16]

  (186) 0x41d240 STP	X16, X3, [SP, #104]

  (186) 0x41d244 LDR	X19, [X24]

  (186) 0x41d248 MADD	X7, X0, X19, XZR

  (186) 0x41d24c STP	X8, X7, [SP, #120]

  (186) 0x41d250 LDR	X1, [X28]

  (186) 0x41d254 MADD	X30, X0, X1, XZR

  (186) 0x41d258 CMP	W5, #1

  (186) 0x41d25c B.EQ	41d4e8

  (186) 0x41d260 SBFM	X2, X27, #0, #31

  (186) 0x41d264 UBFM	W9, W5, #1, #31

  (186) 0x41d268 ADD	X10, X6, X2

  (186) 0x41d26c ADD	X19, X7, X2

  (186) 0x41d270 ADD	X16, X10, #1

  (186) 0x41d274 ADD	X7, X14, X2

  (186) 0x41d278 ADD	X10, X21, X19,LSL #3

  (186) 0x41d27c UBFM	X12, X9, #60, #59

  (186) 0x41d280 UBFM	X9, X16, #61, #60

  (186) 0x41d284 ADD	X1, X13, X16,LSL #3

  (186) 0x41d288 SUB	X11, X12, #16

  (186) 0x41d28c ADD	X16, X3, X2

  (186) 0x41d290 ADD	X3, X15, X7,LSL #3

  (186) 0x41d294 UBFM	X17, X11, #4, #63

  (186) 0x41d298 STR	X9, [SP, #152]

  (186) 0x41d29c SUB	X9, X9, #8

  (186) 0x41d2a0 ADD	X18, X17, #1

  (186) 0x41d2a4 ADD	X17, X8, X2

  (186) 0x41d2a8 ADD	X2, X30, X2

  (186) 0x41d2ac STR	X3, [SP, #96]

  (186) 0x41d2b0 ADD	X3, X13, X9

  (186) 0x41d2b4 ADD	X8, X15, X17,LSL #3

  (186) 0x41d2b8 STR	X9, [SP, #160]

  (186) 0x41d2bc UBFM	X9, X2, #61, #60

  (186) 0x41d2c0 ANDS	X11, X18, #4160

  (186) 0x41d2c4 ADD	X2, X22, X2,LSL #3

  (186) 0x41d2c8 UBFM	X18, X7, #61, #60

  (186) 0x41d2cc MOVZ	X0, #0

  (186) 0x41d2d0 ADD	X7, X23, X16,LSL #3

  (186) 0x41d2d4 STR	X9, [SP, #168]

  (186) 0x41d2d8 UBFM	X19, X19, #61, #60

  (186) 0x41d2dc UBFM	X17, X17, #61, #60

  (186) 0x41d2e0 UBFM	X16, X16, #61, #60

  (186) 0x41d2e4 B.EQ	41d3d0

  (186) 0x41d2e8 CMP	X11, #1

  (186) 0x41d2ec B.EQ	41d384

  (186) 0x41d2f0 CMP	X11, #2

  (186) 0x41d2f4 B.EQ	41d340

  (186) 0x41d2f8 LDR	Q3, [X21, X19]

  (186) 0x41d2fc MOVZ	X0, #16

  (186) 0x41d300 LDP	X19, X11, [SP, #152]

  (186) 0x41d304 LDR	Q1, [X15, X18]

  (186) 0x41d308 LDR	Q2, [X13, X19]

  (186) 0x41d30c LDR	Q30, [X15, X17]

  (186) 0x41d310 LDR	Q0, [X13, X11]

  (186) 0x41d314 FADD	V4.2D, V3.2D, V2.2D

  (186) 0x41d318 LDR	X18, [SP, #168]

  (186) 0x41d31c FADD	V5.2D, V0.2D, V30.2D

  (186) 0x41d320 FADD	V6.2D, V4.2D, V1.2D

  (186) 0x41d324 FSUB	V7.2D, V6.2D, V5.2D

  (186) 0x41d328 STR	Q7, [X23, X16]

  (186) 0x41d32c LDR	Q29, [X13, X11]

  (186) 0x41d330 LDR	Q31, [X13, X19]

  (186) 0x41d334 FSUB	V16.2D, V29.2D, V31.2D

  (186) 0x41d338 FADD	V17.2D, V16.2D, V7.2D

  (186) 0x41d33c STR	Q17, [X22, X18]

  (186) 0x41d340 LDR	Q18, [X10, X0]

  (186) 0x41d344 LDR	Q19, [X1, X0]

  (186) 0x41d348 LDR	X17, [SP, #96]

  (186) 0x41d34c LDR	Q20, [X3, X0]

  (186) 0x41d350 LDR	Q27, [X8, X0]

  (186) 0x41d354 FADD	V21.2D, V18.2D, V19.2D

  (186) 0x41d358 LDR	Q23, [X17, X0]

  (186) 0x41d35c FADD	V22.2D, V20.2D, V27.2D

  (186) 0x41d360 FADD	V24.2D, V21.2D, V23.2D

  (186) 0x41d364 FSUB	V25.2D, V24.2D, V22.2D

  (186) 0x41d368 STR	Q25, [X7, X0]

  (186) 0x41d36c LDR	Q26, [X3, X0]

  (186) 0x41d370 LDR	Q28, [X1, X0]

  (186) 0x41d374 FSUB	V3.2D, V26.2D, V28.2D

  (186) 0x41d378 FADD	V1.2D, V3.2D, V25.2D

  (186) 0x41d37c STR	Q1, [X2, X0]

  (186) 0x41d380 ADD	X0, X0, #16

  (186) 0x41d384 LDR	Q30, [X10, X0]

  (186) 0x41d388 LDR	Q2, [X1, X0]

  (186) 0x41d38c LDR	X16, [SP, #96]

  (186) 0x41d390 LDR	Q0, [X3, X0]

  (186) 0x41d394 LDR	Q4, [X8, X0]

  (186) 0x41d398 FADD	V5.2D, V30.2D, V2.2D

  (186) 0x41d39c LDR	Q7, [X16, X0]

  (186) 0x41d3a0 FADD	V6.2D, V0.2D, V4.2D

  (186) 0x41d3a4 FADD	V29.2D, V5.2D, V7.2D

  (186) 0x41d3a8 FSUB	V31.2D, V29.2D, V6.2D

  (186) 0x41d3ac STR	Q31, [X7, X0]

  (186) 0x41d3b0 LDR	Q16, [X3, X0]

  (186) 0x41d3b4 LDR	Q17, [X1, X0]

  (186) 0x41d3b8 FSUB	V18.2D, V16.2D, V17.2D

  (186) 0x41d3bc FADD	V19.2D, V18.2D, V31.2D

  (186) 0x41d3c0 STR	Q19, [X2, X0]

  (186) 0x41d3c4 ADD	X0, X0, #16

  (186) 0x41d3c8 CMP	X12, X0

  (186) 0x41d3cc B.EQ	41d4dc

  (186) 0x41d3d0 LDR	X9, [SP, #96]

    (187) 0x41d3d4 ADD	X19, X0, #16

    (187) 0x41d3d8 ADD	X18, X0, #32

    (187) 0x41d3dc LDR	Q20, [X10, X0]

    (187) 0x41d3e0 ADD	X11, X0, #48

    (187) 0x41d3e4 LDR	Q27, [X1, X0]

    (187) 0x41d3e8 LDR	Q21, [X9, X0]

    (187) 0x41d3ec LDR	Q22, [X3, X0]

    (187) 0x41d3f0 LDR	Q23, [X8, X0]

    (187) 0x41d3f4 FADD	V24.2D, V20.2D, V27.2D

    (187) 0x41d3f8 FADD	V26.2D, V22.2D, V23.2D

    (187) 0x41d3fc FADD	V25.2D, V24.2D, V21.2D

    (187) 0x41d400 FSUB	V28.2D, V25.2D, V26.2D

    (187) 0x41d404 STR	Q28, [X7, X0]

    (187) 0x41d408 LDR	Q3, [X3, X0]

    (187) 0x41d40c LDR	Q1, [X1, X0]

    (187) 0x41d410 FSUB	V30.2D, V3.2D, V1.2D

    (187) 0x41d414 FADD	V2.2D, V30.2D, V28.2D

    (187) 0x41d418 STR	Q2, [X2, X0]

    (187) 0x41d41c ADD	X0, X0, #64

    (187) 0x41d420 LDR	Q0, [X10, X19]

    (187) 0x41d424 LDR	Q4, [X1, X19]

    (187) 0x41d428 LDR	Q5, [X9, X19]

    (187) 0x41d42c LDR	Q6, [X3, X19]

    (187) 0x41d430 LDR	Q7, [X8, X19]

    (187) 0x41d434 FADD	V29.2D, V0.2D, V4.2D

    (187) 0x41d438 FADD	V31.2D, V6.2D, V7.2D

    (187) 0x41d43c FADD	V16.2D, V29.2D, V5.2D

    (187) 0x41d440 FSUB	V17.2D, V16.2D, V31.2D

    (187) 0x41d444 STR	Q17, [X7, X19]

    (187) 0x41d448 LDR	Q18, [X3, X19]

    (187) 0x41d44c LDR	Q19, [X1, X19]

    (187) 0x41d450 FSUB	V20.2D, V18.2D, V19.2D

    (187) 0x41d454 FADD	V27.2D, V20.2D, V17.2D

    (187) 0x41d458 STR	Q27, [X2, X19]

    (187) 0x41d45c LDR	Q21, [X10, X18]

    (187) 0x41d460 LDR	Q22, [X1, X18]

    (187) 0x41d464 LDR	Q23, [X9, X18]

    (187) 0x41d468 LDR	Q24, [X3, X18]

    (187) 0x41d46c LDR	Q25, [X8, X18]

    (187) 0x41d470 FADD	V26.2D, V21.2D, V22.2D

    (187) 0x41d474 FADD	V28.2D, V24.2D, V25.2D

    (187) 0x41d478 FADD	V3.2D, V26.2D, V23.2D

    (187) 0x41d47c FSUB	V1.2D, V3.2D, V28.2D

    (187) 0x41d480 STR	Q1, [X7, X18]

    (187) 0x41d484 LDR	Q30, [X3, X18]

    (187) 0x41d488 LDR	Q2, [X1, X18]

    (187) 0x41d48c FSUB	V0.2D, V30.2D, V2.2D

    (187) 0x41d490 FADD	V4.2D, V0.2D, V1.2D

    (187) 0x41d494 STR	Q4, [X2, X18]

    (187) 0x41d498 LDR	Q5, [X10, X11]

    (187) 0x41d49c LDR	Q6, [X1, X11]

    (187) 0x41d4a0 LDR	Q7, [X9, X11]

    (187) 0x41d4a4 LDR	Q29, [X3, X11]

    (187) 0x41d4a8 LDR	Q31, [X8, X11]

    (187) 0x41d4ac FADD	V16.2D, V5.2D, V6.2D

    (187) 0x41d4b0 FADD	V17.2D, V29.2D, V31.2D

    (187) 0x41d4b4 FADD	V18.2D, V16.2D, V7.2D

    (187) 0x41d4b8 FSUB	V19.2D, V18.2D, V17.2D

    (187) 0x41d4bc STR	Q19, [X7, X11]

    (187) 0x41d4c0 LDR	Q20, [X3, X11]

    (187) 0x41d4c4 LDR	Q27, [X1, X11]

    (187) 0x41d4c8 FSUB	V21.2D, V20.2D, V27.2D

    (187) 0x41d4cc FADD	V22.2D, V21.2D, V19.2D

    (187) 0x41d4d0 STR	Q22, [X2, X11]

    (187) 0x41d4d4 CMP	X12, X0

    (187) 0x41d4d8 B.NE	41d3d4

  (186) 0x41d4dc TBZ	W5, #0, 41d55c

  (186) 0x41d4e0 AND	W5, W5, #1951

  (186) 0x41d4e4 ADD	W27, W27, W5

  (186) 0x41d4e8 LDR	X3, [SP, #128]

  (186) 0x41d4ec SBFM	X12, X27, #0, #31

  (186) 0x41d4f0 ADD	W1, W27, #1

  (186) 0x41d4f4 ADD	X10, X6, W1,SXTW

  (186) 0x41d4f8 ADD	X14, X14, X12

  (186) 0x41d4fc ADD	X6, X6, X12

  (186) 0x41d500 UBFM	X8, X10, #61, #60

  (186) 0x41d504 UBFM	X7, X6, #61, #60

  (186) 0x41d508 LDR	D23, [X15, X14,LSL #3]

  (186) 0x41d50c ADD	X30, X30, X12

  (186) 0x41d510 ADD	X2, X3, X12

  (186) 0x41d514 LDR	D24, [X13, X8]

  (186) 0x41d518 LDR	D28, [X21, X2,LSL #3]

  (186) 0x41d51c LDR	X21, [SP, #120]

  (186) 0x41d520 LDR	D25, [X13, X7]

  (186) 0x41d524 FADD	D3, D23, D28

  (186) 0x41d528 ADD	X17, X21, X12

  (186) 0x41d52c LDR	D1, [X15, X17,LSL #3]

  (186) 0x41d530 FSUB	D26, D24, S25

  (186) 0x41d534 LDR	X15, [SP, #112]

  (186) 0x41d538 FSUB	D30, D3, S1

  (186) 0x41d53c ADD	X16, X15, X12

  (186) 0x41d540 FADD	D2, D30, D26

  (186) 0x41d544 STR	D2, [X23, X16,LSL #3]

  (186) 0x41d548 LDR	D0, [X13, X7]

  (186) 0x41d54c LDR	D4, [X13, X8]

  (186) 0x41d550 FSUB	D5, D0, S4

  (186) 0x41d554 FADD	D6, D5, D2

  (186) 0x41d558 STR	D6, [X22, X30,LSL #3]

  (186) 0x41d55c LDR	X0, [SP, #104]

  (186) 0x41d560 ORR	W18, WZR, W20

  (186) 0x41d564 LDR	W20, [SP, #136]

  (186) 0x41d568 CMP	W20, W0

  (186) 0x41d56c B.LE	41d5ac

  (186) 0x41d570 LDR	W23, [SP, #148]

  (186) 0x41d574 LDR	W13, [SP, #144]

  (186) 0x41d578 LDR	W27, [SP, #140]

  (186) 0x41d57c SUB	W7, W23, W18

  (186) 0x41d580 CMP	W7, W13

  (186) 0x41d584 CSEL	W5, W7, W13, #9

  (186) 0x41d588 ADD	W20, W18, W5

  (186) 0x41d58c CMP	W18, W20

  (186) 0x41d590 B.CC	41d20c

  (188) 0x41d594 ADD	X15, X0, #1

  (188) 0x41d598 LDR	W20, [SP, #136]

  (188) 0x41d59c STR	X15, [SP, #104]

  (188) 0x41d5a0 LDR	X0, [SP, #104]

  (188) 0x41d5a4 CMP	W20, W0

  (188) 0x41d5a8 B.GT	41d570

(185) 0x41d5ac LDP	X21, X22, [SP, #32]

(185) 0x41d5b0 LDP	X25, X26, [SP, #64]

(185) 0x41d5b4 LDP	X27, X28, [SP, #80]

(185) 0x41d5b8 LDP	X19, X20, [SP, #16]

(185) 0x41d5bc LDP	X23, X24, [SP, #48]

(185) 0x41d5c0 LDP	X29, X30, [SP], #176

(185) 0x41d5c4 RET

  (184) 0x41d5c8 LDP	X21, X22, [SP, #32]

  (184) 0x41d5cc LDP	X19, X20, [SP, #16]

  (184) 0x41d5d0 LDP	X23, X24, [SP, #48]

  (184) 0x41d5d4 LDP	X29, X30, [SP], #176

  (184) 0x41d5d8 RET

  (184) 0x41d5dc ADD	W7, W7, #1

  (184) 0x41d5e0 MOVZ	W8, #0

  (184) 0x41d5e4 B	41d1b4

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d5b8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d5c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41d5dc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d5b8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W3, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d5c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W21, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W20, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41d5dc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.45	1.10
▼Loop 185 - advec_cell.cpp:44-48 - exec–	0.00	0.00
▼Loop 186 - advec_cell.cpp:46-48 - exec–	0.00	0.01
○Loop 187 - advec_cell.cpp:47-48 - exec	1.45	1.09
○Loop 188 - advec_cell.cpp:46-46 - exec	0.00	0.01
○Loop 184 - advec_cell.cpp:44-46 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code