OV - exec - Function revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ...	Module: exec	Source: revert.cpp:34-38 [...]	Coverage (incl. loops): 2.23% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp: 34 - 38

--------------------------------------------------------------------------------

34: #pragma omp parallel for simd collapse(2)

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density1(i, j) = density0(i, j);

38:       energy1(i, j) = energy0(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42e500 STP	X29, X30, [SP, #912]!

0x42e504 ADD	X29, SP, #0

0x42e508 STP	X19, X20, [SP, #16]

0x42e50c ORR	X20, XZR, X0

0x42e510 STP	X25, X26, [SP, #64]

0x42e514 LDP	W26, W19, [X0, #40]

0x42e518 LDP	W0, W25, [X0, #32]

0x42e51c ADD	W26, W26, #1

0x42e520 ADD	W19, W19, #2

0x42e524 CMP	W26, W19

0x42e528 B.GE	42e818

0x42e52c ADD	W25, W25, #2

0x42e530 STP	X21, X22, [SP, #32]

0x42e534 SUB	W22, W19, W26

0x42e538 STP	X23, X24, [SP, #48]

0x42e53c ADD	W23, W0, #1

0x42e540 CMP	W23, W25

0x42e544 B.GE	42e810

0x42e548 SUB	W24, W25, W23

0x42e54c BL	403890

0x42e550 MADD	W22, W22, W24, WZR

0x42e554 ORR	W21, WZR, W0

0x42e558 BL	4038c0

0x42e55c ORR	W2, WZR, W0

0x42e560 UDIV	W1, W22, W21

0x42e564 MSUB	W3, W1, W21, W22

0x42e568 CMP	W0, W3

0x42e56c B.CC	42e844

  (423) 0x42e570 MADD	W15, W1, W2, W3

  (423) 0x42e574 ADD	W4, W1, W15

  (423) 0x42e578 STR	W4, [SP, #100]

  (423) 0x42e57c CMP	W15, W4

  (423) 0x42e580 B.CS	42e810

  (423) 0x42e584 UDIV	W5, W15, W24

  (423) 0x42e588 STP	X27, X28, [SP, #80]

  (423) 0x42e58c LDP	X21, X22, [X20]

  (423) 0x42e590 LDP	X30, X20, [X20, #16]

  (423) 0x42e594 MSUB	W6, W5, W24, W15

  (423) 0x42e598 ADD	W7, W5, W26

  (423) 0x42e59c SBFM	X7, X7, #0, #31

  (423) 0x42e5a0 ADD	W6, W6, W23

  (423) 0x42e5a4 SUB	W18, W25, W6

    (424) 0x42e5a8 CMP	W1, W18

    (424) 0x42e5ac CSEL	W5, W1, W18, #9

    (424) 0x42e5b0 ADD	W12, W15, W5

    (424) 0x42e5b4 CMP	W15, W12

    (424) 0x42e5b8 B.CS	42e7f0

    (424) 0x42e5bc LDR	X13, [X20]

    (424) 0x42e5c0 LDR	X11, [X21]

    (424) 0x42e5c4 LDR	X10, [X22]

    (424) 0x42e5c8 MADD	X13, X7, X13, XZR

    (424) 0x42e5cc LDR	X9, [X30]

    (424) 0x42e5d0 MADD	X11, X7, X11, XZR

    (424) 0x42e5d4 LDR	X15, [X20, #16]

    (424) 0x42e5d8 MADD	X10, X7, X10, XZR

    (424) 0x42e5dc LDR	X18, [X21, #16]

    (424) 0x42e5e0 MADD	X9, X7, X9, XZR

    (424) 0x42e5e4 LDR	X17, [X22, #16]

    (424) 0x42e5e8 LDR	X16, [X30, #16]

    (424) 0x42e5ec CMP	W5, #1

    (424) 0x42e5f0 B.EQ	42e7c8

    (424) 0x42e5f4 UBFM	W8, W5, #1, #31

    (424) 0x42e5f8 SBFM	X25, X6, #0, #31

    (424) 0x42e5fc UBFM	X8, X8, #60, #59

    (424) 0x42e600 ADD	X28, X11, X25

    (424) 0x42e604 SUB	X14, X8, #16

    (424) 0x42e608 ADD	X27, X10, X25

    (424) 0x42e60c ADD	X4, X18, X28,LSL #3

    (424) 0x42e610 UBFM	X2, X14, #4, #63

    (424) 0x42e614 ADD	X26, X9, X25

    (424) 0x42e618 ADD	X3, X17, X27,LSL #3

    (424) 0x42e61c ADD	X1, X2, #1

    (424) 0x42e620 ADD	X25, X13, X25

    (424) 0x42e624 ADD	X2, X16, X26,LSL #3

    (424) 0x42e628 ANDS	X14, X1, #4224

    (424) 0x42e62c MOVZ	X0, #0

    (424) 0x42e630 ADD	X1, X15, X25,LSL #3

    (424) 0x42e634 UBFM	X28, X28, #61, #60

    (424) 0x42e638 UBFM	X27, X27, #61, #60

    (424) 0x42e63c UBFM	X26, X26, #61, #60

    (424) 0x42e640 UBFM	X25, X25, #61, #60

    (424) 0x42e644 B.EQ	42e70c

    (424) 0x42e648 CMP	X14, #1

    (424) 0x42e64c B.EQ	42e6f0

    (424) 0x42e650 CMP	X14, #2

    (424) 0x42e654 B.EQ	42e6dc

    (424) 0x42e658 CMP	X14, #3

    (424) 0x42e65c B.EQ	42e6c8

    (424) 0x42e660 CMP	X14, #4

    (424) 0x42e664 B.EQ	42e6b4

    (424) 0x42e668 CMP	X14, #5

    (424) 0x42e66c B.EQ	42e6a0

    (424) 0x42e670 CMP	X14, #6

    (424) 0x42e674 B.EQ	42e68c

    (424) 0x42e678 LDR	Q31, [X18, X28]

    (424) 0x42e67c MOVZ	X0, #16

    (424) 0x42e680 STR	Q31, [X17, X27]

    (424) 0x42e684 LDR	Q0, [X16, X26]

    (424) 0x42e688 STR	Q0, [X15, X25]

    (424) 0x42e68c LDR	Q1, [X4, X0]

    (424) 0x42e690 STR	Q1, [X3, X0]

    (424) 0x42e694 LDR	Q2, [X2, X0]

    (424) 0x42e698 STR	Q2, [X1, X0]

    (424) 0x42e69c ADD	X0, X0, #16

    (424) 0x42e6a0 LDR	Q3, [X4, X0]

    (424) 0x42e6a4 STR	Q3, [X3, X0]

    (424) 0x42e6a8 LDR	Q4, [X2, X0]

    (424) 0x42e6ac STR	Q4, [X1, X0]

    (424) 0x42e6b0 ADD	X0, X0, #16

    (424) 0x42e6b4 LDR	Q5, [X4, X0]

    (424) 0x42e6b8 STR	Q5, [X3, X0]

    (424) 0x42e6bc LDR	Q6, [X2, X0]

    (424) 0x42e6c0 STR	Q6, [X1, X0]

    (424) 0x42e6c4 ADD	X0, X0, #16

    (424) 0x42e6c8 LDR	Q7, [X4, X0]

    (424) 0x42e6cc STR	Q7, [X3, X0]

    (424) 0x42e6d0 LDR	Q16, [X2, X0]

    (424) 0x42e6d4 STR	Q16, [X1, X0]

    (424) 0x42e6d8 ADD	X0, X0, #16

    (424) 0x42e6dc LDR	Q17, [X4, X0]

    (424) 0x42e6e0 STR	Q17, [X3, X0]

    (424) 0x42e6e4 LDR	Q18, [X2, X0]

    (424) 0x42e6e8 STR	Q18, [X1, X0]

    (424) 0x42e6ec ADD	X0, X0, #16

    (424) 0x42e6f0 LDR	Q19, [X4, X0]

    (424) 0x42e6f4 STR	Q19, [X3, X0]

    (424) 0x42e6f8 LDR	Q20, [X2, X0]

    (424) 0x42e6fc STR	Q20, [X1, X0]

    (424) 0x42e700 ADD	X0, X0, #16

    (424) 0x42e704 CMP	X8, X0

    (424) 0x42e708 B.EQ	42e7bc

    (424) 0x42e70c STP	W19, W23, [SP, #104]

      (425) 0x42e710 LDR	Q21, [X4, X0]

      (425) 0x42e714 ADD	X14, X0, #16

      (425) 0x42e718 ADD	X28, X0, #32

      (425) 0x42e71c ADD	X27, X0, #48

      (425) 0x42e720 ADD	X26, X0, #64

      (425) 0x42e724 ADD	X25, X0, #80

      (425) 0x42e728 ADD	X23, X0, #96

      (425) 0x42e72c ADD	X19, X0, #112

      (425) 0x42e730 STR	Q21, [X3, X0]

      (425) 0x42e734 LDR	Q22, [X2, X0]

      (425) 0x42e738 STR	Q22, [X1, X0]

      (425) 0x42e73c ADD	X0, X0, #128

      (425) 0x42e740 LDR	Q23, [X4, X14]

      (425) 0x42e744 STR	Q23, [X3, X14]

      (425) 0x42e748 LDR	Q24, [X2, X14]

      (425) 0x42e74c STR	Q24, [X1, X14]

      (425) 0x42e750 LDR	Q25, [X4, X28]

      (425) 0x42e754 STR	Q25, [X3, X28]

      (425) 0x42e758 LDR	Q26, [X2, X28]

      (425) 0x42e75c STR	Q26, [X1, X28]

      (425) 0x42e760 LDR	Q27, [X4, X27]

      (425) 0x42e764 STR	Q27, [X3, X27]

      (425) 0x42e768 LDR	Q28, [X2, X27]

      (425) 0x42e76c STR	Q28, [X1, X27]

      (425) 0x42e770 LDR	Q29, [X4, X26]

      (425) 0x42e774 STR	Q29, [X3, X26]

      (425) 0x42e778 LDR	Q30, [X2, X26]

      (425) 0x42e77c STR	Q30, [X1, X26]

      (425) 0x42e780 LDR	Q31, [X4, X25]

      (425) 0x42e784 STR	Q31, [X3, X25]

      (425) 0x42e788 LDR	Q0, [X2, X25]

      (425) 0x42e78c STR	Q0, [X1, X25]

      (425) 0x42e790 LDR	Q1, [X4, X23]

      (425) 0x42e794 STR	Q1, [X3, X23]

      (425) 0x42e798 LDR	Q2, [X2, X23]

      (425) 0x42e79c STR	Q2, [X1, X23]

      (425) 0x42e7a0 LDR	Q3, [X4, X19]

      (425) 0x42e7a4 STR	Q3, [X3, X19]

      (425) 0x42e7a8 LDR	Q4, [X2, X19]

      (425) 0x42e7ac STR	Q4, [X1, X19]

      (425) 0x42e7b0 CMP	X8, X0

      (425) 0x42e7b4 B.NE	42e710

    (424) 0x42e7b8 LDP	W19, W23, [SP, #104]

    (424) 0x42e7bc TBZ	W5, #0, 42e7ec

    (424) 0x42e7c0 AND	W5, W5, #1951

    (424) 0x42e7c4 ADD	W6, W6, W5

    (424) 0x42e7c8 SBFM	X8, X6, #0, #31

    (424) 0x42e7cc ADD	X11, X11, X8

    (424) 0x42e7d0 ADD	X10, X10, X8

    (424) 0x42e7d4 ADD	X9, X9, X8

    (424) 0x42e7d8 ADD	X13, X13, X8

    (424) 0x42e7dc LDR	D5, [X18, X11,LSL #3]

    (424) 0x42e7e0 STR	D5, [X17, X10,LSL #3]

    (424) 0x42e7e4 LDR	D6, [X16, X9,LSL #3]

    (424) 0x42e7e8 STR	D6, [X15, X13,LSL #3]

    (424) 0x42e7ec ORR	W15, WZR, W12

    (424) 0x42e7f0 ADD	X7, X7, #1

    (424) 0x42e7f4 CMP	W19, W7

    (424) 0x42e7f8 B.LE	42e828

    (424) 0x42e7fc LDR	W12, [SP, #100]

    (424) 0x42e800 ORR	W6, WZR, W23

    (424) 0x42e804 ORR	W18, WZR, W24

    (424) 0x42e808 SUB	W1, W12, W15

    (424) 0x42e80c B	42e5a8

(422) 0x42e810 LDP	X21, X22, [SP, #32]

(422) 0x42e814 LDP	X23, X24, [SP, #48]

(422) 0x42e818 LDP	X19, X20, [SP, #16]

(422) 0x42e81c LDP	X25, X26, [SP, #64]

(422) 0x42e820 LDP	X29, X30, [SP], #112

(422) 0x42e824 RET

  (423) 0x42e828 LDP	X21, X22, [SP, #32]

  (423) 0x42e82c LDP	X23, X24, [SP, #48]

  (423) 0x42e830 LDP	X27, X28, [SP, #80]

  (423) 0x42e834 LDP	X19, X20, [SP, #16]

  (423) 0x42e838 LDP	X25, X26, [SP, #64]

  (423) 0x42e83c LDP	X29, X30, [SP], #112

  (423) 0x42e840 RET

  (423) 0x42e844 ADD	W1, W1, #1

  (423) 0x42e848 MOVZ	W3, #0

  (423) 0x42e84c B	42e570

Coverage (%)	Name	Source Location	Module
►98.94+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	revert(global_variables&)	revert.cpp:48	exec
○	PdV(global_variables&, bool)	PdV.cpp:131	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:34-38
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W25, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W26, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42e818 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W25, W25, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W23, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42e810 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W25, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W22, W22, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UDIV W1, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42e844 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:34-38
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W25, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W26, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42e818 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W25, W25, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W23, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42e810 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W25, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W22, W22, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UDIV W1, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42e844 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼revert_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	2.23	1.69
▼Loop 422 - revert.cpp:34-38 - exec–	0.00	0.00
▼Loop 423 - revert.cpp:34-38 - exec–	0.00	0.00
▼Loop 424 - revert.cpp:36-38 - exec–	0.00	0.01
○Loop 425 - revert.cpp:37-38 - exec	2.23	1.68

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code