OV - exec - Function reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ...	Module: exec	Source: reset_field.cpp:34-38 [...]	Coverage (incl. loops): 2.19% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp: 34 - 38

--------------------------------------------------------------------------------

34: #pragma omp parallel for simd collapse(2)

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density0(i, j) = density1(i, j);

38:       energy0(i, j) = energy1(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42dfd0 STP	X29, X30, [SP, #912]!

0x42dfd4 ADD	X29, SP, #0

0x42dfd8 STP	X19, X20, [SP, #16]

0x42dfdc ORR	X20, XZR, X0

0x42dfe0 STP	X25, X26, [SP, #64]

0x42dfe4 LDP	W26, W19, [X0, #40]

0x42dfe8 LDP	W0, W25, [X0, #32]

0x42dfec ADD	W26, W26, #1

0x42dff0 ADD	W19, W19, #2

0x42dff4 CMP	W26, W19

0x42dff8 B.GE	42e2f0

0x42dffc ADD	W25, W25, #2

0x42e000 STP	X21, X22, [SP, #32]

0x42e004 SUB	W22, W19, W26

0x42e008 STP	X23, X24, [SP, #48]

0x42e00c ADD	W23, W0, #1

0x42e010 CMP	W23, W25

0x42e014 B.GE	42e2e8

0x42e018 SUB	W24, W25, W23

0x42e01c BL	403890

0x42e020 MADD	W22, W22, W24, WZR

0x42e024 ORR	W21, WZR, W0

0x42e028 BL	4038c0

0x42e02c ORR	W2, WZR, W0

0x42e030 UDIV	W1, W22, W21

0x42e034 MSUB	W3, W1, W21, W22

0x42e038 CMP	W0, W3

0x42e03c B.CC	42e31c

  (417) 0x42e040 MADD	W16, W1, W2, W3

  (417) 0x42e044 ADD	W4, W1, W16

  (417) 0x42e048 STR	W4, [SP, #100]

  (417) 0x42e04c CMP	W16, W4

  (417) 0x42e050 B.CS	42e2e8

  (417) 0x42e054 UDIV	W5, W16, W24

  (417) 0x42e058 STP	X27, X28, [SP, #80]

  (417) 0x42e05c LDP	X21, X22, [X20]

  (417) 0x42e060 LDP	X30, X20, [X20, #16]

  (417) 0x42e064 MSUB	W6, W5, W24, W16

  (417) 0x42e068 ADD	W7, W5, W26

  (417) 0x42e06c SBFM	X7, X7, #0, #31

  (417) 0x42e070 ADD	W6, W6, W23

  (417) 0x42e074 SUB	W17, W25, W6

  (417) 0x42e078 HINT	#0

  (417) 0x42e07c HINT	#0

    (418) 0x42e080 CMP	W1, W17

    (418) 0x42e084 CSEL	W5, W1, W17, #9

    (418) 0x42e088 ADD	W12, W16, W5

    (418) 0x42e08c CMP	W16, W12

    (418) 0x42e090 B.CS	42e2c8

    (418) 0x42e094 LDR	X9, [X20]

    (418) 0x42e098 LDR	X10, [X21]

    (418) 0x42e09c LDR	X11, [X22]

    (418) 0x42e0a0 MADD	X9, X7, X9, XZR

    (418) 0x42e0a4 LDR	X13, [X30]

    (418) 0x42e0a8 MADD	X10, X7, X10, XZR

    (418) 0x42e0ac LDR	X16, [X20, #16]

    (418) 0x42e0b0 MADD	X11, X7, X11, XZR

    (418) 0x42e0b4 LDR	X17, [X21, #16]

    (418) 0x42e0b8 MADD	X13, X7, X13, XZR

    (418) 0x42e0bc LDR	X18, [X22, #16]

    (418) 0x42e0c0 LDR	X15, [X30, #16]

    (418) 0x42e0c4 CMP	W5, #1

    (418) 0x42e0c8 B.EQ	42e2a0

    (418) 0x42e0cc UBFM	W8, W5, #1, #31

    (418) 0x42e0d0 SBFM	X25, X6, #0, #31

    (418) 0x42e0d4 UBFM	X8, X8, #60, #59

    (418) 0x42e0d8 ADD	X28, X11, X25

    (418) 0x42e0dc SUB	X14, X8, #16

    (418) 0x42e0e0 ADD	X27, X10, X25

    (418) 0x42e0e4 ADD	X4, X18, X28,LSL #3

    (418) 0x42e0e8 UBFM	X2, X14, #4, #63

    (418) 0x42e0ec ADD	X26, X9, X25

    (418) 0x42e0f0 ADD	X3, X17, X27,LSL #3

    (418) 0x42e0f4 ADD	X1, X2, #1

    (418) 0x42e0f8 ADD	X25, X13, X25

    (418) 0x42e0fc ADD	X2, X16, X26,LSL #3

    (418) 0x42e100 ANDS	X14, X1, #4224

    (418) 0x42e104 MOVZ	X0, #0

    (418) 0x42e108 ADD	X1, X15, X25,LSL #3

    (418) 0x42e10c UBFM	X28, X28, #61, #60

    (418) 0x42e110 UBFM	X27, X27, #61, #60

    (418) 0x42e114 UBFM	X26, X26, #61, #60

    (418) 0x42e118 UBFM	X25, X25, #61, #60

    (418) 0x42e11c B.EQ	42e1e4

    (418) 0x42e120 CMP	X14, #1

    (418) 0x42e124 B.EQ	42e1c8

    (418) 0x42e128 CMP	X14, #2

    (418) 0x42e12c B.EQ	42e1b4

    (418) 0x42e130 CMP	X14, #3

    (418) 0x42e134 B.EQ	42e1a0

    (418) 0x42e138 CMP	X14, #4

    (418) 0x42e13c B.EQ	42e18c

    (418) 0x42e140 CMP	X14, #5

    (418) 0x42e144 B.EQ	42e178

    (418) 0x42e148 CMP	X14, #6

    (418) 0x42e14c B.EQ	42e164

    (418) 0x42e150 LDR	Q31, [X18, X28]

    (418) 0x42e154 MOVZ	X0, #16

    (418) 0x42e158 STR	Q31, [X17, X27]

    (418) 0x42e15c LDR	Q0, [X16, X26]

    (418) 0x42e160 STR	Q0, [X15, X25]

    (418) 0x42e164 LDR	Q1, [X4, X0]

    (418) 0x42e168 STR	Q1, [X3, X0]

    (418) 0x42e16c LDR	Q2, [X2, X0]

    (418) 0x42e170 STR	Q2, [X1, X0]

    (418) 0x42e174 ADD	X0, X0, #16

    (418) 0x42e178 LDR	Q3, [X4, X0]

    (418) 0x42e17c STR	Q3, [X3, X0]

    (418) 0x42e180 LDR	Q4, [X2, X0]

    (418) 0x42e184 STR	Q4, [X1, X0]

    (418) 0x42e188 ADD	X0, X0, #16

    (418) 0x42e18c LDR	Q5, [X4, X0]

    (418) 0x42e190 STR	Q5, [X3, X0]

    (418) 0x42e194 LDR	Q6, [X2, X0]

    (418) 0x42e198 STR	Q6, [X1, X0]

    (418) 0x42e19c ADD	X0, X0, #16

    (418) 0x42e1a0 LDR	Q7, [X4, X0]

    (418) 0x42e1a4 STR	Q7, [X3, X0]

    (418) 0x42e1a8 LDR	Q16, [X2, X0]

    (418) 0x42e1ac STR	Q16, [X1, X0]

    (418) 0x42e1b0 ADD	X0, X0, #16

    (418) 0x42e1b4 LDR	Q17, [X4, X0]

    (418) 0x42e1b8 STR	Q17, [X3, X0]

    (418) 0x42e1bc LDR	Q18, [X2, X0]

    (418) 0x42e1c0 STR	Q18, [X1, X0]

    (418) 0x42e1c4 ADD	X0, X0, #16

    (418) 0x42e1c8 LDR	Q19, [X4, X0]

    (418) 0x42e1cc STR	Q19, [X3, X0]

    (418) 0x42e1d0 LDR	Q20, [X2, X0]

    (418) 0x42e1d4 STR	Q20, [X1, X0]

    (418) 0x42e1d8 ADD	X0, X0, #16

    (418) 0x42e1dc CMP	X8, X0

    (418) 0x42e1e0 B.EQ	42e294

    (418) 0x42e1e4 STP	W19, W23, [SP, #104]

      (419) 0x42e1e8 LDR	Q21, [X4, X0]

      (419) 0x42e1ec ADD	X14, X0, #16

      (419) 0x42e1f0 ADD	X28, X0, #32

      (419) 0x42e1f4 ADD	X27, X0, #48

      (419) 0x42e1f8 ADD	X26, X0, #64

      (419) 0x42e1fc ADD	X25, X0, #80

      (419) 0x42e200 ADD	X23, X0, #96

      (419) 0x42e204 ADD	X19, X0, #112

      (419) 0x42e208 STR	Q21, [X3, X0]

      (419) 0x42e20c LDR	Q22, [X2, X0]

      (419) 0x42e210 STR	Q22, [X1, X0]

      (419) 0x42e214 ADD	X0, X0, #128

      (419) 0x42e218 LDR	Q23, [X4, X14]

      (419) 0x42e21c STR	Q23, [X3, X14]

      (419) 0x42e220 LDR	Q24, [X2, X14]

      (419) 0x42e224 STR	Q24, [X1, X14]

      (419) 0x42e228 LDR	Q25, [X4, X28]

      (419) 0x42e22c STR	Q25, [X3, X28]

      (419) 0x42e230 LDR	Q26, [X2, X28]

      (419) 0x42e234 STR	Q26, [X1, X28]

      (419) 0x42e238 LDR	Q27, [X4, X27]

      (419) 0x42e23c STR	Q27, [X3, X27]

      (419) 0x42e240 LDR	Q28, [X2, X27]

      (419) 0x42e244 STR	Q28, [X1, X27]

      (419) 0x42e248 LDR	Q29, [X4, X26]

      (419) 0x42e24c STR	Q29, [X3, X26]

      (419) 0x42e250 LDR	Q30, [X2, X26]

      (419) 0x42e254 STR	Q30, [X1, X26]

      (419) 0x42e258 LDR	Q31, [X4, X25]

      (419) 0x42e25c STR	Q31, [X3, X25]

      (419) 0x42e260 LDR	Q0, [X2, X25]

      (419) 0x42e264 STR	Q0, [X1, X25]

      (419) 0x42e268 LDR	Q1, [X4, X23]

      (419) 0x42e26c STR	Q1, [X3, X23]

      (419) 0x42e270 LDR	Q2, [X2, X23]

      (419) 0x42e274 STR	Q2, [X1, X23]

      (419) 0x42e278 LDR	Q3, [X4, X19]

      (419) 0x42e27c STR	Q3, [X3, X19]

      (419) 0x42e280 LDR	Q4, [X2, X19]

      (419) 0x42e284 STR	Q4, [X1, X19]

      (419) 0x42e288 CMP	X8, X0

      (419) 0x42e28c B.NE	42e1e8

    (418) 0x42e290 LDP	W19, W23, [SP, #104]

    (418) 0x42e294 TBZ	W5, #0, 42e2c4

    (418) 0x42e298 AND	W5, W5, #1951

    (418) 0x42e29c ADD	W6, W6, W5

    (418) 0x42e2a0 SBFM	X8, X6, #0, #31

    (418) 0x42e2a4 ADD	X11, X11, X8

    (418) 0x42e2a8 ADD	X10, X10, X8

    (418) 0x42e2ac ADD	X9, X9, X8

    (418) 0x42e2b0 ADD	X13, X13, X8

    (418) 0x42e2b4 LDR	D5, [X18, X11,LSL #3]

    (418) 0x42e2b8 STR	D5, [X17, X10,LSL #3]

    (418) 0x42e2bc LDR	D6, [X16, X9,LSL #3]

    (418) 0x42e2c0 STR	D6, [X15, X13,LSL #3]

    (418) 0x42e2c4 ORR	W16, WZR, W12

    (418) 0x42e2c8 ADD	X7, X7, #1

    (418) 0x42e2cc CMP	W19, W7

    (418) 0x42e2d0 B.LE	42e300

    (418) 0x42e2d4 LDR	W12, [SP, #100]

    (418) 0x42e2d8 ORR	W6, WZR, W23

    (418) 0x42e2dc ORR	W17, WZR, W24

    (418) 0x42e2e0 SUB	W1, W12, W16

    (418) 0x42e2e4 B	42e080

(416) 0x42e2e8 LDP	X21, X22, [SP, #32]

(416) 0x42e2ec LDP	X23, X24, [SP, #48]

(416) 0x42e2f0 LDP	X19, X20, [SP, #16]

(416) 0x42e2f4 LDP	X25, X26, [SP, #64]

(416) 0x42e2f8 LDP	X29, X30, [SP], #112

(416) 0x42e2fc RET

  (417) 0x42e300 LDP	X21, X22, [SP, #32]

  (417) 0x42e304 LDP	X23, X24, [SP, #48]

  (417) 0x42e308 LDP	X27, X28, [SP, #80]

  (417) 0x42e30c LDP	X19, X20, [SP, #16]

  (417) 0x42e310 LDP	X25, X26, [SP, #64]

  (417) 0x42e314 LDP	X29, X30, [SP], #112

  (417) 0x42e318 RET

  (417) 0x42e31c ADD	W1, W1, #1

  (417) 0x42e320 MOVZ	W3, #0

  (417) 0x42e324 B	42e040

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	reset_field(global_variables&)	reset_field.cpp:34	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	reset_field.cpp:34-38
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:34-38
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42dfd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W25, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W26, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42e2f0 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W25, W25, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W23, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42e2e8 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W25, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W22, W22, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UDIV W1, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42e31c <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	reset_field.cpp:34-38
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:34-38
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42dfd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W25, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W26, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42e2f0 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W25, W25, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W23, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42e2e8 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W25, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W22, W22, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UDIV W1, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42e31c <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [...–	2.19	1.66
▼Loop 416 - reset_field.cpp:34-38 - exec–	0.00	0.00
▼Loop 417 - reset_field.cpp:34-38 - exec–	0.00	0.00
▼Loop 418 - reset_field.cpp:36-38 - exec–	0.00	0.01
○Loop 419 - reset_field.cpp:37-38 - exec	2.18	1.65

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code