OV - exec - Function reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ...	Module: exec	Source: reset_field.cpp:44-48 [...]	Coverage (incl. loops): 2.21% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

46:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

47:       xvel0(i, j) = xvel1(i, j);

48:       yvel0(i, j) = yvel1(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42dc80 STP	X29, X30, [SP, #912]!

0x42dc84 ADD	X29, SP, #0

0x42dc88 STP	X19, X20, [SP, #16]

0x42dc8c ORR	X20, XZR, X0

0x42dc90 STP	X25, X26, [SP, #64]

0x42dc94 LDP	W26, W19, [X0, #40]

0x42dc98 LDP	W0, W25, [X0, #32]

0x42dc9c ADD	W26, W26, #1

0x42dca0 ADD	W19, W19, #3

0x42dca4 CMP	W26, W19

0x42dca8 B.GE	42df98

0x42dcac ADD	W25, W25, #3

0x42dcb0 STP	X21, X22, [SP, #32]

0x42dcb4 SUB	W22, W19, W26

0x42dcb8 STP	X23, X24, [SP, #48]

0x42dcbc ADD	W23, W0, #1

0x42dcc0 CMP	W23, W25

0x42dcc4 B.GE	42df90

0x42dcc8 SUB	W24, W25, W23

0x42dccc BL	403890

0x42dcd0 MADD	W22, W22, W24, WZR

0x42dcd4 ORR	W21, WZR, W0

0x42dcd8 BL	4038c0

0x42dcdc ORR	W2, WZR, W0

0x42dce0 UDIV	W1, W22, W21

0x42dce4 MSUB	W3, W1, W21, W22

0x42dce8 CMP	W0, W3

0x42dcec B.CC	42dfc4

  (413) 0x42dcf0 MADD	W16, W1, W2, W3

  (413) 0x42dcf4 ADD	W4, W1, W16

  (413) 0x42dcf8 STR	W4, [SP, #100]

  (413) 0x42dcfc CMP	W16, W4

  (413) 0x42dd00 B.CS	42df90

  (413) 0x42dd04 UDIV	W5, W16, W24

  (413) 0x42dd08 STP	X27, X28, [SP, #80]

  (413) 0x42dd0c LDP	X21, X22, [X20]

  (413) 0x42dd10 LDP	X30, X20, [X20, #16]

  (413) 0x42dd14 MSUB	W6, W5, W24, W16

  (413) 0x42dd18 ADD	W7, W5, W26

  (413) 0x42dd1c SBFM	X7, X7, #0, #31

  (413) 0x42dd20 ADD	W6, W6, W23

  (413) 0x42dd24 SUB	W17, W25, W6

    (414) 0x42dd28 CMP	W1, W17

    (414) 0x42dd2c CSEL	W5, W1, W17, #9

    (414) 0x42dd30 ADD	W12, W16, W5

    (414) 0x42dd34 CMP	W16, W12

    (414) 0x42dd38 B.CS	42df70

    (414) 0x42dd3c LDR	X9, [X20]

    (414) 0x42dd40 LDR	X10, [X21]

    (414) 0x42dd44 LDR	X11, [X22]

    (414) 0x42dd48 MADD	X9, X7, X9, XZR

    (414) 0x42dd4c LDR	X13, [X30]

    (414) 0x42dd50 MADD	X10, X7, X10, XZR

    (414) 0x42dd54 LDR	X16, [X20, #16]

    (414) 0x42dd58 MADD	X11, X7, X11, XZR

    (414) 0x42dd5c LDR	X17, [X21, #16]

    (414) 0x42dd60 MADD	X13, X7, X13, XZR

    (414) 0x42dd64 LDR	X18, [X22, #16]

    (414) 0x42dd68 LDR	X15, [X30, #16]

    (414) 0x42dd6c CMP	W5, #1

    (414) 0x42dd70 B.EQ	42df48

    (414) 0x42dd74 UBFM	W8, W5, #1, #31

    (414) 0x42dd78 SBFM	X25, X6, #0, #31

    (414) 0x42dd7c UBFM	X8, X8, #60, #59

    (414) 0x42dd80 ADD	X28, X11, X25

    (414) 0x42dd84 SUB	X14, X8, #16

    (414) 0x42dd88 ADD	X27, X10, X25

    (414) 0x42dd8c ADD	X4, X18, X28,LSL #3

    (414) 0x42dd90 UBFM	X2, X14, #4, #63

    (414) 0x42dd94 ADD	X26, X9, X25

    (414) 0x42dd98 ADD	X3, X17, X27,LSL #3

    (414) 0x42dd9c ADD	X1, X2, #1

    (414) 0x42dda0 ADD	X25, X13, X25

    (414) 0x42dda4 ADD	X2, X16, X26,LSL #3

    (414) 0x42dda8 ANDS	X14, X1, #4224

    (414) 0x42ddac MOVZ	X0, #0

    (414) 0x42ddb0 ADD	X1, X15, X25,LSL #3

    (414) 0x42ddb4 UBFM	X28, X28, #61, #60

    (414) 0x42ddb8 UBFM	X27, X27, #61, #60

    (414) 0x42ddbc UBFM	X26, X26, #61, #60

    (414) 0x42ddc0 UBFM	X25, X25, #61, #60

    (414) 0x42ddc4 B.EQ	42de8c

    (414) 0x42ddc8 CMP	X14, #1

    (414) 0x42ddcc B.EQ	42de70

    (414) 0x42ddd0 CMP	X14, #2

    (414) 0x42ddd4 B.EQ	42de5c

    (414) 0x42ddd8 CMP	X14, #3

    (414) 0x42dddc B.EQ	42de48

    (414) 0x42dde0 CMP	X14, #4

    (414) 0x42dde4 B.EQ	42de34

    (414) 0x42dde8 CMP	X14, #5

    (414) 0x42ddec B.EQ	42de20

    (414) 0x42ddf0 CMP	X14, #6

    (414) 0x42ddf4 B.EQ	42de0c

    (414) 0x42ddf8 LDR	Q31, [X18, X28]

    (414) 0x42ddfc MOVZ	X0, #16

    (414) 0x42de00 STR	Q31, [X17, X27]

    (414) 0x42de04 LDR	Q0, [X16, X26]

    (414) 0x42de08 STR	Q0, [X15, X25]

    (414) 0x42de0c LDR	Q1, [X4, X0]

    (414) 0x42de10 STR	Q1, [X3, X0]

    (414) 0x42de14 LDR	Q2, [X2, X0]

    (414) 0x42de18 STR	Q2, [X1, X0]

    (414) 0x42de1c ADD	X0, X0, #16

    (414) 0x42de20 LDR	Q3, [X4, X0]

    (414) 0x42de24 STR	Q3, [X3, X0]

    (414) 0x42de28 LDR	Q4, [X2, X0]

    (414) 0x42de2c STR	Q4, [X1, X0]

    (414) 0x42de30 ADD	X0, X0, #16

    (414) 0x42de34 LDR	Q5, [X4, X0]

    (414) 0x42de38 STR	Q5, [X3, X0]

    (414) 0x42de3c LDR	Q6, [X2, X0]

    (414) 0x42de40 STR	Q6, [X1, X0]

    (414) 0x42de44 ADD	X0, X0, #16

    (414) 0x42de48 LDR	Q7, [X4, X0]

    (414) 0x42de4c STR	Q7, [X3, X0]

    (414) 0x42de50 LDR	Q16, [X2, X0]

    (414) 0x42de54 STR	Q16, [X1, X0]

    (414) 0x42de58 ADD	X0, X0, #16

    (414) 0x42de5c LDR	Q17, [X4, X0]

    (414) 0x42de60 STR	Q17, [X3, X0]

    (414) 0x42de64 LDR	Q18, [X2, X0]

    (414) 0x42de68 STR	Q18, [X1, X0]

    (414) 0x42de6c ADD	X0, X0, #16

    (414) 0x42de70 LDR	Q19, [X4, X0]

    (414) 0x42de74 STR	Q19, [X3, X0]

    (414) 0x42de78 LDR	Q20, [X2, X0]

    (414) 0x42de7c STR	Q20, [X1, X0]

    (414) 0x42de80 ADD	X0, X0, #16

    (414) 0x42de84 CMP	X8, X0

    (414) 0x42de88 B.EQ	42df3c

    (414) 0x42de8c STP	W19, W23, [SP, #104]

      (415) 0x42de90 LDR	Q21, [X4, X0]

      (415) 0x42de94 ADD	X14, X0, #16

      (415) 0x42de98 ADD	X28, X0, #32

      (415) 0x42de9c ADD	X27, X0, #48

      (415) 0x42dea0 ADD	X26, X0, #64

      (415) 0x42dea4 ADD	X25, X0, #80

      (415) 0x42dea8 ADD	X23, X0, #96

      (415) 0x42deac ADD	X19, X0, #112

      (415) 0x42deb0 STR	Q21, [X3, X0]

      (415) 0x42deb4 LDR	Q22, [X2, X0]

      (415) 0x42deb8 STR	Q22, [X1, X0]

      (415) 0x42debc ADD	X0, X0, #128

      (415) 0x42dec0 LDR	Q23, [X4, X14]

      (415) 0x42dec4 STR	Q23, [X3, X14]

      (415) 0x42dec8 LDR	Q24, [X2, X14]

      (415) 0x42decc STR	Q24, [X1, X14]

      (415) 0x42ded0 LDR	Q25, [X4, X28]

      (415) 0x42ded4 STR	Q25, [X3, X28]

      (415) 0x42ded8 LDR	Q26, [X2, X28]

      (415) 0x42dedc STR	Q26, [X1, X28]

      (415) 0x42dee0 LDR	Q27, [X4, X27]

      (415) 0x42dee4 STR	Q27, [X3, X27]

      (415) 0x42dee8 LDR	Q28, [X2, X27]

      (415) 0x42deec STR	Q28, [X1, X27]

      (415) 0x42def0 LDR	Q29, [X4, X26]

      (415) 0x42def4 STR	Q29, [X3, X26]

      (415) 0x42def8 LDR	Q30, [X2, X26]

      (415) 0x42defc STR	Q30, [X1, X26]

      (415) 0x42df00 LDR	Q31, [X4, X25]

      (415) 0x42df04 STR	Q31, [X3, X25]

      (415) 0x42df08 LDR	Q0, [X2, X25]

      (415) 0x42df0c STR	Q0, [X1, X25]

      (415) 0x42df10 LDR	Q1, [X4, X23]

      (415) 0x42df14 STR	Q1, [X3, X23]

      (415) 0x42df18 LDR	Q2, [X2, X23]

      (415) 0x42df1c STR	Q2, [X1, X23]

      (415) 0x42df20 LDR	Q3, [X4, X19]

      (415) 0x42df24 STR	Q3, [X3, X19]

      (415) 0x42df28 LDR	Q4, [X2, X19]

      (415) 0x42df2c STR	Q4, [X1, X19]

      (415) 0x42df30 CMP	X8, X0

      (415) 0x42df34 B.NE	42de90

    (414) 0x42df38 LDP	W19, W23, [SP, #104]

    (414) 0x42df3c TBZ	W5, #0, 42df6c

    (414) 0x42df40 AND	W5, W5, #1951

    (414) 0x42df44 ADD	W6, W6, W5

    (414) 0x42df48 SBFM	X8, X6, #0, #31

    (414) 0x42df4c ADD	X11, X11, X8

    (414) 0x42df50 ADD	X10, X10, X8

    (414) 0x42df54 ADD	X9, X9, X8

    (414) 0x42df58 ADD	X13, X13, X8

    (414) 0x42df5c LDR	D5, [X18, X11,LSL #3]

    (414) 0x42df60 STR	D5, [X17, X10,LSL #3]

    (414) 0x42df64 LDR	D6, [X16, X9,LSL #3]

    (414) 0x42df68 STR	D6, [X15, X13,LSL #3]

    (414) 0x42df6c ORR	W16, WZR, W12

    (414) 0x42df70 ADD	X7, X7, #1

    (414) 0x42df74 CMP	W19, W7

    (414) 0x42df78 B.LE	42dfa8

    (414) 0x42df7c LDR	W12, [SP, #100]

    (414) 0x42df80 ORR	W6, WZR, W23

    (414) 0x42df84 ORR	W17, WZR, W24

    (414) 0x42df88 SUB	W1, W12, W16

    (414) 0x42df8c B	42dd28

(412) 0x42df90 LDP	X21, X22, [SP, #32]

(412) 0x42df94 LDP	X23, X24, [SP, #48]

(412) 0x42df98 LDP	X19, X20, [SP, #16]

(412) 0x42df9c LDP	X25, X26, [SP, #64]

(412) 0x42dfa0 LDP	X29, X30, [SP], #112

(412) 0x42dfa4 RET

  (413) 0x42dfa8 LDP	X21, X22, [SP, #32]

  (413) 0x42dfac LDP	X23, X24, [SP, #48]

  (413) 0x42dfb0 LDP	X27, X28, [SP, #80]

  (413) 0x42dfb4 LDP	X19, X20, [SP, #16]

  (413) 0x42dfb8 LDP	X25, X26, [SP, #64]

  (413) 0x42dfbc LDP	X29, X30, [SP], #112

  (413) 0x42dfc0 RET

  (413) 0x42dfc4 ADD	W1, W1, #1

  (413) 0x42dfc8 MOVZ	W3, #0

  (413) 0x42dfcc B	42dcf0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	reset_field(global_variables&)	reset_field.cpp:61	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	reset_field.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:44-48
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42dc80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W25, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W26, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42df98 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W25, W25, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W23, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42df90 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W25, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W22, W22, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UDIV W1, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42dfc4 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	reset_field.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:44-48
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42dc80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W25, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W26, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42df98 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W25, W25, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W23, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42df90 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W25, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W22, W22, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UDIV W1, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42dfc4 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [...–	2.21	1.68
▼Loop 412 - reset_field.cpp:44-48 - exec–	0.00	0.00
▼Loop 413 - reset_field.cpp:44-48 - exec–	0.00	0.00
▼Loop 414 - reset_field.cpp:46-48 - exec–	0.00	0.01
○Loop 415 - reset_field.cpp:47-48 - exec	2.21	1.67

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code