OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage (incl. loops): 6.36% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 48 - 63

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48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42cca0 STP	X29, X30, [SP, #656]!

0x42cca4 ADD	X29, SP, #0

0x42cca8 STP	X19, X20, [SP, #16]

0x42ccac ORR	X20, XZR, X0

0x42ccb0 STP	X21, X22, [SP, #32]

0x42ccb4 LDP	W22, W1, [X0, #104]

0x42ccb8 LDP	W0, W2, [X0, #96]

0x42ccbc ADD	W3, W1, #2

0x42ccc0 ADD	W22, W22, #1

0x42ccc4 ADD	W4, W0, #1

0x42ccc8 STR	W3, [SP, #264]

0x42cccc STR	W4, [SP, #268]

0x42ccd0 CMP	W22, W3

0x42ccd4 B.GE	42d1a8

0x42ccd8 ADD	W19, W2, #2

0x42ccdc STP	X23, X24, [SP, #48]

0x42cce0 SUB	W23, W3, W22

0x42cce4 CMP	W4, W19

0x42cce8 B.GE	42d1a4

0x42ccec SUB	W5, W19, W4

0x42ccf0 MADD	W24, W23, W5, WZR

0x42ccf4 STR	W5, [SP, #272]

0x42ccf8 BL	403890

0x42ccfc ORR	W21, WZR, W0

0x42cd00 BL	4038c0

0x42cd04 UDIV	W7, W24, W21

0x42cd08 ORR	W6, WZR, W0

0x42cd0c MSUB	W8, W7, W21, W24

0x42cd10 CMP	W0, W8

0x42cd14 B.CC	42d1d4

  (401) 0x42cd18 MADD	W23, W7, W6, W8

  (401) 0x42cd1c ADD	W9, W7, W23

  (401) 0x42cd20 STR	W9, [SP, #276]

  (401) 0x42cd24 CMP	W23, W9

  (401) 0x42cd28 B.CS	42d1a4

  (401) 0x42cd2c STP	X25, X26, [SP, #64]

  (401) 0x42cd30 FMOV	D30, #0.1250000

  (401) 0x42cd34 STP	X27, X28, [SP, #80]

  (401) 0x42cd38 LDP	X10, X11, [X20, #8]

  (401) 0x42cd3c LDR	W12, [SP, #272]

  (401) 0x42cd40 STR	X10, [SP, #280]

  (401) 0x42cd44 STR	X11, [SP, #296]

  (401) 0x42cd48 LDP	X16, X17, [X20, #24]

  (401) 0x42cd4c UDIV	W13, W23, W12

  (401) 0x42cd50 LDR	D31, [X20]

  (401) 0x42cd54 STR	X16, [SP, #312]

  (401) 0x42cd58 STR	X17, [SP, #328]

  (401) 0x42cd5c LDP	X18, X25, [X20, #40]

  (401) 0x42cd60 FMUL	D30, D31, D30

  (401) 0x42cd64 LDR	W26, [SP, #268]

  (401) 0x42cd68 STR	X25, [SP, #344]

  (401) 0x42cd6c MSUB	W14, W13, W12, W23

  (401) 0x42cd70 ADD	W15, W13, W22

  (401) 0x42cd74 STR	X18, [SP, #360]

  (401) 0x42cd78 SBFM	X27, X15, #0, #31

  (401) 0x42cd7c LDP	X28, X30, [X20, #56]

  (401) 0x42cd80 DUP	V29.2D, V30.D[0]

  (401) 0x42cd84 ADD	W26, W14, W26

  (401) 0x42cd88 SUB	W14, W19, W26

  (401) 0x42cd8c STR	X30, [SP, #320]

  (401) 0x42cd90 STR	X28, [SP, #352]

  (401) 0x42cd94 LDP	X22, X0, [X20, #72]

  (401) 0x42cd98 LDR	X20, [X20, #88]

  (401) 0x42cd9c STR	X0, [SP, #288]

  (401) 0x42cda0 STR	X22, [SP, #336]

  (401) 0x42cda4 STR	X20, [SP, #304]

    (402) 0x42cda8 CMP	W7, W14

    (402) 0x42cdac CSEL	W9, W7, W14, #9

    (402) 0x42cdb0 ADD	W2, W23, W9

    (402) 0x42cdb4 STR	W2, [SP, #212]

    (402) 0x42cdb8 CMP	W23, W2

    (402) 0x42cdbc B.CS	42d180

    (402) 0x42cdc0 LDP	X7, X11, [SP, #312]

    (402) 0x42cdc4 LDP	X23, X5, [SP, #280]

    (402) 0x42cdc8 LDP	X21, X6, [SP, #296]

    (402) 0x42cdcc LDP	X30, X22, [SP, #328]

    (402) 0x42cdd0 LDR	X12, [X7]

    (402) 0x42cdd4 LDR	X1, [X5]

    (402) 0x42cdd8 LDR	X3, [X21]

    (402) 0x42cddc MADD	X14, X27, X12, XZR

    (402) 0x42cde0 LDR	X4, [X6]

    (402) 0x42cde4 MADD	X24, X1, X27, XZR

    (402) 0x42cde8 LDR	X13, [X11]

    (402) 0x42cdec MADD	X10, X3, X27, XZR

    (402) 0x42cdf0 STR	X14, [SP, #200]

    (402) 0x42cdf4 LDP	X12, X14, [SP, #344]

    (402) 0x42cdf8 ADD	X16, X1, X24

    (402) 0x42cdfc MADD	X25, X4, X27, XZR

    (402) 0x42ce00 ADD	X17, X3, X10

    (402) 0x42ce04 MADD	X15, X27, X13, XZR

    (402) 0x42ce08 ADD	X19, X4, X25

    (402) 0x42ce0c LDR	X8, [X23]

    (402) 0x42ce10 LDR	X28, [X30]

    (402) 0x42ce14 STP	X19, X17, [SP, #224]

    (402) 0x42ce18 MADD	X18, X27, X8, XZR

    (402) 0x42ce1c LDR	X13, [SP, #360]

    (402) 0x42ce20 STP	X10, X16, [SP, #240]

    (402) 0x42ce24 MADD	X0, X27, X28, XZR

    (402) 0x42ce28 LDR	X20, [X22]

    (402) 0x42ce2c STR	X15, [SP, #184]

    (402) 0x42ce30 LDR	X2, [X12]

    (402) 0x42ce34 STR	X0, [SP, #168]

    (402) 0x42ce38 LDR	X1, [X14]

    (402) 0x42ce3c MADD	X3, X27, X20, XZR

    (402) 0x42ce40 STR	X18, [SP, #256]

    (402) 0x42ce44 LDR	X15, [X13]

    (402) 0x42ce48 MADD	X4, X27, X2, XZR

    (402) 0x42ce4c LDR	X20, [X22, #16]

    (402) 0x42ce50 STR	X3, [SP, #152]

    (402) 0x42ce54 MADD	X8, X27, X1, XZR

    (402) 0x42ce58 LDR	X28, [X23, #16]

    (402) 0x42ce5c STR	X4, [SP, #112]

    (402) 0x42ce60 MADD	X0, X27, X15, XZR

    (402) 0x42ce64 LDR	X3, [X30, #16]

    (402) 0x42ce68 STR	X20, [SP, #104]

    (402) 0x42ce6c LDR	X22, [X5, #16]

    (402) 0x42ce70 STR	X0, [SP, #216]

    (402) 0x42ce74 LDR	X5, [X7, #16]

    (402) 0x42ce78 STR	X3, [SP, #160]

    (402) 0x42ce7c LDR	X30, [X21, #16]

    (402) 0x42ce80 LDR	X23, [X6, #16]

    (402) 0x42ce84 STR	X5, [SP, #192]

    (402) 0x42ce88 LDR	X21, [X11, #16]

    (402) 0x42ce8c LDR	X6, [X12, #16]

    (402) 0x42ce90 LDR	X7, [X14, #16]

    (402) 0x42ce94 STR	X21, [SP, #176]

    (402) 0x42ce98 LDR	X11, [X13, #16]

    (402) 0x42ce9c STP	X6, X8, [SP, #120]

    (402) 0x42cea0 STP	X7, X11, [SP, #136]

    (402) 0x42cea4 CMP	W9, #1

    (402) 0x42cea8 B.EQ	42d044

    (402) 0x42ceac SBFM	X1, X26, #0, #31

    (402) 0x42ceb0 UBFM	W12, W9, #1, #31

    (402) 0x42ceb4 ADD	X2, X16, X1

    (402) 0x42ceb8 ADD	X18, X18, X1

    (402) 0x42cebc LDR	X11, [SP, #152]

    (402) 0x42cec0 ADD	X3, X28, X18,LSL #3

    (402) 0x42cec4 ADD	X16, X10, X1

    (402) 0x42cec8 ADD	X4, X19, X1

    (402) 0x42cecc ADD	X10, X22, X2,LSL #3

    (402) 0x42ced0 ADD	X13, X25, X1

    (402) 0x42ced4 ADD	X14, X24, X1

    (402) 0x42ced8 LDR	X2, [SP, #168]

    (402) 0x42cedc ORR	X8, XZR, X3

    (402) 0x42cee0 ADD	X21, X3, #8

    (402) 0x42cee4 ADD	X5, X23, X13,LSL #3

    (402) 0x42cee8 ORR	X6, XZR, X10

    (402) 0x42ceec ADD	X19, X10, #8

    (402) 0x42cef0 LDR	X10, [SP, #112]

    (402) 0x42cef4 ADD	X20, X22, X14,LSL #3

    (402) 0x42cef8 UBFM	X3, X12, #60, #59

    (402) 0x42cefc ADD	X18, X5, #8

    (402) 0x42cf00 ADD	X5, X23, X13,LSL #3

    (402) 0x42cf04 LDR	X12, [SP, #184]

    (402) 0x42cf08 ADD	X15, X17, X1

    (402) 0x42cf0c ADD	X17, X23, X4,LSL #3

    (402) 0x42cf10 ORR	X7, XZR, X20

    (402) 0x42cf14 ADD	X2, X2, X1

    (402) 0x42cf18 ADD	X4, X23, X4,LSL #3

    (402) 0x42cf1c ADD	X20, X20, #8

    (402) 0x42cf20 LDR	X14, [SP, #200]

    (402) 0x42cf24 ADD	X16, X30, X16,LSL #3

    (402) 0x42cf28 ADD	X17, X17, #8

    (402) 0x42cf2c ADD	X15, X30, X15,LSL #3

    (402) 0x42cf30 ADD	X13, X12, X1

    (402) 0x42cf34 ADD	X12, X11, X1

    (402) 0x42cf38 ADD	X11, X10, X1

    (402) 0x42cf3c LDR	X10, [SP, #128]

    (402) 0x42cf40 ADD	X14, X14, X1

    (402) 0x42cf44 ADD	X10, X10, X1

    (402) 0x42cf48 ADD	X1, X0, X1

    (402) 0x42cf4c LDR	X0, [SP, #192]

    (402) 0x42cf50 ADD	X14, X0, X14,LSL #3

    (402) 0x42cf54 LDR	X0, [SP, #176]

    (402) 0x42cf58 ADD	X13, X0, X13,LSL #3

    (402) 0x42cf5c LDR	X0, [SP, #160]

    (402) 0x42cf60 ADD	X2, X0, X2,LSL #3

    (402) 0x42cf64 LDR	X0, [SP, #104]

    (402) 0x42cf68 ADD	X12, X0, X12,LSL #3

    (402) 0x42cf6c LDR	X0, [SP, #120]

    (402) 0x42cf70 ADD	X11, X0, X11,LSL #3

    (402) 0x42cf74 LDR	X0, [SP, #136]

    (402) 0x42cf78 ADD	X10, X0, X10,LSL #3

    (402) 0x42cf7c LDR	X0, [SP, #144]

    (402) 0x42cf80 ADD	X1, X0, X1,LSL #3

    (402) 0x42cf84 MOVZ	X0, #0

      (403) 0x42cf88 LDR	Q17, [X5, X0]

      (403) 0x42cf8c LDR	Q16, [X18, X0]

      (403) 0x42cf90 LDR	Q24, [X16, X0]

      (403) 0x42cf94 LDR	Q4, [X4, X0]

      (403) 0x42cf98 LDR	Q3, [X17, X0]

      (403) 0x42cf9c FADD	V0.2D, V17.2D, V16.2D

      (403) 0x42cfa0 LDR	Q26, [X15, X0]

      (403) 0x42cfa4 FADD	V1.2D, V24.2D, V24.2D

      (403) 0x42cfa8 LDR	Q28, [X6, X0]

      (403) 0x42cfac LDR	Q27, [X7, X0]

      (403) 0x42cfb0 FADD	V2.2D, V4.2D, V3.2D

      (403) 0x42cfb4 LDR	Q25, [X8, X0]

      (403) 0x42cfb8 FADD	V18.2D, V26.2D, V26.2D

      (403) 0x42cfbc FMUL	V19.2D, V0.2D, V1.2D

      (403) 0x42cfc0 LDR	Q7, [X21, X0]

      (403) 0x42cfc4 LDR	Q6, [X20, X0]

      (403) 0x42cfc8 FADD	V20.2D, V28.2D, V27.2D

      (403) 0x42cfcc LDR	Q5, [X19, X0]

      (403) 0x42cfd0 FADD	V22.2D, V25.2D, V25.2D

      (403) 0x42cfd4 FMUL	V23.2D, V2.2D, V18.2D

      (403) 0x42cfd8 FADD	V31.2D, V7.2D, V7.2D

      (403) 0x42cfdc LDR	Q21, [X13, X0]

      (403) 0x42cfe0 LDR	Q17, [X12, X0]

      (403) 0x42cfe4 FADD	V16.2D, V6.2D, V5.2D

      (403) 0x42cfe8 LDR	Q24, [X2, X0]

      (403) 0x42cfec FMLA	V19.2D, V20.2D, V22.2D

      (403) 0x42cff0 LDR	Q4, [X14, X0]

      (403) 0x42cff4 FADD	V3.2D, V21.2D, V17.2D

      (403) 0x42cff8 LDR	Q26, [X11, X0]

      (403) 0x42cffc FMLA	V23.2D, V31.2D, V16.2D

      (403) 0x42d000 FDIV	V0.2D, V3.2D, V24.2D

      (403) 0x42d004 FDIV	V1.2D, V0.2D, V4.2D

      (403) 0x42d008 FSUB	V28.2D, V23.2D, V19.2D

      (403) 0x42d00c FMUL	V27.2D, V28.2D, V29.2D

      (403) 0x42d010 FMLS	V26.2D, V27.2D, V1.2D

      (403) 0x42d014 FADD	V2.2D, V27.2D, V4.2D

      (403) 0x42d018 STR	Q26, [X10, X0]

      (403) 0x42d01c FDIV	V25.2D, V4.2D, V2.2D

      (403) 0x42d020 LDR	Q18, [X2, X0]

      (403) 0x42d024 FMUL	V19.2D, V18.2D, V25.2D

      (403) 0x42d028 STR	Q19, [X1, X0]

      (403) 0x42d02c ADD	X0, X0, #16

      (403) 0x42d030 CMP	X0, X3

      (403) 0x42d034 B.NE	42cf88

    (402) 0x42d038 TBZ	W9, #0, 42d17c

    (402) 0x42d03c AND	W9, W9, #1951

    (402) 0x42d040 ADD	W26, W26, W9

    (402) 0x42d044 LDR	X6, [SP, #240]

    (402) 0x42d048 ADD	W8, W26, #1

    (402) 0x42d04c SBFM	X21, X26, #0, #31

    (402) 0x42d050 SBFM	X20, X8, #0, #31

    (402) 0x42d054 LDP	X18, X5, [SP, #224]

    (402) 0x42d058 ADD	X7, X24, X21

    (402) 0x42d05c ADD	X14, X25, X20

    (402) 0x42d060 ADD	X25, X25, X21

    (402) 0x42d064 ADD	X24, X24, X20

    (402) 0x42d068 LDP	X12, X11, [SP, #248]

    (402) 0x42d06c ADD	X19, X6, X21

    (402) 0x42d070 ADD	X17, X18, X20

    (402) 0x42d074 ADD	X3, X18, X21

    (402) 0x42d078 ADD	X15, X5, X21

    (402) 0x42d07c LDP	X18, X5, [SP, #112]

    (402) 0x42d080 ADD	X1, X12, X21

    (402) 0x42d084 ADD	X26, X12, X20

    (402) 0x42d088 ADD	X0, X11, X20

    (402) 0x42d08c ADD	X10, X11, X21

    (402) 0x42d090 LDR	D7, [X30, X19,LSL #3]

    (402) 0x42d094 LDR	D31, [X23, X14,LSL #3]

    (402) 0x42d098 LDR	D17, [X23, X25,LSL #3]

    (402) 0x42d09c LDR	X4, [SP, #152]

    (402) 0x42d0a0 FADD	D22, D7, D7

    (402) 0x42d0a4 LDR	X2, [SP, #184]

    (402) 0x42d0a8 LDR	D5, [X23, X17,LSL #3]

    (402) 0x42d0ac FADD	D16, D31, D17

    (402) 0x42d0b0 ADD	X17, X18, X21

    (402) 0x42d0b4 ADD	X13, X4, X21

    (402) 0x42d0b8 LDR	D23, [X23, X3,LSL #3]

    (402) 0x42d0bc ADD	X9, X2, X21

    (402) 0x42d0c0 LDR	D24, [X30, X15,LSL #3]

    (402) 0x42d0c4 LDR	X30, [SP, #104]

    (402) 0x42d0c8 FMUL	D0, D16, D22

    (402) 0x42d0cc LDR	X8, [SP, #176]

    (402) 0x42d0d0 FADD	D21, D5, D23

    (402) 0x42d0d4 LDR	D20, [X22, X7,LSL #3]

    (402) 0x42d0d8 FADD	D4, D24, D24

    (402) 0x42d0dc LDR	D6, [X22, X24,LSL #3]

    (402) 0x42d0e0 LDP	X24, X6, [SP, #192]

    (402) 0x42d0e4 FMUL	D3, D21, D4

    (402) 0x42d0e8 LDR	D1, [X22, X1,LSL #3]

    (402) 0x42d0ec ADD	X19, X6, X21

    (402) 0x42d0f0 LDR	D26, [X28, X10,LSL #3]

    (402) 0x42d0f4 LDR	D28, [X28, X0,LSL #3]

    (402) 0x42d0f8 LDR	D2, [X22, X26,LSL #3]

    (402) 0x42d0fc FADD	D25, D1, D20

    (402) 0x42d100 LDP	X28, X22, [SP, #160]

    (402) 0x42d104 FADD	D18, D26, D26

    (402) 0x42d108 FADD	D19, D28, D28

    (402) 0x42d10c LDR	D27, [X30, X13,LSL #3]

    (402) 0x42d110 ADD	X20, X22, X21

    (402) 0x42d114 FADD	D20, D2, D6

    (402) 0x42d118 LDR	D22, [X8, X9,LSL #3]

    (402) 0x42d11c UBFM	X7, X20, #61, #60

    (402) 0x42d120 FMADD	D6, D18, D25, D0

    (402) 0x42d124 LDR	D31, [X28, X7]

    (402) 0x42d128 LDR	D16, [X24, X19,LSL #3]

    (402) 0x42d12c FMADD	D7, D19, D20, D3

    (402) 0x42d130 FADD	D21, D27, D22

    (402) 0x42d134 LDR	X16, [SP, #216]

    (402) 0x42d138 LDR	X3, [SP, #128]

    (402) 0x42d13c LDR	D0, [X5, X17,LSL #3]

    (402) 0x42d140 ADD	X23, X16, X21

    (402) 0x42d144 FDIV	D17, D21, D31

    (402) 0x42d148 LDR	X4, [SP, #136]

    (402) 0x42d14c ADD	X21, X3, X21

    (402) 0x42d150 LDR	X16, [SP, #144]

    (402) 0x42d154 FSUB	D5, D7, S6

    (402) 0x42d158 FMUL	D23, D5, D30

    (402) 0x42d15c FADD	D24, D16, D23

    (402) 0x42d160 FDIV	D4, D17, D16

    (402) 0x42d164 FDIV	D3, D16, D24

    (402) 0x42d168 FMSUB	D27, D4, D23, D0

    (402) 0x42d16c STR	D27, [X4, X21,LSL #3]

    (402) 0x42d170 LDR	D1, [X28, X7]

    (402) 0x42d174 FMUL	D26, D1, D3

    (402) 0x42d178 STR	D26, [X16, X23,LSL #3]

    (402) 0x42d17c LDR	W23, [SP, #212]

    (402) 0x42d180 ADD	X27, X27, #1

    (402) 0x42d184 LDR	W15, [SP, #264]

    (402) 0x42d188 CMP	W15, W27

    (402) 0x42d18c B.LE	42d1b8

    (402) 0x42d190 LDR	W25, [SP, #276]

    (402) 0x42d194 LDR	W26, [SP, #268]

    (402) 0x42d198 LDR	W14, [SP, #272]

    (402) 0x42d19c SUB	W7, W25, W23

    (402) 0x42d1a0 B	42cda8

(400) 0x42d1a4 LDP	X23, X24, [SP, #48]

(400) 0x42d1a8 LDP	X19, X20, [SP, #16]

(400) 0x42d1ac LDP	X21, X22, [SP, #32]

(400) 0x42d1b0 LDP	X29, X30, [SP], #368

(400) 0x42d1b4 RET

  (401) 0x42d1b8 LDP	X23, X24, [SP, #48]

  (401) 0x42d1bc LDP	X25, X26, [SP, #64]

  (401) 0x42d1c0 LDP	X27, X28, [SP, #80]

  (401) 0x42d1c4 LDP	X19, X20, [SP, #16]

  (401) 0x42d1c8 LDP	X21, X22, [SP, #32]

  (401) 0x42d1cc LDP	X29, X30, [SP], #368

  (401) 0x42d1d0 RET

  (401) 0x42d1d4 ADD	W7, W7, #1

  (401) 0x42d1d8 MOVZ	W8, #0

  (401) 0x42d1dc B	42cd18

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:99	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 42% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42cca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR W3, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W4, [SP, #268]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42d1a8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W3, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42d1a4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42d1d4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.50	3.50	2.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42cca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR W3, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W4, [SP, #268]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42d1a8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W3, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42d1a4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 42d1d4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.36	4.83
▼Loop 400 - PdV.cpp:48-63 - exec–	0.00	0.00
▼Loop 401 - PdV.cpp:48-63 - exec–	0.00	0.00
▼Loop 402 - PdV.cpp:50-63 - exec–	0.01	0.01
○Loop 403 - PdV.cpp:51-63 - exec	6.36	4.79

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code