OV - exec - Function initialise_chunk(int, global_variables&) [clone ._omp

	Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4]	Module: exec	Source: initialise_chunk.cpp:77-82 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp: 77 - 82

--------------------------------------------------------------------------------

77: #pragma omp parallel for simd collapse(2)

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x428dd0 STP	X29, X30, [SP, #912]!

0x428dd4 ADD	X29, SP, #0

0x428dd8 STP	X19, X20, [SP, #16]

0x428ddc LDP	W19, W20, [X0, #24]

0x428de0 CMP	W20, #0

0x428de4 B.LE	429128

0x428de8 CMP	W19, #0

0x428dec B.LE	429128

0x428df0 STP	X21, X22, [SP, #32]

0x428df4 ORR	X22, XZR, X0

0x428df8 STP	X23, X24, [SP, #48]

0x428dfc MADD	W23, W20, W19, WZR

0x428e00 BL	403890

0x428e04 ORR	W21, WZR, W0

0x428e08 BL	4038c0

0x428e0c UDIV	W1, W23, W21

0x428e10 ORR	W2, WZR, W0

0x428e14 MSUB	W3, W1, W21, W23

0x428e18 CMP	W0, W3

0x428e1c B.CC	429148

  (349) 0x428e20 MADD	W14, W1, W2, W3

  (349) 0x428e24 ADD	W23, W1, W14

  (349) 0x428e28 CMP	W14, W23

  (349) 0x428e2c B.CS	429134

(350) 0x428e30 STP	X25, X26, [SP, #64]

(350) 0x428e34 UDIV	W6, W14, W19

(350) 0x428e38 ORR	W24, WZR, W19

(350) 0x428e3c STP	X27, X28, [SP, #80]

(350) 0x428e40 LDP	D30, D22, [X22]

(350) 0x428e44 LDR	X7, [X22, #16]

(350) 0x428e48 MSUB	W13, W6, W19, W14

(350) 0x428e4c SBFM	X6, X6, #0, #31

(350) 0x428e50 FMUL	D23, D22, D30

(350) 0x428e54 SUB	W15, W19, W13

(350) 0x428e58 DUP	V29.2D, V23.D[0]

(350) 0x428e5c HINT	#0

  (351) 0x428e60 CMP	W1, W15

  (351) 0x428e64 CSEL	W5, W1, W15, #9

  (351) 0x428e68 ADD	W15, W14, W5

  (351) 0x428e6c CMP	W14, W15

  (351) 0x428e70 B.CS	4290fc

  (351) 0x428e74 ADD	X0, X7, #672

  (351) 0x428e78 LDR	X12, [X7, #584]

  (351) 0x428e7c UBFM	X14, X6, #61, #60

  (351) 0x428e80 LDP	X22, X10, [X0]

  (351) 0x428e84 LDP	X21, X16, [X0, #24]

  (351) 0x428e88 ADD	X8, X12, X6,LSL #3

  (351) 0x428e8c MADD	X10, X6, X10, XZR

  (351) 0x428e90 LDR	X11, [X7, #656]

  (351) 0x428e94 MADD	X16, X6, X16, XZR

  (351) 0x428e98 LDR	X19, [X7, #552]

  (351) 0x428e9c LDR	X18, [X7, #720]

  (351) 0x428ea0 MADD	X11, X6, X11, XZR

  (351) 0x428ea4 CMP	W5, #1

  (351) 0x428ea8 B.EQ	4290d4

  (351) 0x428eac UBFM	W9, W5, #1, #31

  (351) 0x428eb0 SBFM	X26, X13, #0, #31

  (351) 0x428eb4 UBFM	X9, X9, #60, #59

  (351) 0x428eb8 ADD	X25, X11, X26

  (351) 0x428ebc SUB	X17, X9, #16

  (351) 0x428ec0 ADD	X28, X10, X26

  (351) 0x428ec4 ADD	X4, X22, X25,LSL #3

  (351) 0x428ec8 UBFM	X27, X17, #4, #63

  (351) 0x428ecc ADD	X2, X16, X26

  (351) 0x428ed0 ADD	X3, X21, X28,LSL #3

  (351) 0x428ed4 ADD	X30, X27, #1

  (351) 0x428ed8 UBFM	X27, X13, #61, #31

  (351) 0x428edc ADD	X1, X18, X2,LSL #3

  (351) 0x428ee0 ANDS	X17, X30, #4224

  (351) 0x428ee4 UBFM	X26, X2, #61, #60

  (351) 0x428ee8 MOVZ	X0, #0

  (351) 0x428eec UBFM	X25, X25, #61, #60

  (351) 0x428ef0 UBFM	X28, X28, #61, #60

  (351) 0x428ef4 ADD	X2, X19, X27

  (351) 0x428ef8 B.EQ	428ff8

  (351) 0x428efc CMP	X17, #1

  (351) 0x428f00 B.EQ	428fd4

  (351) 0x428f04 CMP	X17, #2

  (351) 0x428f08 B.EQ	428fb8

  (351) 0x428f0c CMP	X17, #3

  (351) 0x428f10 B.EQ	428f9c

  (351) 0x428f14 CMP	X17, #4

  (351) 0x428f18 B.EQ	428f80

  (351) 0x428f1c CMP	X17, #5

  (351) 0x428f20 B.EQ	428f64

  (351) 0x428f24 CMP	X17, #6

  (351) 0x428f28 B.EQ	428f48

  (351) 0x428f2c STR	Q29, [X22, X25]

  (351) 0x428f30 MOVZ	X0, #16

  (351) 0x428f34 LDR	D21, [X12, X14]

  (351) 0x428f38 DUP	V0.2D, V21.D[0]

  (351) 0x428f3c STR	Q0, [X21, X28]

  (351) 0x428f40 LDR	Q31, [X19, X27]

  (351) 0x428f44 STR	Q31, [X18, X26]

  (351) 0x428f48 STR	Q29, [X4, X0]

  (351) 0x428f4c LDR	D20, [X12, X14]

  (351) 0x428f50 DUP	V1.2D, V20.D[0]

  (351) 0x428f54 STR	Q1, [X3, X0]

  (351) 0x428f58 LDR	Q2, [X2, X0]

  (351) 0x428f5c STR	Q2, [X1, X0]

  (351) 0x428f60 ADD	X0, X0, #16

  (351) 0x428f64 STR	Q29, [X4, X0]

  (351) 0x428f68 LDR	D19, [X12, X14]

  (351) 0x428f6c DUP	V3.2D, V19.D[0]

  (351) 0x428f70 STR	Q3, [X3, X0]

  (351) 0x428f74 LDR	Q4, [X2, X0]

  (351) 0x428f78 STR	Q4, [X1, X0]

  (351) 0x428f7c ADD	X0, X0, #16

  (351) 0x428f80 STR	Q29, [X4, X0]

  (351) 0x428f84 LDR	D18, [X12, X14]

  (351) 0x428f88 DUP	V5.2D, V18.D[0]

  (351) 0x428f8c STR	Q5, [X3, X0]

  (351) 0x428f90 LDR	Q6, [X2, X0]

  (351) 0x428f94 STR	Q6, [X1, X0]

  (351) 0x428f98 ADD	X0, X0, #16

  (351) 0x428f9c STR	Q29, [X4, X0]

  (351) 0x428fa0 LDR	D17, [X12, X14]

  (351) 0x428fa4 DUP	V7.2D, V17.D[0]

  (351) 0x428fa8 STR	Q7, [X3, X0]

  (351) 0x428fac LDR	Q16, [X2, X0]

  (351) 0x428fb0 STR	Q16, [X1, X0]

  (351) 0x428fb4 ADD	X0, X0, #16

  (351) 0x428fb8 STR	Q29, [X4, X0]

  (351) 0x428fbc LDR	D24, [X12, X14]

  (351) 0x428fc0 DUP	V25.2D, V24.D[0]

  (351) 0x428fc4 STR	Q25, [X3, X0]

  (351) 0x428fc8 LDR	Q26, [X2, X0]

  (351) 0x428fcc STR	Q26, [X1, X0]

  (351) 0x428fd0 ADD	X0, X0, #16

  (351) 0x428fd4 STR	Q29, [X4, X0]

  (351) 0x428fd8 LDR	D27, [X12, X14]

  (351) 0x428fdc DUP	V28.2D, V27.D[0]

  (351) 0x428fe0 STR	Q28, [X3, X0]

  (351) 0x428fe4 LDR	Q30, [X2, X0]

  (351) 0x428fe8 STR	Q30, [X1, X0]

  (351) 0x428fec ADD	X0, X0, #16

  (351) 0x428ff0 CMP	X9, X0

  (351) 0x428ff4 B.EQ	4290c8

  (351) 0x428ff8 STR	W20, [SP, #108]

    (352) 0x428ffc STR	Q29, [X4, X0]

    (352) 0x429000 ADD	X17, X0, #16

    (352) 0x429004 ADD	X28, X0, #32

    (352) 0x429008 LD1R	{V22.2D}, [X8]

    (352) 0x42900c ADD	X30, X0, #48

    (352) 0x429010 ADD	X27, X0, #64

    (352) 0x429014 ADD	X26, X0, #80

    (352) 0x429018 ADD	X25, X0, #96

    (352) 0x42901c ADD	X20, X0, #112

    (352) 0x429020 STR	Q22, [X3, X0]

    (352) 0x429024 LDR	Q21, [X2, X0]

    (352) 0x429028 STR	Q21, [X1, X0]

    (352) 0x42902c ADD	X0, X0, #128

    (352) 0x429030 STR	Q29, [X4, X17]

    (352) 0x429034 LD1R	{V0.2D}, [X8]

    (352) 0x429038 STR	Q0, [X3, X17]

    (352) 0x42903c LDR	Q31, [X2, X17]

    (352) 0x429040 STR	Q31, [X1, X17]

    (352) 0x429044 STR	Q29, [X4, X28]

    (352) 0x429048 LD1R	{V20.2D}, [X8]

    (352) 0x42904c STR	Q20, [X3, X28]

    (352) 0x429050 LDR	Q1, [X2, X28]

    (352) 0x429054 STR	Q1, [X1, X28]

    (352) 0x429058 STR	Q29, [X4, X30]

    (352) 0x42905c LD1R	{V2.2D}, [X8]

    (352) 0x429060 STR	Q2, [X3, X30]

    (352) 0x429064 LDR	Q19, [X2, X30]

    (352) 0x429068 STR	Q19, [X1, X30]

    (352) 0x42906c STR	Q29, [X4, X27]

    (352) 0x429070 LD1R	{V3.2D}, [X8]

    (352) 0x429074 STR	Q3, [X3, X27]

    (352) 0x429078 LDR	Q4, [X2, X27]

    (352) 0x42907c STR	Q4, [X1, X27]

    (352) 0x429080 STR	Q29, [X4, X26]

    (352) 0x429084 LD1R	{V18.2D}, [X8]

    (352) 0x429088 STR	Q18, [X3, X26]

    (352) 0x42908c LDR	Q5, [X2, X26]

    (352) 0x429090 STR	Q5, [X1, X26]

    (352) 0x429094 STR	Q29, [X4, X25]

    (352) 0x429098 LD1R	{V6.2D}, [X8]

    (352) 0x42909c STR	Q6, [X3, X25]

    (352) 0x4290a0 LDR	Q17, [X2, X25]

    (352) 0x4290a4 STR	Q17, [X1, X25]

    (352) 0x4290a8 STR	Q29, [X4, X20]

    (352) 0x4290ac LD1R	{V7.2D}, [X8]

    (352) 0x4290b0 STR	Q7, [X3, X20]

    (352) 0x4290b4 LDR	Q16, [X2, X20]

    (352) 0x4290b8 STR	Q16, [X1, X20]

    (352) 0x4290bc CMP	X9, X0

    (352) 0x4290c0 B.NE	428ffc

  (351) 0x4290c4 LDR	W20, [SP, #108]

  (351) 0x4290c8 TBZ	W5, #0, 4290f8

  (351) 0x4290cc AND	W5, W5, #1951

  (351) 0x4290d0 ADD	W13, W13, W5

  (351) 0x4290d4 SBFM	X8, X13, #0, #31

  (351) 0x4290d8 ADD	X11, X11, X8

  (351) 0x4290dc ADD	X10, X10, X8

  (351) 0x4290e0 ADD	X16, X16, X8

  (351) 0x4290e4 STR	D23, [X22, X11,LSL #3]

  (351) 0x4290e8 LDR	D24, [X12, X14]

  (351) 0x4290ec STR	D24, [X21, X10,LSL #3]

  (351) 0x4290f0 LDR	D25, [X19, X13,UXTW #3]

  (351) 0x4290f4 STR	D25, [X18, X16,LSL #3]

  (351) 0x4290f8 ORR	W14, WZR, W15

  (351) 0x4290fc ADD	X6, X6, #1

  (351) 0x429100 CMP	W20, W6

  (351) 0x429104 B.LE	429118

  (351) 0x429108 SUB	W1, W23, W14

  (351) 0x42910c ORR	W15, WZR, W24

  (351) 0x429110 MOVZ	W13, #0

  (351) 0x429114 B	428e60

(350) 0x429118 LDP	X21, X22, [SP, #32]

(350) 0x42911c LDP	X23, X24, [SP, #48]

(350) 0x429120 LDP	X25, X26, [SP, #64]

(350) 0x429124 LDP	X27, X28, [SP, #80]

(350) 0x429128 LDP	X19, X20, [SP, #16]

(350) 0x42912c LDP	X29, X30, [SP], #112

(350) 0x429130 RET

  (349) 0x429134 LDP	X21, X22, [SP, #32]

  (349) 0x429138 LDP	X23, X24, [SP, #48]

  (349) 0x42913c LDP	X19, X20, [SP, #16]

  (349) 0x429140 LDP	X29, X30, [SP], #112

  (349) 0x429144 RET

  (349) 0x429148 ADD	W1, W1, #1

  (349) 0x42914c MOVZ	W3, #0

  (349) 0x429150 B	428e20

0x429154 HINT	#0

0x429158 HINT	#0

0x42915c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.01+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.08	1.92	2.00	2.00	3.00	2.00	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00
cycles	2.50	2.50	2.08	1.92	2.00	2.00	3.00	2.00	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428dd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W19, W20, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 429128 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W19, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 429128 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MADD W23, W20, W19, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 429148 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.08	1.92	2.00	2.00	3.00	2.00	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00
cycles	2.50	2.50	2.08	1.92	2.00	2.00	3.00	2.00	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428dd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W19, W20, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 429128 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W19, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 429128 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MADD W23, W20, W19, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 429148 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼initialise_chunk(int, global_variables&) [clone ._omp_fn.4]–	0.02	0.02
▼Loop 350 - initialise_chunk.cpp:77-82 - exec–	0.00	0.00
▼Loop 351 - initialise_chunk.cpp:77-82 - exec–	0.00	0.00
○Loop 352 - initialise_chunk.cpp:80-82 - exec	0.02	0.02
○Loop 349 - initialise_chunk.cpp:77-77 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code