OV - exec - Function ideal_gas_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: ideal_gas_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: ideal_gas.cpp:37-45 [...]	Coverage (incl. loops): 4.83% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 37 - 45

--------------------------------------------------------------------------------

37: #pragma omp parallel for simd collapse(2)

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x427c60 STP	X29, X30, [SP, #912]!

0x427c64 ADD	X29, SP, #0

0x427c68 STP	X19, X20, [SP, #16]

0x427c6c ORR	X20, XZR, X0

0x427c70 STP	X21, X22, [SP, #32]

0x427c74 STP	X23, X24, [SP, #48]

0x427c78 LDP	W3, W22, [X0, #40]

0x427c7c LDP	W23, W0, [X0, #32]

0x427c80 ADD	W1, W3, #1

0x427c84 ADD	W22, W22, #2

0x427c88 CMP	W1, W22

0x427c8c B.GE	428008

0x427c90 ADD	W23, W23, #1

0x427c94 ADD	W19, W0, #2

0x427c98 STP	X25, X26, [SP, #64]

0x427c9c SUB	W25, W22, W1

0x427ca0 STR	W1, [SP, #108]

0x427ca4 CMP	W23, W19

0x427ca8 B.GE	428004

0x427cac SUB	W24, W19, W23

0x427cb0 BL	403890

0x427cb4 MADD	W26, W25, W24, WZR

0x427cb8 ORR	W21, WZR, W0

0x427cbc BL	4038c0

0x427cc0 LDR	W6, [SP, #108]

0x427cc4 ORR	W4, WZR, W0

0x427cc8 UDIV	W2, W26, W21

0x427ccc MSUB	W5, W2, W21, W26

0x427cd0 CMP	W0, W5

0x427cd4 B.CC	428038

  (337) 0x427cd8 MADD	W21, W2, W4, W5

  (337) 0x427cdc ADD	W7, W2, W21

  (337) 0x427ce0 STR	W7, [SP, #108]

  (337) 0x427ce4 CMP	W21, W7

  (337) 0x427ce8 B.CS	428004

  (337) 0x427cec UDIV	W8, W21, W24

  (337) 0x427cf0 ORR	X9, XZR, #3651

  (337) 0x427cf4 ADRP	X10,

  (337) 0x427cf8 FMOV	D24, #1.0000000

  (337) 0x427cfc FMOV	V27.2D, #1.0000000

  (337) 0x427d00 MOVK	X9, #16374

  (337) 0x427d04 STP	X27, X28, [SP, #80]

  (337) 0x427d08 FMOV	D26, X9

  (337) 0x427d0c LDR	D25, [X10, #1144]

  (337) 0x427d10 LDP	X27, X28, [X20]

  (337) 0x427d14 LDP	X25, X26, [X20, #16]

  (337) 0x427d18 MSUB	W11, W8, W24, W21

  (337) 0x427d1c ADD	W12, W8, W6

  (337) 0x427d20 DUP	V28.2D, V25.D[0]

  (337) 0x427d24 SBFM	X5, X12, #0, #31

  (337) 0x427d28 DUP	V29.2D, V26.D[0]

  (337) 0x427d2c ADD	W4, W11, W23

  (337) 0x427d30 SUB	W20, W19, W4

  (337) 0x427d34 HINT	#0

  (337) 0x427d38 HINT	#0

  (337) 0x427d3c HINT	#0

    (338) 0x427d40 CMP	W2, W20

    (338) 0x427d44 CSEL	W2, W2, W20, #9

    (338) 0x427d48 ADD	W19, W21, W2

    (338) 0x427d4c CMP	W21, W19

    (338) 0x427d50 B.CS	427fe4

    (338) 0x427d54 LDR	X13, [X25]

    (338) 0x427d58 LDR	X14, [X26]

    (338) 0x427d5c LDR	X15, [X27]

    (338) 0x427d60 MADD	X12, X5, X13, XZR

    (338) 0x427d64 LDR	X16, [X28]

    (338) 0x427d68 MADD	X14, X5, X14, XZR

    (338) 0x427d6c LDR	X21, [X25, #16]

    (338) 0x427d70 MADD	X10, X5, X15, XZR

    (338) 0x427d74 LDR	X20, [X26, #16]

    (338) 0x427d78 MADD	X13, X5, X16, XZR

    (338) 0x427d7c LDR	X18, [X27, #16]

    (338) 0x427d80 LDR	X30, [X28, #16]

    (338) 0x427d84 CMP	W2, #1

    (338) 0x427d88 B.EQ	427f94

    (338) 0x427d8c UBFM	W17, W2, #1, #31

    (338) 0x427d90 SBFM	X3, X4, #0, #31

    (338) 0x427d94 UBFM	X11, X17, #60, #59

    (338) 0x427d98 ADD	X6, X10, X3

    (338) 0x427d9c SUB	X7, X11, #16

    (338) 0x427da0 ADD	X17, X13, X3

    (338) 0x427da4 ADD	X1, X18, X6,LSL #3

    (338) 0x427da8 UBFM	X9, X7, #4, #63

    (338) 0x427dac ADD	X16, X12, X3

    (338) 0x427db0 ADD	X8, X30, X17,LSL #3

    (338) 0x427db4 ADD	X15, X9, #1

    (338) 0x427db8 ADD	X3, X14, X3

    (338) 0x427dbc ADD	X7, X21, X16,LSL #3

    (338) 0x427dc0 ANDS	X9, X15, #4160

    (338) 0x427dc4 MOVZ	X0, #0

    (338) 0x427dc8 UBFM	X15, X6, #61, #60

    (338) 0x427dcc UBFM	X17, X17, #61, #60

    (338) 0x427dd0 ADD	X6, X20, X3,LSL #3

    (338) 0x427dd4 UBFM	X16, X16, #61, #60

    (338) 0x427dd8 UBFM	X3, X3, #61, #60

    (338) 0x427ddc B.EQ	427ea0

    (338) 0x427de0 CMP	X9, #1

    (338) 0x427de4 B.EQ	427e60

    (338) 0x427de8 CMP	X9, #2

    (338) 0x427dec B.EQ	427e28

    (338) 0x427df0 LDR	Q23, [X18, X15]

    (338) 0x427df4 MOVZ	X0, #16

    (338) 0x427df8 LDR	Q30, [X30, X17]

    (338) 0x427dfc FDIV	V31.2D, V27.2D, V23.2D

    (338) 0x427e00 FMUL	V0.2D, V30.2D, V23.2D

    (338) 0x427e04 FMUL	V1.2D, V31.2D, V31.2D

    (338) 0x427e08 FMUL	V2.2D, V0.2D, V28.2D

    (338) 0x427e0c STR	Q2, [X21, X16]

    (338) 0x427e10 LDR	Q3, [X18, X15]

    (338) 0x427e14 FMUL	V4.2D, V3.2D, V29.2D

    (338) 0x427e18 FMUL	V5.2D, V4.2D, V2.2D

    (338) 0x427e1c FMUL	V6.2D, V5.2D, V1.2D

    (338) 0x427e20 FSQRT	V7.2D, V6.2D

    (338) 0x427e24 STR	Q7, [X20, X3]

    (338) 0x427e28 LDR	Q16, [X1, X0]

    (338) 0x427e2c LDR	Q17, [X8, X0]

    (338) 0x427e30 FDIV	V18.2D, V27.2D, V16.2D

    (338) 0x427e34 FMUL	V19.2D, V17.2D, V16.2D

    (338) 0x427e38 FMUL	V20.2D, V18.2D, V18.2D

    (338) 0x427e3c FMUL	V21.2D, V19.2D, V28.2D

    (338) 0x427e40 STR	Q21, [X7, X0]

    (338) 0x427e44 LDR	Q22, [X1, X0]

    (338) 0x427e48 FMUL	V23.2D, V22.2D, V29.2D

    (338) 0x427e4c FMUL	V30.2D, V23.2D, V21.2D

    (338) 0x427e50 FMUL	V31.2D, V30.2D, V20.2D

    (338) 0x427e54 FSQRT	V0.2D, V31.2D

    (338) 0x427e58 STR	Q0, [X6, X0]

    (338) 0x427e5c ADD	X0, X0, #16

    (338) 0x427e60 LDR	Q1, [X1, X0]

    (338) 0x427e64 LDR	Q2, [X8, X0]

    (338) 0x427e68 FDIV	V3.2D, V27.2D, V1.2D

    (338) 0x427e6c FMUL	V4.2D, V2.2D, V1.2D

    (338) 0x427e70 FMUL	V5.2D, V3.2D, V3.2D

    (338) 0x427e74 FMUL	V6.2D, V4.2D, V28.2D

    (338) 0x427e78 STR	Q6, [X7, X0]

    (338) 0x427e7c LDR	Q7, [X1, X0]

    (338) 0x427e80 FMUL	V16.2D, V7.2D, V29.2D

    (338) 0x427e84 FMUL	V17.2D, V16.2D, V6.2D

    (338) 0x427e88 FMUL	V18.2D, V17.2D, V5.2D

    (338) 0x427e8c FSQRT	V19.2D, V18.2D

    (338) 0x427e90 STR	Q19, [X6, X0]

    (338) 0x427e94 ADD	X0, X0, #16

    (338) 0x427e98 CMP	X0, X11

    (338) 0x427e9c B.EQ	427f88

      (339) 0x427ea0 LDR	Q20, [X1, X0]

      (339) 0x427ea4 ADD	X17, X0, #16

      (339) 0x427ea8 ADD	X15, X0, #32

      (339) 0x427eac ADD	X9, X0, #48

      (339) 0x427eb0 LDR	Q21, [X8, X0]

      (339) 0x427eb4 FDIV	V22.2D, V27.2D, V20.2D

      (339) 0x427eb8 FMUL	V30.2D, V21.2D, V20.2D

      (339) 0x427ebc FMUL	V23.2D, V22.2D, V22.2D

      (339) 0x427ec0 FMUL	V0.2D, V30.2D, V28.2D

      (339) 0x427ec4 STR	Q0, [X7, X0]

      (339) 0x427ec8 LDR	Q31, [X1, X0]

      (339) 0x427ecc FMUL	V1.2D, V31.2D, V29.2D

      (339) 0x427ed0 FMUL	V2.2D, V1.2D, V0.2D

      (339) 0x427ed4 FMUL	V3.2D, V2.2D, V23.2D

      (339) 0x427ed8 FSQRT	V4.2D, V3.2D

      (339) 0x427edc STR	Q4, [X6, X0]

      (339) 0x427ee0 ADD	X0, X0, #64

      (339) 0x427ee4 LDR	Q5, [X1, X17]

      (339) 0x427ee8 LDR	Q6, [X8, X17]

      (339) 0x427eec FDIV	V7.2D, V27.2D, V5.2D

      (339) 0x427ef0 FMUL	V16.2D, V6.2D, V5.2D

      (339) 0x427ef4 FMUL	V17.2D, V7.2D, V7.2D

      (339) 0x427ef8 FMUL	V18.2D, V16.2D, V28.2D

      (339) 0x427efc STR	Q18, [X7, X17]

      (339) 0x427f00 LDR	Q19, [X1, X17]

      (339) 0x427f04 FMUL	V20.2D, V19.2D, V29.2D

      (339) 0x427f08 FMUL	V21.2D, V20.2D, V18.2D

      (339) 0x427f0c FMUL	V22.2D, V21.2D, V17.2D

      (339) 0x427f10 FSQRT	V30.2D, V22.2D

      (339) 0x427f14 STR	Q30, [X6, X17]

      (339) 0x427f18 LDR	Q23, [X1, X15]

      (339) 0x427f1c LDR	Q0, [X8, X15]

      (339) 0x427f20 FDIV	V31.2D, V27.2D, V23.2D

      (339) 0x427f24 FMUL	V1.2D, V0.2D, V23.2D

      (339) 0x427f28 FMUL	V2.2D, V31.2D, V31.2D

      (339) 0x427f2c FMUL	V3.2D, V1.2D, V28.2D

      (339) 0x427f30 STR	Q3, [X7, X15]

      (339) 0x427f34 LDR	Q4, [X1, X15]

      (339) 0x427f38 FMUL	V5.2D, V4.2D, V29.2D

      (339) 0x427f3c FMUL	V6.2D, V5.2D, V3.2D

      (339) 0x427f40 FMUL	V7.2D, V6.2D, V2.2D

      (339) 0x427f44 FSQRT	V16.2D, V7.2D

      (339) 0x427f48 STR	Q16, [X6, X15]

      (339) 0x427f4c LDR	Q17, [X1, X9]

      (339) 0x427f50 LDR	Q18, [X8, X9]

      (339) 0x427f54 FDIV	V19.2D, V27.2D, V17.2D

      (339) 0x427f58 FMUL	V20.2D, V18.2D, V17.2D

      (339) 0x427f5c FMUL	V21.2D, V19.2D, V19.2D

      (339) 0x427f60 FMUL	V22.2D, V20.2D, V28.2D

      (339) 0x427f64 STR	Q22, [X7, X9]

      (339) 0x427f68 LDR	Q30, [X1, X9]

      (339) 0x427f6c FMUL	V23.2D, V30.2D, V29.2D

      (339) 0x427f70 FMUL	V0.2D, V23.2D, V22.2D

      (339) 0x427f74 FMUL	V31.2D, V0.2D, V21.2D

      (339) 0x427f78 FSQRT	V1.2D, V31.2D

      (339) 0x427f7c STR	Q1, [X6, X9]

      (339) 0x427f80 CMP	X0, X11

      (339) 0x427f84 B.NE	427ea0

    (338) 0x427f88 TBZ	W2, #0, 427fe0

    (338) 0x427f8c AND	W2, W2, #1951

    (338) 0x427f90 ADD	W4, W4, W2

    (338) 0x427f94 SBFM	X11, X4, #0, #31

    (338) 0x427f98 ADD	X10, X10, X11

    (338) 0x427f9c ADD	X13, X13, X11

    (338) 0x427fa0 UBFM	X1, X10, #61, #60

    (338) 0x427fa4 ADD	X12, X12, X11

    (338) 0x427fa8 LDR	D2, [X30, X13,LSL #3]

    (338) 0x427fac ADD	X14, X14, X11

    (338) 0x427fb0 LDR	D3, [X18, X1]

    (338) 0x427fb4 FMUL	D4, D3, D2

    (338) 0x427fb8 FDIV	D5, D24, D3

    (338) 0x427fbc FMUL	D6, D4, D25

    (338) 0x427fc0 STR	D6, [X21, X12,LSL #3]

    (338) 0x427fc4 LDR	D7, [X18, X1]

    (338) 0x427fc8 FMUL	D16, D5, D5

    (338) 0x427fcc FMUL	D17, D7, D26

    (338) 0x427fd0 FMUL	D18, D17, D6

    (338) 0x427fd4 FMUL	D19, D18, D16

    (338) 0x427fd8 FSQRT	D20, D19

    (338) 0x427fdc STR	D20, [X20, X14,LSL #3]

    (338) 0x427fe0 ORR	W21, WZR, W19

    (338) 0x427fe4 ADD	X5, X5, #1

    (338) 0x427fe8 CMP	W22, W5

    (338) 0x427fec B.LE	42801c

    (338) 0x427ff0 LDR	W19, [SP, #108]

    (338) 0x427ff4 ORR	W4, WZR, W23

    (338) 0x427ff8 ORR	W20, WZR, W24

    (338) 0x427ffc SUB	W2, W19, W21

    (338) 0x428000 B	427d40

(336) 0x428004 LDP	X25, X26, [SP, #64]

(336) 0x428008 LDP	X19, X20, [SP, #16]

(336) 0x42800c LDP	X21, X22, [SP, #32]

(336) 0x428010 LDP	X23, X24, [SP, #48]

(336) 0x428014 LDP	X29, X30, [SP], #112

(336) 0x428018 RET

  (337) 0x42801c LDP	X25, X26, [SP, #64]

  (337) 0x428020 LDP	X27, X28, [SP, #80]

  (337) 0x428024 LDP	X19, X20, [SP, #16]

  (337) 0x428028 LDP	X21, X22, [SP, #32]

  (337) 0x42802c LDP	X23, X24, [SP, #48]

  (337) 0x428030 LDP	X29, X30, [SP], #112

  (337) 0x428034 RET

  (337) 0x428038 ADD	W2, W2, #1

  (337) 0x42803c MOVZ	W5, #0

  (337) 0x428040 B	427cd8

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	ideal_gas.cpp:37-45
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:37-45
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 45% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W3, W22, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W23, W0, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 428008 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W25, W22, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR W1, [SP, #108]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W23, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 428004 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W19, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W26, W25, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W6, [SP, #108]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W4, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UDIV W2, W26, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W5, W2, W21, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 428038 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	ideal_gas.cpp:37-45
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:37-45
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W3, W22, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W23, W0, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 428008 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W23, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W25, W22, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR W1, [SP, #108]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W23, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 428004 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W19, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W26, W25, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W6, [SP, #108]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W4, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UDIV W2, W26, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W5, W2, W21, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 428038 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	4.83	3.67
▼Loop 336 - ideal_gas.cpp:37-45 - exec–	0.00	0.00
▼Loop 337 - ideal_gas.cpp:37-45 - exec–	0.00	0.00
▼Loop 338 - ideal_gas.cpp:39-45 - exec–	0.00	0.01
○Loop 339 - ideal_gas.cpp:40-45 - exec	4.83	3.64

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code