OV - exec - Function generate_chunk(int, global_variables&) [clone ._omp

	Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0]	Module: exec	Source: generate_chunk.cpp:74-80 [...]	Coverage (incl. loops): 0.05% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 74 - 80

--------------------------------------------------------------------------------

74: #pragma omp parallel for simd collapse(2)

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

78:       field.density0(i, j) = state_density[0];

79:       field.xvel0(i, j) = state_xvel[0];

80:       field.yvel0(i, j) = state_yvel[0];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x427060 STP	X29, X30, [SP, #880]!

0x427064 ADD	X29, SP, #0

0x427068 STP	X23, X24, [SP, #48]

0x42706c LDP	W23, W24, [X0, #40]

0x427070 CMP	W24, #0

0x427074 B.LE	427344

0x427078 CMP	W23, #0

0x42707c B.LE	427344

0x427080 STP	X19, X20, [SP, #16]

0x427084 ORR	X20, XZR, X0

0x427088 STP	X21, X22, [SP, #32]

0x42708c MADD	W21, W24, W23, WZR

0x427090 BL	403890

0x427094 ORR	W19, WZR, W0

0x427098 BL	4038c0

0x42709c UDIV	W1, W21, W19

0x4270a0 ORR	W2, WZR, W0

0x4270a4 MSUB	W3, W1, W19, W21

0x4270a8 CMP	W0, W3

0x4270ac B.CC	427364

  (322) 0x4270b0 MADD	W30, W1, W2, W3

  (322) 0x4270b4 ADD	W0, W1, W30

  (322) 0x4270b8 STR	W0, [SP, #108]

  (322) 0x4270bc CMP	W30, W0

  (322) 0x4270c0 B.CS	427350

(323) 0x4270c4 UDIV	W13, W30, W23

(323) 0x4270c8 STP	X25, X26, [SP, #64]

(323) 0x4270cc STP	X27, X28, [SP, #80]

(323) 0x4270d0 LDP	X4, X5, [X20]

(323) 0x4270d4 LDR	X15, [X20, #32]

(323) 0x4270d8 MSUB	W7, W13, W23, W30

(323) 0x4270dc SBFM	X13, X13, #0, #31

(323) 0x4270e0 STP	X5, X4, [SP, #112]

(323) 0x4270e4 SUB	W27, W23, W7

(323) 0x4270e8 LDP	X6, X8, [X20, #16]

(323) 0x4270ec STP	X6, X8, [SP, #128]

  (324) 0x4270f0 CMP	W1, W27

  (324) 0x4270f4 CSEL	W1, W1, W27, #9

  (324) 0x4270f8 ADD	W25, W30, W1

  (324) 0x4270fc CMP	W30, W25

  (324) 0x427100 B.CS	427314

  (324) 0x427104 ORR	X9, XZR, X15

  (324) 0x427108 LDR	X18, [X15, #48]

  (324) 0x42710c LDR	X11, [SP, #112]

  (324) 0x427110 LDR	X12, [SP, #120]

  (324) 0x427114 MADD	X18, X13, X18, XZR

  (324) 0x427118 LDR	X14, [SP, #128]

  (324) 0x42711c LDR	X22, [SP, #136]

  (324) 0x427120 LDR	X17, [X9], #168

  (324) 0x427124 LDR	X16, [X15, #168]

  (324) 0x427128 LDR	X10, [X15, #216]

  (324) 0x42712c MADD	X17, X13, X17, XZR

  (324) 0x427130 LDR	X6, [X11, #8]

  (324) 0x427134 MADD	X16, X13, X16, XZR

  (324) 0x427138 LDR	X5, [X12, #8]

  (324) 0x42713c MADD	X19, X13, X10, XZR

  (324) 0x427140 LDR	X4, [X14, #8]

  (324) 0x427144 LDR	X3, [X22, #8]

  (324) 0x427148 LDR	X27, [X9, #16]

  (324) 0x42714c LDR	X28, [X15, #16]

  (324) 0x427150 LDR	X30, [X15, #64]

  (324) 0x427154 LDR	X26, [X15, #232]

  (324) 0x427158 CMP	W1, #1

  (324) 0x42715c B.EQ	4272dc

  (324) 0x427160 UBFM	W20, W1, #1, #31

  (324) 0x427164 SBFM	X2, X7, #0, #31

  (324) 0x427168 UBFM	X14, X20, #60, #59

  (324) 0x42716c ADD	X8, X18, X2

  (324) 0x427170 SUB	X9, X14, #16

  (324) 0x427174 ADD	X21, X17, X2

  (324) 0x427178 ADD	X11, X30, X8,LSL #3

  (324) 0x42717c UBFM	X12, X9, #4, #63

  (324) 0x427180 ADD	X20, X16, X2

  (324) 0x427184 ADD	X10, X28, X21,LSL #3

  (324) 0x427188 ADD	X22, X12, #1

  (324) 0x42718c ADD	X2, X19, X2

  (324) 0x427190 ADD	X9, X27, X20,LSL #3

  (324) 0x427194 ANDS	X12, X22, #4160

  (324) 0x427198 MOVZ	X0, #0

  (324) 0x42719c UBFM	X22, X8, #61, #60

  (324) 0x4271a0 UBFM	X21, X21, #61, #60

  (324) 0x4271a4 ADD	X8, X26, X2,LSL #3

  (324) 0x4271a8 UBFM	X20, X20, #61, #60

  (324) 0x4271ac UBFM	X2, X2, #61, #60

  (324) 0x4271b0 B.EQ	427238

  (324) 0x4271b4 CMP	X12, #1

  (324) 0x4271b8 B.EQ	42720c

  (324) 0x4271bc CMP	X12, #2

  (324) 0x4271c0 B.EQ	4271e8

  (324) 0x4271c4 LD1R	{V28.2D}, [X6]

  (324) 0x4271c8 MOVZ	X0, #16

  (324) 0x4271cc STR	Q28, [X30, X22]

  (324) 0x4271d0 LD1R	{V29.2D}, [X5]

  (324) 0x4271d4 STR	Q29, [X28, X21]

  (324) 0x4271d8 LD1R	{V30.2D}, [X4]

  (324) 0x4271dc STR	Q30, [X27, X20]

  (324) 0x4271e0 LD1R	{V31.2D}, [X3]

  (324) 0x4271e4 STR	Q31, [X26, X2]

  (324) 0x4271e8 LD1R	{V24.2D}, [X6]

  (324) 0x4271ec STR	Q24, [X11, X0]

  (324) 0x4271f0 LD1R	{V25.2D}, [X5]

  (324) 0x4271f4 STR	Q25, [X10, X0]

  (324) 0x4271f8 LD1R	{V26.2D}, [X4]

  (324) 0x4271fc STR	Q26, [X9, X0]

  (324) 0x427200 LD1R	{V27.2D}, [X3]

  (324) 0x427204 STR	Q27, [X8, X0]

  (324) 0x427208 ADD	X0, X0, #16

  (324) 0x42720c LD1R	{V20.2D}, [X6]

  (324) 0x427210 STR	Q20, [X11, X0]

  (324) 0x427214 LD1R	{V21.2D}, [X5]

  (324) 0x427218 STR	Q21, [X10, X0]

  (324) 0x42721c LD1R	{V22.2D}, [X4]

  (324) 0x427220 STR	Q22, [X9, X0]

  (324) 0x427224 LD1R	{V23.2D}, [X3]

  (324) 0x427228 STR	Q23, [X8, X0]

  (324) 0x42722c ADD	X0, X0, #16

  (324) 0x427230 CMP	X14, X0

  (324) 0x427234 B.EQ	4272d0

    (325) 0x427238 LD1R	{V0.2D}, [X6]

    (325) 0x42723c ADD	X22, X0, #16

    (325) 0x427240 ADD	X21, X0, #32

    (325) 0x427244 ADD	X12, X0, #48

    (325) 0x427248 STR	Q0, [X11, X0]

    (325) 0x42724c LD1R	{V1.2D}, [X5]

    (325) 0x427250 STR	Q1, [X10, X0]

    (325) 0x427254 LD1R	{V2.2D}, [X4]

    (325) 0x427258 STR	Q2, [X9, X0]

    (325) 0x42725c LD1R	{V3.2D}, [X3]

    (325) 0x427260 STR	Q3, [X8, X0]

    (325) 0x427264 ADD	X0, X0, #64

    (325) 0x427268 LD1R	{V4.2D}, [X6]

    (325) 0x42726c STR	Q4, [X11, X22]

    (325) 0x427270 LD1R	{V5.2D}, [X5]

    (325) 0x427274 STR	Q5, [X10, X22]

    (325) 0x427278 LD1R	{V6.2D}, [X4]

    (325) 0x42727c STR	Q6, [X9, X22]

    (325) 0x427280 LD1R	{V7.2D}, [X3]

    (325) 0x427284 STR	Q7, [X8, X22]

    (325) 0x427288 LD1R	{V16.2D}, [X6]

    (325) 0x42728c STR	Q16, [X11, X21]

    (325) 0x427290 LD1R	{V17.2D}, [X5]

    (325) 0x427294 STR	Q17, [X10, X21]

    (325) 0x427298 LD1R	{V18.2D}, [X4]

    (325) 0x42729c STR	Q18, [X9, X21]

    (325) 0x4272a0 LD1R	{V19.2D}, [X3]

    (325) 0x4272a4 STR	Q19, [X8, X21]

    (325) 0x4272a8 LD1R	{V28.2D}, [X6]

    (325) 0x4272ac STR	Q28, [X11, X12]

    (325) 0x4272b0 LD1R	{V29.2D}, [X5]

    (325) 0x4272b4 STR	Q29, [X10, X12]

    (325) 0x4272b8 LD1R	{V30.2D}, [X4]

    (325) 0x4272bc STR	Q30, [X9, X12]

    (325) 0x4272c0 LD1R	{V31.2D}, [X3]

    (325) 0x4272c4 STR	Q31, [X8, X12]

    (325) 0x4272c8 CMP	X14, X0

    (325) 0x4272cc B.NE	427238

  (324) 0x4272d0 TBZ	W1, #0, 427310

  (324) 0x4272d4 AND	W1, W1, #1951

  (324) 0x4272d8 ADD	W7, W7, W1

  (324) 0x4272dc LDR	D24, [X6]

  (324) 0x4272e0 SBFM	X14, X7, #0, #31

  (324) 0x4272e4 ADD	X18, X18, X14

  (324) 0x4272e8 ADD	X17, X17, X14

  (324) 0x4272ec ADD	X16, X16, X14

  (324) 0x4272f0 ADD	X19, X19, X14

  (324) 0x4272f4 STR	D24, [X30, X18,LSL #3]

  (324) 0x4272f8 LDR	D25, [X5]

  (324) 0x4272fc STR	D25, [X28, X17,LSL #3]

  (324) 0x427300 LDR	D26, [X4]

  (324) 0x427304 STR	D26, [X27, X16,LSL #3]

  (324) 0x427308 LDR	D27, [X3]

  (324) 0x42730c STR	D27, [X26, X19,LSL #3]

  (324) 0x427310 ORR	W30, WZR, W25

  (324) 0x427314 ADD	X13, X13, #1

  (324) 0x427318 CMP	W24, W13

  (324) 0x42731c B.LE	427334

  (324) 0x427320 LDR	W25, [SP, #108]

  (324) 0x427324 MOVZ	W7, #0

  (324) 0x427328 ORR	W27, WZR, W23

  (324) 0x42732c SUB	W1, W25, W30

  (324) 0x427330 B	4270f0

(323) 0x427334 LDP	X19, X20, [SP, #16]

(323) 0x427338 LDP	X21, X22, [SP, #32]

(323) 0x42733c LDP	X25, X26, [SP, #64]

(323) 0x427340 LDP	X27, X28, [SP, #80]

(323) 0x427344 LDP	X23, X24, [SP, #48]

(323) 0x427348 LDP	X29, X30, [SP], #144

(323) 0x42734c RET

  (322) 0x427350 LDP	X19, X20, [SP, #16]

  (322) 0x427354 LDP	X21, X22, [SP, #32]

  (322) 0x427358 LDP	X23, X24, [SP, #48]

  (322) 0x42735c LDP	X29, X30, [SP], #144

  (322) 0x427360 RET

  (322) 0x427364 ADD	W1, W1, #1

  (322) 0x427368 MOVZ	W3, #0

  (322) 0x42736c B	4270b0

Coverage (%)	Name	Source Location	Module
►98.87+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.13+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.08	1.92	2.00	2.00	3.00	2.00	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00
cycles	2.50	2.50	2.08	1.92	2.00	2.00	3.00	2.00	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W24, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 427344 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 427344 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MADD W21, W24, W23, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 427364 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.08	1.92	2.00	2.00	3.00	2.00	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00
cycles	2.50	2.50	2.08	1.92	2.00	2.00	3.00	2.00	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.50
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W23, W24, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 427344 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 427344 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MADD W21, W24, W23, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 427364 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone ._omp_fn.0]–	0.05	0.04
▼Loop 323 - generate_chunk.cpp:74-80 - exec–	0.00	0.00
○Loop 322 - generate_chunk.cpp:74-74 - exec	0.00	0.00
▼Loop 324 - generate_chunk.cpp:74-80 - exec–	0.00	0.00
○Loop 325 - generate_chunk.cpp:77-80 - exec	0.05	0.04

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code