OV - exec - Function flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage (incl. loops): 4.66% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp: 36 - 40

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36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x426a00 STP	X29, X30, [SP, #688]!

0x426a04 ADD	X29, SP, #0

0x426a08 STP	X19, X20, [SP, #16]

0x426a0c ORR	X20, XZR, X0

0x426a10 STP	X21, X22, [SP, #32]

0x426a14 LDP	W22, W1, [X0, #80]

0x426a18 LDP	W0, W3, [X0, #72]

0x426a1c ADD	W2, W1, #3

0x426a20 ADD	W22, W22, #1

0x426a24 ADD	W4, W0, #1

0x426a28 STP	W2, W4, [SP, #240]

0x426a2c CMP	W22, W2

0x426a30 B.GE	426ea4

0x426a34 ADD	W19, W3, #3

0x426a38 STP	X23, X24, [SP, #48]

0x426a3c SUB	W23, W2, W22

0x426a40 CMP	W4, W19

0x426a44 B.GE	426ea0

0x426a48 SUB	W5, W19, W4

0x426a4c MADD	W24, W23, W5, WZR

0x426a50 STR	W5, [SP, #272]

0x426a54 BL	403890

0x426a58 ORR	W21, WZR, W0

0x426a5c BL	4038c0

0x426a60 UDIV	W7, W24, W21

0x426a64 ORR	W6, WZR, W0

0x426a68 MSUB	W8, W7, W21, W24

0x426a6c CMP	W0, W8

0x426a70 B.CC	426ed0

  (317) 0x426a74 MADD	W2, W7, W6, W8

  (317) 0x426a78 ADD	W9, W7, W2

  (317) 0x426a7c STR	W9, [SP, #276]

  (317) 0x426a80 CMP	W2, W9

  (317) 0x426a84 B.CS	426ea0

  (317) 0x426a88 LDR	W12, [SP, #272]

  (317) 0x426a8c FMOV	D30, #0.2500000

  (317) 0x426a90 STP	X25, X26, [SP, #64]

  (317) 0x426a94 STP	X27, X28, [SP, #80]

  (317) 0x426a98 UDIV	W13, W2, W12

  (317) 0x426a9c LDP	X10, X11, [X20, #8]

  (317) 0x426aa0 LDR	D23, [X20]

  (317) 0x426aa4 STR	X10, [SP, #280]

  (317) 0x426aa8 STR	X11, [SP, #304]

  (317) 0x426aac LDP	X16, X17, [X20, #24]

  (317) 0x426ab0 MSUB	W14, W13, W12, W2

  (317) 0x426ab4 ADD	W15, W13, W22

  (317) 0x426ab8 SBFM	X18, X15, #0, #31

  (317) 0x426abc FMUL	D30, D23, D30

  (317) 0x426ac0 LDR	W27, [SP, #244]

  (317) 0x426ac4 STR	X16, [SP, #288]

  (317) 0x426ac8 STR	X17, [SP, #312]

  (317) 0x426acc LDP	X26, X25, [X20, #40]

  (317) 0x426ad0 DUP	V29.2D, V30.D[0]

  (317) 0x426ad4 ADD	W27, W14, W27

  (317) 0x426ad8 SUB	W1, W19, W27

  (317) 0x426adc STR	X25, [SP, #320]

  (317) 0x426ae0 LDP	X28, X30, [X20, #56]

  (317) 0x426ae4 STR	X28, [SP, #296]

  (317) 0x426ae8 STR	X30, [SP, #328]

    (318) 0x426aec CMP	W7, W1

    (318) 0x426af0 CSEL	W3, W7, W1, #9

    (318) 0x426af4 ADD	W20, W2, W3

    (318) 0x426af8 STR	W20, [SP, #140]

    (318) 0x426afc CMP	W2, W20

    (318) 0x426b00 B.CS	426e7c

    (318) 0x426b04 LDP	X0, X2, [SP, #280]

    (318) 0x426b08 LDP	X4, X23, [SP, #296]

    (318) 0x426b0c LDP	X16, X17, [SP, #312]

    (318) 0x426b10 LDR	X1, [X26]

    (318) 0x426b14 LDR	X19, [X2]

    (318) 0x426b18 LDR	X8, [X4]

    (318) 0x426b1c MADD	X22, X1, X18, XZR

    (318) 0x426b20 LDR	X5, [X0]

    (318) 0x426b24 MADD	X24, X19, X18, XZR

    (318) 0x426b28 LDR	X28, [X16]

    (318) 0x426b2c ADD	X21, X1, X22

    (318) 0x426b30 MADD	X13, X18, X8, XZR

    (318) 0x426b34 LDR	X20, [X17]

    (318) 0x426b38 ADD	X6, X19, X24

    (318) 0x426b3c MADD	X7, X18, X5, XZR

    (318) 0x426b40 LDR	X9, [X0, #16]

    (318) 0x426b44 LDR	X10, [X4, #16]

    (318) 0x426b48 MADD	X4, X18, X20, XZR

    (318) 0x426b4c LDR	X30, [SP, #328]

    (318) 0x426b50 LDR	X14, [X2, #16]

    (318) 0x426b54 MADD	X2, X18, X28, XZR

    (318) 0x426b58 LDR	X12, [X23]

    (318) 0x426b5c LDR	X11, [X23, #16]

    (318) 0x426b60 LDR	X25, [X26, #16]

    (318) 0x426b64 STP	X10, X9, [SP, #152]

    (318) 0x426b68 MADD	X15, X18, X12, XZR

    (318) 0x426b6c STP	X4, X2, [SP, #176]

    (318) 0x426b70 STP	X13, X21, [SP, #192]

    (318) 0x426b74 STP	X22, X6, [SP, #208]

    (318) 0x426b78 STP	X24, X7, [SP, #224]

    (318) 0x426b7c LDR	X1, [X30]

    (318) 0x426b80 STR	X15, [SP, #112]

    (318) 0x426b84 LDR	X0, [X30, #16]

    (318) 0x426b88 STR	X11, [SP, #144]

    (318) 0x426b8c LDR	X28, [X17, #16]

    (318) 0x426b90 MADD	X8, X18, X1, XZR

    (318) 0x426b94 LDR	X30, [X16, #16]

    (318) 0x426b98 STR	X0, [SP, #104]

    (318) 0x426b9c STR	X8, [SP, #168]

    (318) 0x426ba0 CMP	W3, #1

    (318) 0x426ba4 B.EQ	426db4

    (318) 0x426ba8 SBFM	X15, X27, #0, #31

    (318) 0x426bac UBFM	W16, W3, #1, #31

    (318) 0x426bb0 ADD	X23, X2, X15

    (318) 0x426bb4 ADD	X19, X4, X15

    (318) 0x426bb8 ADD	X20, X7, X15

    (318) 0x426bbc ADD	X7, X13, X15

    (318) 0x426bc0 LDR	X13, [SP, #112]

    (318) 0x426bc4 ADD	X2, X30, X23,LSL #3

    (318) 0x426bc8 UBFM	X5, X23, #61, #60

    (318) 0x426bcc UBFM	X12, X19, #61, #60

    (318) 0x426bd0 ADD	X4, X28, X19,LSL #3

    (318) 0x426bd4 ADD	X1, X8, X15

    (318) 0x426bd8 ADD	X23, X6, X15

    (318) 0x426bdc ADD	X10, X10, X7,LSL #3

    (318) 0x426be0 UBFM	X8, X1, #61, #60

    (318) 0x426be4 STP	X5, X12, [SP, #248]

    (318) 0x426be8 ADD	X5, X5, #8

    (318) 0x426bec ADD	X12, X12, #8

    (318) 0x426bf0 ADD	X24, X24, X15

    (318) 0x426bf4 ADD	X17, X13, X15

    (318) 0x426bf8 ADD	X22, X22, X15

    (318) 0x426bfc ADD	X6, X14, X24,LSL #3

    (318) 0x426c00 ADD	X21, X21, X15

    (318) 0x426c04 LDR	X15, [SP, #104]

    (318) 0x426c08 ADD	X11, X11, X17,LSL #3

    (318) 0x426c0c UBFM	X19, X7, #61, #60

    (318) 0x426c10 STP	X5, X12, [SP, #120]

    (318) 0x426c14 ADD	X7, X14, X23,LSL #3

    (318) 0x426c18 MOVZ	X0, #0

    (318) 0x426c1c UBFM	X24, X24, #61, #60

    (318) 0x426c20 ADD	X5, X9, X20,LSL #3

    (318) 0x426c24 UBFM	X23, X23, #61, #60

    (318) 0x426c28 UBFM	X17, X17, #61, #60

    (318) 0x426c2c ADD	X9, X25, X21,LSL #3

    (318) 0x426c30 UBFM	X20, X20, #61, #60

    (318) 0x426c34 UBFM	X21, X21, #61, #60

    (318) 0x426c38 LDR	X13, [SP, #120]

    (318) 0x426c3c STR	X8, [SP, #264]

    (318) 0x426c40 ADD	X1, X15, X1,LSL #3

    (318) 0x426c44 UBFM	X15, X16, #60, #59

    (318) 0x426c48 LDR	X8, [SP, #128]

    (318) 0x426c4c ADD	X12, X30, X13

    (318) 0x426c50 ADD	X13, X28, X8

    (318) 0x426c54 ADD	X8, X25, X22,LSL #3

    (318) 0x426c58 UBFM	X22, X22, #61, #60

    (318) 0x426c5c TBZ	W16, #0, 426ce8

    (318) 0x426c60 LDR	Q22, [X14, X24]

    (318) 0x426c64 MOVZ	X0, #16

    (318) 0x426c68 LDR	Q21, [X14, X23]

    (318) 0x426c6c LDR	Q20, [X25, X22]

    (318) 0x426c70 LDR	Q19, [X25, X21]

    (318) 0x426c74 LDR	X16, [SP, #160]

    (318) 0x426c78 FADD	V0.2D, V22.2D, V21.2D

    (318) 0x426c7c LDR	X24, [SP, #152]

    (318) 0x426c80 FADD	V1.2D, V20.2D, V19.2D

    (318) 0x426c84 LDR	X23, [SP, #120]

    (318) 0x426c88 LDR	Q18, [X16, X20]

    (318) 0x426c8c LDR	X21, [SP, #128]

    (318) 0x426c90 FADD	V2.2D, V0.2D, V1.2D

    (318) 0x426c94 LDR	X20, [SP, #256]

    (318) 0x426c98 FMUL	V3.2D, V18.2D, V29.2D

    (318) 0x426c9c LDR	X22, [SP, #144]

    (318) 0x426ca0 LDR	X16, [SP, #104]

    (318) 0x426ca4 FMUL	V4.2D, V2.2D, V3.2D

    (318) 0x426ca8 STR	Q4, [X24, X19]

    (318) 0x426cac LDR	X19, [SP, #248]

    (318) 0x426cb0 LDR	Q16, [X30, X23]

    (318) 0x426cb4 LDR	Q7, [X28, X20]

    (318) 0x426cb8 LDR	Q17, [X30, X19]

    (318) 0x426cbc LDR	Q6, [X28, X21]

    (318) 0x426cc0 LDR	Q26, [X22, X17]

    (318) 0x426cc4 FADD	V5.2D, V17.2D, V16.2D

    (318) 0x426cc8 LDR	X17, [SP, #264]

    (318) 0x426ccc FADD	V24.2D, V7.2D, V6.2D

    (318) 0x426cd0 FMUL	V27.2D, V26.2D, V29.2D

    (318) 0x426cd4 FADD	V25.2D, V5.2D, V24.2D

    (318) 0x426cd8 FMUL	V28.2D, V25.2D, V27.2D

    (318) 0x426cdc STR	Q28, [X16, X17]

    (318) 0x426ce0 CMP	X15, X0

    (318) 0x426ce4 B.EQ	426da8

      (319) 0x426ce8 LDR	Q31, [X6, X0]

      (319) 0x426cec ADD	X24, X0, #16

      (319) 0x426cf0 LDR	Q23, [X7, X0]

      (319) 0x426cf4 LDR	Q22, [X8, X0]

      (319) 0x426cf8 LDR	Q21, [X9, X0]

      (319) 0x426cfc FADD	V20.2D, V31.2D, V23.2D

      (319) 0x426d00 LDR	Q19, [X5, X0]

      (319) 0x426d04 FADD	V0.2D, V22.2D, V21.2D

      (319) 0x426d08 FMUL	V1.2D, V19.2D, V29.2D

      (319) 0x426d0c FADD	V2.2D, V20.2D, V0.2D

      (319) 0x426d10 FMUL	V18.2D, V2.2D, V1.2D

      (319) 0x426d14 STR	Q18, [X10, X0]

      (319) 0x426d18 LDR	Q3, [X2, X0]

      (319) 0x426d1c LDR	Q4, [X12, X0]

      (319) 0x426d20 LDR	Q17, [X4, X0]

      (319) 0x426d24 LDR	Q16, [X13, X0]

      (319) 0x426d28 FADD	V5.2D, V3.2D, V4.2D

      (319) 0x426d2c LDR	Q7, [X11, X0]

      (319) 0x426d30 FADD	V6.2D, V17.2D, V16.2D

      (319) 0x426d34 FMUL	V24.2D, V7.2D, V29.2D

      (319) 0x426d38 FADD	V25.2D, V5.2D, V6.2D

      (319) 0x426d3c FMUL	V26.2D, V25.2D, V24.2D

      (319) 0x426d40 STR	Q26, [X1, X0]

      (319) 0x426d44 ADD	X0, X0, #32

      (319) 0x426d48 LDR	Q27, [X6, X24]

      (319) 0x426d4c LDR	Q28, [X7, X24]

      (319) 0x426d50 LDR	Q31, [X8, X24]

      (319) 0x426d54 LDR	Q22, [X9, X24]

      (319) 0x426d58 FADD	V23.2D, V27.2D, V28.2D

      (319) 0x426d5c LDR	Q20, [X5, X24]

      (319) 0x426d60 FADD	V21.2D, V31.2D, V22.2D

      (319) 0x426d64 FMUL	V19.2D, V20.2D, V29.2D

      (319) 0x426d68 FADD	V0.2D, V23.2D, V21.2D

      (319) 0x426d6c FMUL	V1.2D, V0.2D, V19.2D

      (319) 0x426d70 STR	Q1, [X10, X24]

      (319) 0x426d74 LDR	Q2, [X2, X24]

      (319) 0x426d78 LDR	Q18, [X12, X24]

      (319) 0x426d7c LDR	Q3, [X4, X24]

      (319) 0x426d80 LDR	Q4, [X13, X24]

      (319) 0x426d84 FADD	V17.2D, V2.2D, V18.2D

      (319) 0x426d88 LDR	Q5, [X11, X24]

      (319) 0x426d8c FADD	V16.2D, V3.2D, V4.2D

      (319) 0x426d90 FMUL	V7.2D, V5.2D, V29.2D

      (319) 0x426d94 FADD	V6.2D, V17.2D, V16.2D

      (319) 0x426d98 FMUL	V24.2D, V6.2D, V7.2D

      (319) 0x426d9c STR	Q24, [X1, X24]

      (319) 0x426da0 CMP	X15, X0

      (319) 0x426da4 B.NE	426ce8

    (318) 0x426da8 TBZ	W3, #0, 426e78

    (318) 0x426dac AND	W3, W3, #1951

    (318) 0x426db0 ADD	W27, W27, W3

    (318) 0x426db4 LDR	X9, [SP, #224]

    (318) 0x426db8 SBFM	X10, X27, #0, #31

    (318) 0x426dbc ADD	W2, W27, #1

    (318) 0x426dc0 LDP	X6, X4, [SP, #192]

    (318) 0x426dc4 SBFM	X11, X2, #0, #31

    (318) 0x426dc8 LDP	X7, X5, [SP, #208]

    (318) 0x426dcc ADD	X13, X9, X10

    (318) 0x426dd0 ADD	X8, X4, X10

    (318) 0x426dd4 ADD	X19, X6, X10

    (318) 0x426dd8 LDR	X22, [SP, #232]

    (318) 0x426ddc ADD	X12, X5, X10

    (318) 0x426de0 ADD	X0, X7, X10

    (318) 0x426de4 LDR	D26, [X14, X13,LSL #3]

    (318) 0x426de8 LDR	D25, [X14, X12,LSL #3]

    (318) 0x426dec ADD	X16, X22, X10

    (318) 0x426df0 LDR	D27, [X25, X8,LSL #3]

    (318) 0x426df4 LDR	D28, [X25, X0,LSL #3]

    (318) 0x426df8 LDR	X27, [SP, #160]

    (318) 0x426dfc FADD	D31, D25, D26

    (318) 0x426e00 LDR	X1, [SP, #112]

    (318) 0x426e04 FADD	D22, D27, D28

    (318) 0x426e08 LDR	X25, [SP, #168]

    (318) 0x426e0c LDR	D20, [X27, X16,LSL #3]

    (318) 0x426e10 ADD	X20, X1, X10

    (318) 0x426e14 LDR	X15, [SP, #176]

    (318) 0x426e18 ADD	X3, X25, X10

    (318) 0x426e1c FADD	D23, D31, D22

    (318) 0x426e20 LDR	X21, [SP, #184]

    (318) 0x426e24 FMUL	D21, D30, D20

    (318) 0x426e28 ADD	X23, X15, X10

    (318) 0x426e2c ADD	X14, X15, X11

    (318) 0x426e30 ADD	X24, X21, X10

    (318) 0x426e34 LDR	X10, [SP, #152]

    (318) 0x426e38 ADD	X17, X21, X11

    (318) 0x426e3c FMUL	D19, D23, D21

    (318) 0x426e40 STR	D19, [X10, X19,LSL #3]

    (318) 0x426e44 LDR	D1, [X28, X23,LSL #3]

    (318) 0x426e48 LDR	D2, [X30, X24,LSL #3]

    (318) 0x426e4c LDR	D0, [X30, X17,LSL #3]

    (318) 0x426e50 LDR	D18, [X28, X14,LSL #3]

    (318) 0x426e54 LDR	X28, [SP, #144]

    (318) 0x426e58 FADD	D3, D1, D2

    (318) 0x426e5c LDR	X30, [SP, #104]

    (318) 0x426e60 FADD	D4, D0, D18

    (318) 0x426e64 LDR	D5, [X28, X20,LSL #3]

    (318) 0x426e68 FADD	D17, D3, D4

    (318) 0x426e6c FMUL	D16, D30, D5

    (318) 0x426e70 FMUL	D7, D17, D16

    (318) 0x426e74 STR	D7, [X30, X3,LSL #3]

    (318) 0x426e78 LDR	W2, [SP, #140]

    (318) 0x426e7c ADD	X18, X18, #1

    (318) 0x426e80 LDR	W11, [SP, #240]

    (318) 0x426e84 CMP	W11, W18

    (318) 0x426e88 B.LE	426eb4

    (318) 0x426e8c LDR	W15, [SP, #276]

    (318) 0x426e90 LDR	W27, [SP, #244]

    (318) 0x426e94 LDR	W1, [SP, #272]

    (318) 0x426e98 SUB	W7, W15, W2

    (318) 0x426e9c B	426aec

(316) 0x426ea0 LDP	X23, X24, [SP, #48]

(316) 0x426ea4 LDP	X19, X20, [SP, #16]

(316) 0x426ea8 LDP	X21, X22, [SP, #32]

(316) 0x426eac LDP	X29, X30, [SP], #336

(316) 0x426eb0 RET

  (317) 0x426eb4 LDP	X23, X24, [SP, #48]

  (317) 0x426eb8 LDP	X25, X26, [SP, #64]

  (317) 0x426ebc LDP	X27, X28, [SP, #80]

  (317) 0x426ec0 LDP	X19, X20, [SP, #16]

  (317) 0x426ec4 LDP	X21, X22, [SP, #32]

  (317) 0x426ec8 LDP	X29, X30, [SP], #336

  (317) 0x426ecc RET

  (317) 0x426ed0 ADD	W7, W7, #1

  (317) 0x426ed4 MOVZ	W8, #0

  (317) 0x426ed8 B	426a74

0x426edc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	flux_calc(global_variables&)	flux_calc.cpp:53	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 44% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #688]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W3, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 426ea4 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W3, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 426ea0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 426ed0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #688]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W3, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 426ea4 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W3, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W4, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 426ea0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W5, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W5, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W6, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W8, W7, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 426ed0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.66	3.54
▼Loop 316 - flux_calc.cpp:36-40 - exec–	0.00	0.00
▼Loop 317 - flux_calc.cpp:36-40 - exec–	0.00	0.00
▼Loop 318 - flux_calc.cpp:38-40 - exec–	0.00	0.01
○Loop 319 - flux_calc.cpp:39-40 - exec	4.66	3.51

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code