OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 3.92% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x424860 STP	X29, X30, [SP, #880]!

0x424864 ADD	X29, SP, #0

0x424868 STP	X19, X20, [SP, #16]

0x42486c ORR	X19, XZR, X0

0x424870 STP	X21, X22, [SP, #32]

0x424874 LDP	W22, W2, [X0, #128]

0x424878 LDP	W1, W0, [X0, #120]

0x42487c ADD	W3, W2, #2

0x424880 ADD	W22, W22, #1

0x424884 ADD	W4, W1, #1

0x424888 STR	W3, [SP, #136]

0x42488c STR	W4, [SP, #116]

0x424890 CMP	W22, W3

0x424894 B.GE	424c40

0x424898 LDR	W6, [SP, #136]

0x42489c ADD	W20, W0, #2

0x4248a0 STP	X23, X24, [SP, #48]

0x4248a4 LDR	W7, [SP, #116]

0x4248a8 SUB	W23, W6, W22

0x4248ac CMP	W7, W20

0x4248b0 B.GE	424bec

0x4248b4 SUB	W8, W20, W7

0x4248b8 MADD	W24, W23, W8, WZR

0x4248bc STR	W8, [SP, #120]

0x4248c0 BL	403890

0x4248c4 ORR	W21, WZR, W0

0x4248c8 BL	4038c0

0x4248cc UDIV	W9, W24, W21

0x4248d0 MSUB	W10, W9, W21, W24

0x4248d4 CMP	W0, W10

0x4248d8 B.CC	424c2c

(299) 0x4248dc MADD	W2, W9, W0, W10

(299) 0x4248e0 ADD	W11, W9, W2

(299) 0x4248e4 STR	W11, [SP, #124]

(299) 0x4248e8 CMP	W2, W11

(299) 0x4248ec B.CS	424bec

(299) 0x4248f0 LDR	W17, [SP, #120]

(299) 0x4248f4 MOVN	X13, #32784

(299) 0x4248f8 ADRP	X16,

(299) 0x4248fc FMOV	D19, #0.5000000

(299) 0x424900 FMOV	D17, #-1.0000000

(299) 0x424904 STP	X27, X28, [SP, #80]

(299) 0x424908 ADRP	X14,

(299) 0x42490c ADRP	X15,

(299) 0x424910 MOVZ	W7, #0

(299) 0x424914 FMOV	D16, X13

(299) 0x424918 UDIV	W18, W2, W17

(299) 0x42491c LDR	W27, [SP, #116]

(299) 0x424920 STP	X25, X26, [SP, #64]

(299) 0x424924 STR	D15, [SP, #96]

(299) 0x424928 LDP	D21, D22, [X19]

(299) 0x42492c LDP	D23, D18, [X19, #16]

(299) 0x424930 FMOV	D27, D16

(299) 0x424934 LDR	W30, [SP, #136]

(299) 0x424938 ADD	W26, W18, W22

(299) 0x42493c MSUB	W25, W18, W17, W2

(299) 0x424940 LDP	X22, X28, [X19, #48]

(299) 0x424944 SBFM	X5, X26, #0, #31

(299) 0x424948 FADD	D22, D22, D22

(299) 0x42494c ADD	X18, X5, #1

(299) 0x424950 ADD	W13, W25, W27

(299) 0x424954 LDP	X26, X27, [X19, #32]

(299) 0x424958 FADD	D23, D23, D23

(299) 0x42495c SUB	W11, W20, W13

(299) 0x424960 CMP	W9, W11

(299) 0x424964 CSEL	W3, W9, W11, #9

(299) 0x424968 STR	X22, [SP, #128]

(299) 0x42496c LDP	X24, X25, [X19, #64]

(299) 0x424970 LDP	X22, X23, [X19, #80]

(299) 0x424974 LDP	X20, X21, [X19, #96]

(299) 0x424978 STR	X19, [SP, #136]

(299) 0x42497c ADD	W19, W2, W3

(299) 0x424980 LDR	D20, [X16, #1136]

(299) 0x424984 ORR	X16, XZR, X18

(299) 0x424988 LDR	D25, [X14, #976]

(299) 0x42498c LDR	D26, [X15, #1120]

(299) 0x424990 CMP	W2, W19

(299) 0x424994 B.CS	424ba0

(299) 0x424998 HINT	#0

(299) 0x42499c HINT	#0

  (301) 0x4249a0 SBFM	X0, X13, #0, #31

  (301) 0x4249a4 SUB	W4, W3, #1

  (301) 0x4249a8 LDR	X6, [X20]

  (301) 0x4249ac ADD	X2, X0, #1

  (301) 0x4249b0 ADD	W1, W13, #1

  (301) 0x4249b4 ADD	X7, X4, X2

  (301) 0x4249b8 SBFM	X1, X1, #0, #31

  (301) 0x4249bc LDR	X9, [X22]

  (301) 0x4249c0 LDR	X8, [X21]

  (301) 0x4249c4 UBFM	X10, X6, #61, #60

  (301) 0x4249c8 LDR	X14, [X23]

  (301) 0x4249cc MADD	X12, X5, X9, XZR

  (301) 0x4249d0 LDR	X11, [X22, #16]

  (301) 0x4249d4 UBFM	X17, X8, #61, #60

  (301) 0x4249d8 LDR	X6, [X24]

  (301) 0x4249dc MADD	X4, X5, X14, XZR

  (301) 0x4249e0 LDR	X15, [X23, #16]

  (301) 0x4249e4 ADD	X13, X11, X12,LSL #3

  (301) 0x4249e8 LDR	X12, [X25]

  (301) 0x4249ec MADD	X9, X5, X6, XZR

  (301) 0x4249f0 LDR	X3, [X20, #16]

  (301) 0x4249f4 ADD	X14, X15, X4,LSL #3

  (301) 0x4249f8 LDR	X8, [X24, #16]

  (301) 0x4249fc MADD	X4, X5, X12, XZR

  (301) 0x424a00 LDR	X15, [X25, #16]

  (301) 0x424a04 LDR	X6, [X26, #16]

  (301) 0x424a08 ADD	X11, X8, X9,LSL #3

  (301) 0x424a0c MADD	X9, X5, X10, X3

  (301) 0x424a10 MADD	X3, X16, X10, X3

  (301) 0x424a14 LDR	X10, [X26]

  (301) 0x424a18 ADD	X12, X15, X4,LSL #3

  (301) 0x424a1c LDR	X15, [X21, #16]

  (301) 0x424a20 MADD	X8, X5, X10, XZR

  (301) 0x424a24 LDR	X10, [X27]

  (301) 0x424a28 ADD	X4, X6, X8,LSL #3

  (301) 0x424a2c MADD	X8, X5, X17, X15

  (301) 0x424a30 MADD	X6, X16, X17, X15

  (301) 0x424a34 LDR	X15, [X28, #8]

  (301) 0x424a38 UBFM	X10, X10, #61, #60

  (301) 0x424a3c LDR	X17, [X27, #16]

  (301) 0x424a40 LDR	D24, [X15, X5,LSL #3]

  (301) 0x424a44 MADD	X5, X5, X10, X17

  (301) 0x424a48 MADD	X17, X16, X10, X17

  (301) 0x424a4c LDR	X10, [SP, #128]

  (301) 0x424a50 LDR	X15, [X10, #8]

  (301) 0x424a54 B	424a5c

    (300) 0x424a58 ADD	X2, X2, #1

    (300) 0x424a5c LDR	D29, [X9, X0,LSL #3]

    (300) 0x424a60 FMOV	D7, D26

    (300) 0x424a64 LDR	D15, [X3, X0,LSL #3]

    (300) 0x424a68 LDR	D1, [X3, X1,LSL #3]

    (300) 0x424a6c LDR	D31, [X9, X1,LSL #3]

    (300) 0x424a70 LDR	D30, [X8, X0,LSL #3]

    (300) 0x424a74 FADD	D0, D29, D15

    (300) 0x424a78 LDR	D28, [X8, X1,LSL #3]

    (300) 0x424a7c LDR	D3, [X6, X1,LSL #3]

    (300) 0x424a80 FADD	D31, D31, D1

    (300) 0x424a84 LDR	D6, [X6, X0,LSL #3]

    (300) 0x424a88 LDR	D4, [X4, X0,LSL #3]

    (300) 0x424a8c FADD	D2, D30, D28

    (300) 0x424a90 LDR	D15, [X4, X1,LSL #3]

    (300) 0x424a94 LDR	D5, [X5, X0,LSL #3]

    (300) 0x424a98 FADD	D6, D6, D3

    (300) 0x424a9c LDR	D28, [X17, X0,LSL #3]

    (300) 0x424aa0 FMUL	D29, D0, D4

    (300) 0x424aa4 FMUL	D4, D31, D15

    (300) 0x424aa8 LDR	D1, [X13, X0,LSL #3]

    (300) 0x424aac FMUL	D30, D2, D5

    (300) 0x424ab0 LDR	D31, [X15, X0,LSL #3]

    (300) 0x424ab4 FMINNM	D15, D24, D31

    (300) 0x424ab8 FMUL	D6, D6, D28

    (300) 0x424abc FABS	D2, D29

    (300) 0x424ac0 LDR	D0, [X12, X0,LSL #3]

    (300) 0x424ac4 FABS	D31, D4

    (300) 0x424ac8 FMAXNM	D2, D2, D31

    (300) 0x424acc FADD	D1, D1, D1

    (300) 0x424ad0 LDR	D3, [X11, X0,LSL #3]

    (300) 0x424ad4 FADD	D5, D29, D30

    (300) 0x424ad8 FMUL	D29, D15, D21

    (300) 0x424adc LDR	D28, [X14, X0,LSL #3]

    (300) 0x424ae0 FABS	D30, D30

    (300) 0x424ae4 FADD	D31, D4, D6

    (300) 0x424ae8 FABS	D6, D6

    (300) 0x424aec FMAXNM	D30, D30, D6

    (300) 0x424af0 FDIV	D1, D1, D0

    (300) 0x424af4 FMUL	D4, D22, D3

    (300) 0x424af8 FMUL	D0, D3, D25

    (300) 0x424afc FMAXNM	D2, D2, D0

    (300) 0x424b00 FMAXNM	D30, D30, D0

    (300) 0x424b04 FMUL	D15, D23, D3

    (300) 0x424b08 FSUB	D5, D31, S5

    (300) 0x424b0c FDIV	D4, D4, D2

    (300) 0x424b10 FMUL	D31, D5, D19

    (300) 0x424b14 FDIV	D15, D15, D30

    (300) 0x424b18 FMINNM	D6, D4, D15

    (300) 0x424b1c FMADD	D28, D28, D28, D1

    (300) 0x424b20 FDIV	D3, D31, D3

    (300) 0x424b24 FSQRT	D1, D28

    (300) 0x424b28 FMAXNM	D0, D1, D25

    (300) 0x424b2c FDIV	D29, D29, D0

    (300) 0x424b30 FMINNM	D2, D29, D26

    (300) 0x424b34 FCMPE	D3, D20

    (300) 0x424b38 B.GE	424b44

    (300) 0x424b3c FDIV	D7, D17, D3

    (300) 0x424b40 FMUL	D7, D7, D18

    (300) 0x424b44 FMINNM	D30, D2, D7

    (300) 0x424b48 ADD	X1, X1, #1

    (300) 0x424b4c FMINNM	D5, D30, D6

    (300) 0x424b50 ORR	X0, XZR, X2

    (300) 0x424b54 FMINNM	D27, D27, D5

    (300) 0x424b58 CMP	X7, X2

    (300) 0x424b5c B.NE	424a58

  (301) 0x424b60 MOVZ	W7, #1

  (301) 0x424b64 ADD	X16, X16, #1

  (301) 0x424b68 ORR	X5, XZR, X18

  (301) 0x424b6c CMP	W30, W18

  (301) 0x424b70 B.LE	424bc0

  (301) 0x424b74 LDR	W14, [SP, #124]

  (301) 0x424b78 ORR	W2, WZR, W19

  (301) 0x424b7c ADD	X18, X18, #1

  (301) 0x424b80 LDR	W11, [SP, #120]

  (301) 0x424b84 LDR	W13, [SP, #116]

  (301) 0x424b88 SUB	W9, W14, W19

  (301) 0x424b8c CMP	W9, W11

  (301) 0x424b90 CSEL	W3, W9, W11, #9

  (301) 0x424b94 ADD	W19, W2, W3

  (301) 0x424b98 CMP	W2, W19

  (301) 0x424b9c B.CC	4249a0

  (302) 0x424ba0 ORR	W19, WZR, W2

  (302) 0x424ba4 ADD	X16, X16, #1

  (302) 0x424ba8 ORR	X5, XZR, X18

  (302) 0x424bac CMP	W30, W18

  (302) 0x424bb0 B.GT	424b74

(299) 0x424bb4 HINT	#0

(299) 0x424bb8 HINT	#0

(299) 0x424bbc HINT	#0

(299) 0x424bc0 CMP	W7, #0

(299) 0x424bc4 MOVN	X30, #32784

(299) 0x424bc8 LDR	D15, [SP, #96]

(299) 0x424bcc LDP	X23, X24, [SP, #48]

(299) 0x424bd0 FCSEL	D19, D16, D27, #0

(299) 0x424bd4 FMOV	D25, X30

(299) 0x424bd8 FMINNM	D17, D19, D25

(299) 0x424bdc LDR	X19, [SP, #136]

(299) 0x424be0 LDP	X25, X26, [SP, #64]

(299) 0x424be4 LDP	X27, X28, [SP, #80]

(299) 0x424be8 B	424bf8

(299) 0x424bec MOVN	X12, #32784

(299) 0x424bf0 LDP	X23, X24, [SP, #48]

(299) 0x424bf4 FMOV	D17, X12

(299) 0x424bf8 ADD	X21, X19, #112

(299) 0x424bfc LDR	X1, [X21]

  (298) 0x424c00 FMOV	D16, X1

  (298) 0x424c04 ORR	X22, XZR, X1

  (298) 0x424c08 FMINNM	D26, D17, D16

  (298) 0x424c0c FMOV	X20, D26

  (298) 0x424c10 CAS	X22, X20, [X21]

  (298) 0x424c14 CMP	X1, X22

  (298) 0x424c18 B.NE	424c38

(299) 0x424c1c LDP	X19, X20, [SP, #16]

(299) 0x424c20 LDP	X21, X22, [SP, #32]

(299) 0x424c24 LDP	X29, X30, [SP], #144

(299) 0x424c28 RET

(299) 0x424c2c ADD	W9, W9, #1

(299) 0x424c30 MOVZ	W10, #0

(299) 0x424c34 B	4248dc

  (298) 0x424c38 ORR	X1, XZR, X22

  (298) 0x424c3c B	424c00

0x424c40 MOVN	X5, #32784

0x424c44 FMOV	D17, X5

0x424c48 B	424bf8

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	calc_dt_kernel(int, int, int, [...]	calc_dt.cpp:83	exec
○	calc_dt(global_variables&, int[...]	calc_dt.cpp:131	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:80	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 42% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.25	3.08	3.17	3.17	3.17	3.17	0.25	0.25	0.25	0.25	3.83	3.50	3.67	3.50	3.50
cycles	3.00	3.00	3.25	3.08	3.17	3.17	3.17	3.17	0.25	0.25	0.25	0.25	3.83	3.50	3.67	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	4.25
Overall L1	5.00-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W4, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 424c40 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W20, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR W7, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W23, W6, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W7, W20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 424bec <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W8, W20, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W8, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W9, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W10, W9, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 424c2c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X5, #32784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMOV D17, X5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 424bf8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.25	3.08	3.17	3.17	3.17	3.17	0.25	0.25	0.25	0.25	3.83	3.50	3.67	3.50	3.50
cycles	3.00	3.00	3.25	3.08	3.17	3.17	3.17	3.17	0.25	0.25	0.25	0.25	3.83	3.50	3.67	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	4.25
Overall L1	5.00-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W4, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 424c40 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W20, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR W7, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W23, W6, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W7, W20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 424bec <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W8, W20, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W23, W8, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403890 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4038c0 <@plt_start@+0x230>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W9, W24, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W10, W9, W21, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 424c2c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X5, #32784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMOV D17, X5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 424bf8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	3.92	2.97
▼Loop 299 - calc_dt.cpp:49-75 - exec–	0.00	0.00
▼Loop 301 - calc_dt.cpp:51-75 - exec–	0.00	0.01
○Loop 300 - calc_dt.cpp:52-75 - exec	3.91	2.95
○Loop 302 - calc_dt.cpp:75-75 - exec	0.00	0.00
○Loop 298 - calc_dt.cpp:49-49 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code