OV - exec - Loop 738

	Loop Id: 738	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage: 3.20%

  (739) 0x43cab4 ADRP	X0,

  (739) 0x43cab8 ADD	X0, X0, #3200

  (739) 0x43cabc ORR	W1, WZR, W26

  (739) 0x43cac0 BL	403400

  (739) 0x43cac4 LDP	X20, X19, [SP, #256]

  (739) 0x43cac8 LDP	X22, X21, [SP, #240]

  (739) 0x43cacc LDP	X24, X23, [SP, #224]

  (739) 0x43cad0 LDP	X26, X25, [SP, #208]

  (739) 0x43cad4 LDP	X28, X27, [SP, #192]

  (739) 0x43cad8 LDP	X29, X30, [SP, #176]

  (739) 0x43cadc ADD	SP, SP, #272

  (739) 0x43cae0 RET

  (739) 0x43cae4 LDP	X1, X18, [X29, #120]

  (739) 0x43cae8 LDP	X13, X15, [X29, #104]

  (739) 0x43caec LDR	X12, [X29, #96]

  (739) 0x43caf0 ADD	X27, X17, #1

  (739) 0x43caf4 LDR	X8, [X21, #16]

  (739) 0x43caf8 LDR	X9, [X21]

  (739) 0x43cafc LDR	X10, [X20, #16]

  (739) 0x43cb00 LDR	X11, [X20]

  (739) 0x43cb04 LDR	X17, [X18, #16]

  (739) 0x43cb08 LDR	X13, [X13, #8]

  (739) 0x43cb0c LDR	X12, [X12, #8]

  (739) 0x43cb10 LDR	X14, [X15, #16]

  (739) 0x43cb14 LDR	X15, [X15]

  (739) 0x43cb18 LDR	X21, [X1, #16]

  (739) 0x43cb1c LDR	X1, [X1]

  (739) 0x43cb20 LDR	X16, [X18]

  (739) 0x43cb24 ADD	X20, X13, #16

  (739) 0x43cb28 STP	X16, X17, [X29, #968]

  (739) 0x43cb2c SUB	X16, X27, X0

  (739) 0x43cb30 CMP	X16, #2

  (739) 0x43cb34 B.CS	43cb40

  (739) 0x43cb38 ORR	X3, XZR, X0

  (739) 0x43cb3c B	43cf0c

0x43cb40 MOVZ	X17, #35260

0x43cb44 STUR	X13, [X29, #448]

0x43cb48 AND	X13, X16, #8127

0x43cb4c FMOV	V0.2D, #0.5000000

0x43cb50 STR	X27, [SP, #24]

0x43cb54 ORR	X6, XZR, XZR

0x43cb58 MOVK	X17, #38872

0x43cb5c STUR	X13, [X29, #440]

0x43cb60 ADD	X3, X0, X13

0x43cb64 SUB	W13, WZR, W25

0x43cb68 STR	W26, [SP, #36]

0x43cb6c MOVK	X17, #53938

0x43cb70 STR	W13, [SP, #60]

0x43cb74 ADD	W13, W24, W0

0x43cb78 STR	X16, [SP, #16]

0x43cb7c MOVK	X17, #15516

0x43cb80 STP	X24, X13, [SP, #40]

0x43cb84 STUR	X25, [X29, #432]

0x43cb88 DUP	V1.2D, X17

0x43cb8c STUR	W23, [X29, #428]

0x43cb90 STP	X1, X21, [SP, #72]

0x43cb94 STR	X0, [SP, #64]

0x43cb98 B	43cc48

0x43cba0 FCMLT	V17.2D, V4.2D, #0

0x43cba4 FABS	V4.2D, V4.2D

0x43cba8 FABS	V6.2D, V6.2D

0x43cbac LDP	X1, X21, [SP, #72]

0x43cbb0 LDUR	W23, [X29, #428]

0x43cbb4 LDP	X25, X13, [X29, #944]

0x43cbb8 ADD	X6, X6, #2

0x43cbbc FMAXNM	V4.2D, V4.2D, V1.2D

0x43cbc0 FMAXNM	V6.2D, V6.2D, V1.2D

0x43cbc4 LDR	X0, [SP, #64]

0x43cbc8 FNEG	V18.2D, V4.2D

0x43cbcc MADD	X18, X1, X28, XZR

0x43cbd0 MADD	X16, X1, X27, XZR

0x43cbd4 BIT	V4.16B, V18.16B, V17.16B

0x43cbd8 FNEG	V18.2D, V6.2D

0x43cbdc ADD	X18, X21, X18,LSL #3

0x43cbe0 ADD	X16, X21, X16,LSL #3

0x43cbe4 ADD	X17, X18, X17,LSL #3

0x43cbe8 FCMLT	V17.2D, V4.2D, #0

0x43cbec BIT	V6.16B, V18.16B, V17.16B

0x43cbf0 FMUL	V17.2D, V4.2D, V4.2D

0x43cbf4 FMLA	V17.2D, V6.2D, V6.2D

0x43cbf8 FSQRT	V17.2D, V17.2D

0x43cbfc FMUL	V2.2D, V17.2D, V2.2D

0x43cc00 FMUL	V3.2D, V17.2D, V3.2D

0x43cc04 FDIV	V2.2D, V2.2D, V4.2D

0x43cc08 FDIV	V3.2D, V3.2D, V6.2D

0x43cc0c FABS	V2.2D, V2.2D

0x43cc10 FABS	V3.2D, V3.2D

0x43cc14 FMINNM	V2.2D, V2.2D, V3.2D

0x43cc18 FADD	V3.2D, V16.2D, V16.2D

0x43cc1c FMUL	V2.2D, V2.2D, V5.2D

0x43cc20 FMUL	V2.2D, V2.2D, V2.2D

0x43cc24 FMUL	V2.2D, V2.2D, V3.2D

0x43cc28 USHLL	V3.2D, V7.2S, #32

0x43cc2c SHL	V3.2D, V3.2D, #1

0x43cc30 CMLT	V3.2D, V3.2D, #0

0x43cc34 AND	V2.16B, V2.16B, V3.16B

0x43cc38 STR	D2, [X16, X26,SXTW #3]

0x43cc3c ST1	{V2.D[1]}, [X17]

0x43cc40 CMP	X13, X6

0x43cc44 B.EQ	43cef0

0x43cc48 ADD	X17, X0, X6

0x43cc4c LDR	X13, [SP, #48]

0x43cc50 ORR	W1, WZR, W22

0x43cc54 SDIV	X19, X17, X25

0x43cc58 ADD	X18, X17, #1

0x43cc5c ADD	W17, W13, W6

0x43cc60 LDR	W13, [SP, #60]

0x43cc64 ADD	W5, W23, W19

0x43cc68 SDIV	X21, X18, X25

0x43cc6c SBFM	X27, X5, #0, #31

0x43cc70 ADD	W25, W23, W21

0x43cc74 MADD	X18, X9, X27, XZR

0x43cc78 SBFM	X28, X25, #0, #31

0x43cc7c MADD	X4, X9, X28, XZR

0x43cc80 ADD	X22, X8, X18,LSL #3

0x43cc84 ADD	X23, X8, X4,LSL #3

0x43cc88 ADD	W4, W25, #1

0x43cc8c SBFM	X25, X25, #61, #31

0x43cc90 MADD	W24, W13, W19, W17

0x43cc94 ADD	W7, W24, #2

0x43cc98 LDR	D4, [X22, X7,SXTW #3]

0x43cc9c ADD	W26, W24, #1

0x43cca0 LDR	D6, [X22, X26,SXTW #3]

0x43cca4 LDR	D2, [X12, X26,SXTW #3]

0x43cca8 LDR	D22, [X12, X7,SXTW #3]

0x43ccac MADD	W2, W13, W21, W17

0x43ccb0 ADD	W17, W2, #3

0x43ccb4 SBFM	X17, X17, #61, #31

0x43ccb8 ORR	X13, XZR, X20

0x43ccbc LDR	D25, [X13, X5,SXTW #3]

0x43ccc0 ADD	X18, X23, X17

0x43ccc4 LD1	{V4.D[1]}, [X18]

0x43ccc8 ADD	W18, W5, #1

0x43cccc SBFM	X20, X18, #0, #31

0x43ccd0 SBFM	X18, X4, #0, #31

0x43ccd4 MADD	X4, X9, X20, XZR

0x43ccd8 MADD	X30, X9, X18, XZR

0x43ccdc ADD	X16, X8, X4,LSL #3

0x43cce0 ADD	X0, X8, X30,LSL #3

0x43cce4 ADD	W30, W2, #2

0x43cce8 LDR	D5, [X16, X7,SXTW #3]

0x43ccec LDR	D7, [X16, X26,SXTW #3]

0x43ccf0 MADD	X16, X11, X20, XZR

0x43ccf4 ADD	X4, X0, X17

0x43ccf8 ADD	X16, X10, X16,LSL #3

0x43ccfc LDR	D17, [X16, X7,SXTW #3]

0x43cd00 LDR	D16, [X16, X26,SXTW #3]

0x43cd04 MADD	X16, X11, X27, XZR

0x43cd08 ADD	X16, X10, X16,LSL #3

0x43cd0c LDR	D19, [X16, X7,SXTW #3]

0x43cd10 LDR	D18, [X16, X26,SXTW #3]

0x43cd14 LD1	{V5.D[1]}, [X4]

0x43cd18 SBFM	X4, X30, #61, #31

0x43cd1c ADD	X0, X0, X4

0x43cd20 ADD	X22, X23, X4

0x43cd24 LD1	{V7.D[1]}, [X0]

0x43cd28 MADD	X0, X11, X18, XZR

0x43cd2c LD1	{V6.D[1]}, [X22]

0x43cd30 ADD	X0, X10, X0,LSL #3

0x43cd34 ADD	X22, X0, X4

0x43cd38 ADD	X0, X0, X17

0x43cd3c LD1	{V17.D[1]}, [X0]

0x43cd40 MADD	X0, X11, X28, XZR

0x43cd44 LD1	{V16.D[1]}, [X22]

0x43cd48 ADD	X0, X10, X0,LSL #3

0x43cd4c FADD	V26.2D, V5.2D, V4.2D

0x43cd50 ADD	X16, X0, X17

0x43cd54 ADD	X22, X0, X4

0x43cd58 MADD	X0, X15, X28, XZR

0x43cd5c LD1	{V19.D[1]}, [X16]

0x43cd60 ADD	X16, X12, X4

0x43cd64 LD1	{V18.D[1]}, [X22]

0x43cd68 FADD	V4.2D, V4.2D, V6.2D

0x43cd6c FADD	V27.2D, V6.2D, V7.2D

0x43cd70 ORR	W22, WZR, W1

0x43cd74 ADD	X0, X14, X0,LSL #3

0x43cd78 LD1	{V2.D[1]}, [X16]

0x43cd7c LDUR	X16, [X29, #448]

0x43cd80 FSUB	V4.2D, V5.2D, V4.2D

0x43cd84 FSUB	V26.2D, V26.2D, V27.2D

0x43cd88 FADD	V4.2D, V4.2D, V7.2D

0x43cd8c FADD	V27.2D, V17.2D, V16.2D

0x43cd90 LDR	D3, [X16, X5,SXTW #3]

0x43cd94 ADD	X16, X16, X25

0x43cd98 FMUL	V4.2D, V4.2D, V0.2D

0x43cd9c FADD	V5.2D, V16.2D, V18.2D

0x43cda0 FADD	V28.2D, V18.2D, V19.2D

0x43cda4 FMUL	V18.2D, V26.2D, V0.2D

0x43cda8 FMUL	V7.2D, V2.2D, V26.2D

0x43cdac FSUB	V5.2D, V17.2D, V5.2D

0x43cdb0 FSUB	V27.2D, V27.2D, V28.2D

0x43cdb4 LD1	{V3.D[1]}, [X16]

0x43cdb8 MADD	X16, X15, X27, XZR

0x43cdbc FADD	V5.2D, V5.2D, V19.2D

0x43cdc0 FMUL	V19.2D, V27.2D, V0.2D

0x43cdc4 ADD	X16, X14, X16,LSL #3

0x43cdc8 FMUL	V5.2D, V5.2D, V0.2D

0x43cdcc LDR	D21, [X16, X7,SXTW #3]

0x43cdd0 LDR	D20, [X16, X24,SXTW #3]

0x43cdd4 ADD	X16, X0, X17

0x43cdd8 FDIV	V5.2D, V5.2D, V2.2D

0x43cddc FDIV	V4.2D, V4.2D, V3.2D

0x43cde0 FMLA	V7.2D, V3.2D, V27.2D

0x43cde4 LD1	{V21.D[1]}, [X16]

0x43cde8 ADD	W16, W2, #1

0x43cdec ADD	X16, X0, W16,SXTW #3

0x43cdf0 FCMLT	V7.2D, V7.2D, #0

0x43cdf4 LD1	{V20.D[1]}, [X16]

0x43cdf8 ADD	X16, X12, X17

0x43cdfc ADD	W17, W1, W19

0x43ce00 LD1	{V22.D[1]}, [X16]

0x43ce04 MADD	X16, X15, X20, XZR

0x43ce08 SBFM	X17, X17, #0, #31

0x43ce0c ORR	X20, XZR, X13

0x43ce10 MADD	X17, X15, X17, XZR

0x43ce14 ADD	X16, X14, X16,LSL #3

0x43ce18 LDR	D23, [X16, X26,SXTW #3]

0x43ce1c MADD	X16, X15, X18, XZR

0x43ce20 ADD	X17, X14, X17,LSL #3

0x43ce24 LDR	D24, [X17, X26,SXTW #3]

0x43ce28 ADD	X16, X14, X16,LSL #3

0x43ce2c ADD	X16, X16, X4

0x43ce30 FADD	V6.2D, V22.2D, V2.2D

0x43ce34 FADD	V5.2D, V4.2D, V5.2D

0x43ce38 FSUB	V4.2D, V21.2D, V20.2D

0x43ce3c LD1	{V23.D[1]}, [X16]

0x43ce40 ADD	W16, W1, W21

0x43ce44 SBFM	X16, X16, #0, #31

0x43ce48 FDIV	V4.2D, V4.2D, V6.2D

0x43ce4c MADD	X16, X15, X16, XZR

0x43ce50 ADD	X16, X14, X16,LSL #3

0x43ce54 ADD	X16, X16, X4

0x43ce58 LD1	{V24.D[1]}, [X16]

0x43ce5c ADD	X16, X13, X25

0x43ce60 LD1	{V25.D[1]}, [X16]

0x43ce64 FSUB	V6.2D, V23.2D, V24.2D

0x43ce68 FADD	V16.2D, V25.2D, V3.2D

0x43ce6c FDIV	V6.2D, V6.2D, V16.2D

0x43ce70 FMUL	V16.2D, V4.2D, V4.2D

0x43ce74 FMUL	V18.2D, V18.2D, V16.2D

0x43ce78 FDIV	V18.2D, V18.2D, V2.2D

0x43ce7c FMUL	V17.2D, V6.2D, V6.2D

0x43ce80 FMUL	V20.2D, V4.2D, V6.2D

0x43ce84 FMUL	V19.2D, V19.2D, V17.2D

0x43ce88 FADD	V16.2D, V17.2D, V16.2D

0x43ce8c FMAXNM	V16.2D, V16.2D, V1.2D

0x43ce90 FDIV	V19.2D, V19.2D, V3.2D

0x43ce94 FMLA	V18.2D, V20.2D, V5.2D

0x43ce98 FADD	V5.2D, V18.2D, V19.2D

0x43ce9c FDIV	V5.2D, V5.2D, V16.2D

0x43cea0 FCMLE	V16.2D, V5.2D, #0

0x43cea4 AND	V7.16B, V16.16B, V7.16B

0x43cea8 XTN	V7.2S, V7.2D

0x43ceac FMOV	W16, S7

0x43ceb0 TBZ	W16, #0, 43cec8

0x43ceb4 LDUR	X13, [X29, #456]

0x43ceb8 MADD	X16, X13, X27, XZR

0x43cebc LDUR	X13, [X29, #464]

0x43cec0 ADD	X16, X13, X16,LSL #3

0x43cec4 LDR	D16, [X16, X26,SXTW #3]

0x43cec8 MOV	W16, V7.S[1]

0x43cecc SBFM	X17, X30, #0, #31

0x43ced0 TBZ	W16, #0, 43cba0

0x43ced4 LDUR	X13, [X29, #456]

0x43ced8 MADD	X16, X13, X28, XZR

0x43cedc LDUR	X13, [X29, #464]

0x43cee0 ADD	X16, X13, X16,LSL #3

0x43cee4 ADD	X16, X16, X17,LSL #3

0x43cee8 LD1	{V16.D[1]}, [X16]

0x43ceec B	43cba0

0x43cef0 LDP	X13, X27, [SP, #16]

0x43cef4 LDUR	X16, [X29, #440]

0x43cef8 LDR	X24, [SP, #40]

0x43cefc LDR	W26, [SP, #36]

0x43cf00 CMP	X13, X16

0x43cf04 LDUR	X13, [X29, #448]

0x43cf08 B.EQ	43cab4

  (739) 0x43cf0c ADRP	X16,

  (739) 0x43cf10 FMOV	D0, #0.5000000

  (739) 0x43cf14 SUB	W4, WZR, W25

  (739) 0x43cf18 LDR	D1, [X16, #2032]

  (739) 0x43cf1c B	43cf38

    (740) 0x43cf20 MADD	X16, X1, X17, XZR

    (740) 0x43cf24 ADD	X3, X3, #1

    (740) 0x43cf28 ADD	X16, X21, X16,LSL #3

    (740) 0x43cf2c STR	D17, [X16, X2,SXTW #3]

    (740) 0x43cf30 CMP	X27, X3

    (740) 0x43cf34 B.EQ	43cab4

    (740) 0x43cf38 SDIV	X16, X3, X25

    (740) 0x43cf3c ADD	W17, W24, W3

    (740) 0x43cf40 ADD	W18, W23, W16

    (740) 0x43cf44 MADD	W0, W4, W16, W17

    (740) 0x43cf48 ADD	W16, W22, W16

    (740) 0x43cf4c SBFM	X17, X18, #0, #31

    (740) 0x43cf50 ADD	W7, W18, #1

    (740) 0x43cf54 SBFM	X16, X16, #0, #31

    (740) 0x43cf58 MADD	X6, X9, X17, XZR

    (740) 0x43cf5c ADD	W2, W0, #1

    (740) 0x43cf60 ADD	W5, W0, #2

    (740) 0x43cf64 SBFM	X7, X7, #0, #31

    (740) 0x43cf68 MADD	X16, X15, X16, XZR

    (740) 0x43cf6c MADD	X19, X9, X7, XZR

    (740) 0x43cf70 ADD	X6, X8, X6,LSL #3

    (740) 0x43cf74 ADD	X16, X14, X16,LSL #3

    (740) 0x43cf78 LDR	D6, [X6, X5,SXTW #3]

    (740) 0x43cf7c LDR	D16, [X6, X2,SXTW #3]

    (740) 0x43cf80 MADD	X6, X11, X7, XZR

    (740) 0x43cf84 ADD	X19, X8, X19,LSL #3

    (740) 0x43cf88 LDR	D7, [X19, X5,SXTW #3]

    (740) 0x43cf8c LDR	D17, [X19, X2,SXTW #3]

    (740) 0x43cf90 ADD	X6, X10, X6,LSL #3

    (740) 0x43cf94 LDR	D18, [X6, X2,SXTW #3]

    (740) 0x43cf98 LDR	D19, [X6, X5,SXTW #3]

    (740) 0x43cf9c MADD	X6, X11, X17, XZR

    (740) 0x43cfa0 ADD	X6, X10, X6,LSL #3

    (740) 0x43cfa4 LDR	D20, [X6, X2,SXTW #3]

    (740) 0x43cfa8 LDR	D21, [X6, X5,SXTW #3]

    (740) 0x43cfac MADD	X6, X15, X17, XZR

    (740) 0x43cfb0 FADD	D2, D7, D6

    (740) 0x43cfb4 FADD	D6, D6, D16

    (740) 0x43cfb8 FADD	D3, D16, D17

    (740) 0x43cfbc ADD	X6, X14, X6,LSL #3

    (740) 0x43cfc0 FSUB	D6, D7, S6

    (740) 0x43cfc4 FSUB	D4, D2, S3

    (740) 0x43cfc8 FADD	D2, D19, D18

    (740) 0x43cfcc LDR	D16, [X6, X0,SXTW #3]

    (740) 0x43cfd0 MADD	X0, X15, X7, XZR

    (740) 0x43cfd4 FADD	D6, D6, D17

    (740) 0x43cfd8 ADD	X0, X14, X0,LSL #3

    (740) 0x43cfdc LDR	D17, [X16, X2,SXTW #3]

    (740) 0x43cfe0 FADD	D7, D18, D20

    (740) 0x43cfe4 FADD	D3, D20, D21

    (740) 0x43cfe8 FMUL	D6, D6, D0

    (740) 0x43cfec FSUB	D7, D19, S7

    (740) 0x43cff0 FSUB	D5, D2, S3

    (740) 0x43cff4 LDR	D3, [X12, X2,SXTW #3]

    (740) 0x43cff8 LDR	D2, [X13, X18,SXTW #3]

    (740) 0x43cffc FMUL	D19, D4, D0

    (740) 0x43d000 FADD	D7, D7, D21

    (740) 0x43d004 FMUL	D20, D5, D0

    (740) 0x43d008 FMUL	D7, D7, D0

    (740) 0x43d00c FDIV	D6, D6, D2

    (740) 0x43d010 FDIV	D7, D7, D3

    (740) 0x43d014 FADD	D7, D6, D7

    (740) 0x43d018 LDR	D6, [X6, X5,SXTW #3]

    (740) 0x43d01c FSUB	D6, D6, S16

    (740) 0x43d020 LDR	D16, [X12, X5,SXTW #3]

    (740) 0x43d024 FADD	D16, D16, D3

    (740) 0x43d028 FDIV	D6, D6, D16

    (740) 0x43d02c LDR	D16, [X0, X2,SXTW #3]

    (740) 0x43d030 FSUB	D16, D16, S17

    (740) 0x43d034 LDR	D17, [X20, X18,SXTW #3]

    (740) 0x43d038 FADD	D17, D17, D2

    (740) 0x43d03c FDIV	D16, D16, D17

    (740) 0x43d040 FMUL	D17, D6, D6

    (740) 0x43d044 FMUL	D19, D19, D17

    (740) 0x43d048 FDIV	D19, D19, D3

    (740) 0x43d04c FMUL	D18, D16, D16

    (740) 0x43d050 FMUL	D21, D6, D16

    (740) 0x43d054 FMUL	D20, D20, D18

    (740) 0x43d058 FADD	D17, D18, D17

    (740) 0x43d05c FMAXNM	D17, D17, D1

    (740) 0x43d060 FDIV	D20, D20, D2

    (740) 0x43d064 FMADD	D7, D21, D7, D19

    (740) 0x43d068 FADD	D7, D7, D20

    (740) 0x43d06c FDIV	D7, D7, D17

    (740) 0x43d070 MOVI	D17, #0

    (740) 0x43d074 FCMP	D7, #0

    (740) 0x43d078 B.GT	43cf20

    (740) 0x43d07c FMUL	D4, D3, D4

    (740) 0x43d080 FMADD	D4, D2, D5, D4

    (740) 0x43d084 FCMP	D4, #0

    (740) 0x43d088 B.GE	43cf20

    (740) 0x43d08c FABS	D4, D6

    (740) 0x43d090 FCMP	D6, #0

    (740) 0x43d094 LDP	X16, X18, [X29, #968]

    (740) 0x43d098 FMAXNM	D4, D4, D1

    (740) 0x43d09c FNEG	D5, D4

    (740) 0x43d0a0 MADD	X16, X16, X17, XZR

    (740) 0x43d0a4 FCSEL	D4, D5, D4, #11

    (740) 0x43d0a8 FABS	D5, D16

    (740) 0x43d0ac ADD	X16, X18, X16,LSL #3

    (740) 0x43d0b0 FMAXNM	D5, D5, D1

    (740) 0x43d0b4 FCMP	D4, #0

    (740) 0x43d0b8 FNEG	D6, D5

    (740) 0x43d0bc FCSEL	D5, D6, D5, #11

    (740) 0x43d0c0 FMUL	D6, D4, D4

    (740) 0x43d0c4 FMADD	D6, D5, D5, D6

    (740) 0x43d0c8 FSQRT	D6, D6

    (740) 0x43d0cc FMUL	D3, D6, D3

    (740) 0x43d0d0 FMUL	D2, D6, D2

    (740) 0x43d0d4 FDIV	D3, D3, D4

    (740) 0x43d0d8 FDIV	D2, D2, D5

    (740) 0x43d0dc FABS	D3, D3

    (740) 0x43d0e0 FABS	D2, D2

    (740) 0x43d0e4 FMINNM	D2, D3, D2

    (740) 0x43d0e8 LDR	D3, [X16, X2,SXTW #3]

    (740) 0x43d0ec FMUL	D2, D2, D7

    (740) 0x43d0f0 FMUL	D2, D2, D2

    (740) 0x43d0f4 FADD	D3, D3, D3

    (740) 0x43d0f8 FMUL	D17, D2, D3

    (740) 0x43d0fc B	43cf20

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.29 - 1.57
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13 - 1.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49 - 3.65
Bottlenecks	P8, P10,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	context.h:46-46,context.h:69-69,viscosity.cpp:37-50,viscosity.cpp:62-64
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.97 - 110.46
CQA cycles if no scalar integer	34.97 - 70.46
CQA cycles if FP arith vectorized	44.97 - 110.46
CQA cycles if fully vectorized	39.97 - 90.46
Front-end cycles	30.25
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	15.33
P3 cycles	15.17
P4 cycles	15.17
P5 cycles	15.17
P6 cycles	23.00
P7 cycles	15.17
P8 cycles	23.25
P9 cycles	23.25
P10 cycles	23.25
P11 cycles	23.25
P12 cycles	21.17
P13 cycles	20.83
P14 cycles	21.00
P15 cycles	5.50
P16 cycles	5.50
DIV/SQRT cycles	44.97 - 110.46
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	242.00
Nb uops	242.00
Nb loads	NA
Nb stores	13.00
Nb stack references	0.00
FLOP/cycle	2.31 - 0.94
Nb FLOP add-sub	40.00
Nb FLOP mul	32.00
Nb FLOP fma	6.00
Nb FLOP div	18.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.78 - 11.74
Bytes prefetched	0.00
Bytes loaded	412.00
Bytes stored	116.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	51.06
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	80.00
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	83.33
Vectorization ratio other	67.65
Vector-efficiency ratio all	75.89
Vector-efficiency ratio load	50.69
Vector-efficiency ratio store	51.92
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	88.00
Vector-efficiency ratio fma	75.00
Vector-efficiency ratio div_sqrt	91.67
Vector-efficiency ratio other	86.03

Metric	Value
CQA speedup if no scalar integer	1.29 - 1.57
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13 - 1.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49 - 3.65
Bottlenecks	P8, P10,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	context.h:46-46,context.h:69-69,viscosity.cpp:37-50,viscosity.cpp:62-64
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.97 - 110.46
CQA cycles if no scalar integer	34.97 - 70.46
CQA cycles if FP arith vectorized	44.97 - 110.46
CQA cycles if fully vectorized	39.97 - 90.46
Front-end cycles	30.25
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	15.33
P3 cycles	15.17
P4 cycles	15.17
P5 cycles	15.17
P6 cycles	23.00
P7 cycles	15.17
P8 cycles	23.25
P9 cycles	23.25
P10 cycles	23.25
P11 cycles	23.25
P12 cycles	21.17
P13 cycles	20.83
P14 cycles	21.00
P15 cycles	5.50
P16 cycles	5.50
DIV/SQRT cycles	44.97 - 110.46
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	242.00
Nb uops	242.00
Nb loads	NA
Nb stores	13.00
Nb stack references	0.00
FLOP/cycle	2.31 - 0.94
Nb FLOP add-sub	40.00
Nb FLOP mul	32.00
Nb FLOP fma	6.00
Nb FLOP div	18.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.78 - 11.74
Bytes prefetched	0.00
Bytes loaded	412.00
Bytes stored	116.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	51.06
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	80.00
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	83.33
Vectorization ratio other	67.65
Vector-efficiency ratio all	75.89
Vector-efficiency ratio load	50.69
Vector-efficiency ratio store	51.92
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	88.00
Vector-efficiency ratio fma	75.00
Vector-efficiency ratio div_sqrt	91.67
Vector-efficiency ratio other	86.03

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	viscosity.cpp:36-64
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 110.46 to 70.46 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 75% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 110.46 to 90.46 cycles (1.22x speedup).

Details

51% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
80% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
83% of VPU divide and square root instructions are used in vector version.
67% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

46: addition or subtraction (6 inside FMA instructions)
38: multiply (6 inside FMA instructions)
18: divide
2: square root

The binary loop is loading 412 bytes. The binary loop is storing 116 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	242
loop length	968
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	15.33	15.17	15.17	15.17	23.00	15.17	23.25	23.25	23.25	23.25	21.17	20.83	21.00	5.50	5.50
cycles	3.00	3.00	15.33	15.17	15.17	15.17	23.00	15.17	23.25	23.25	23.25	23.25	21.17	20.83	21.00	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

44.97-110.46

Cycles summary

Front-end	30.25
Overall L1	44.97-110.46

Vectorization ratios

INT

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	40%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	51%
load	0%
store	0%
mul	100%
add-sub	80%
fma	60%
div/sqrt	83%
other	67%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 110.46 cycles. At this rate:

3% of peak load performance is reached (3.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43cba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVZ X17, #35260	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X13, X16, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV V0.2D, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X27, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X6, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVK X17, #38872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X3, X0, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB W13, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W26, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVK X17, #53938	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W13, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W13, W24, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X16, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVK X17, #15516	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X24, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X25, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
DUP V1.2D, X17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STUR W23, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X1, X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 43cc48 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMLT V17.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS V4.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS V6.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDP X1, X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDUR W23, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X25, X13, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X6, X6, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMAXNM V4.2D, V4.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V6.2D, V6.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FNEG V18.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MADD X18, X1, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X16, X1, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
BIT V4.16B, V18.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V18.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X18, X21, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X21, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X18, X17,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FCMLT V17.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
BIT V6.16B, V18.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL V17.2D, V4.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA V17.2D, V6.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FSQRT V17.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	3.50-7.52	vect (100.0%)
FMUL V2.2D, V17.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V3.2D, V17.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV V2.2D, V2.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV V3.2D, V3.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FABS V2.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS V3.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMINNM V2.2D, V2.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V3.2D, V16.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL V2.2D, V2.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V2.2D, V2.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V2.2D, V2.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
USHLL V3.2D, V7.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (50.0%)
SHL V3.2D, V3.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
CMLT V3.2D, V3.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND V2.16B, V2.16B, V3.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR D2, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ST1 {V2.D[1]}, [X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	4	1	scal (50.0%)
CMP X13, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 43cef0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X0, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X19, X17, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD X18, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W17, W13, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W13, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W5, W23, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X21, X18, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
SBFM X27, X5, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W25, W23, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X18, X9, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X28, X25, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X4, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X22, X8, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X23, X8, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W4, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X25, X25, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD W24, W13, W19, W17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W7, W24, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D4, [X22, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD W26, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D6, [X22, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D2, [X12, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D22, [X12, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD W2, W13, W21, W17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W17, W2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X17, X17, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X13, X5,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X18, X23, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V4.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD W18, W5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X20, X18, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X18, X4, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X4, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X30, X9, X18, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X16, X8, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X8, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W30, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D5, [X16, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D7, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD X16, X11, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X10, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D17, [X16, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D16, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD X16, X11, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X16, X10, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D19, [X16, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D18, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LD1 {V5.D[1]}, [X4]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
SBFM X4, X30, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X23, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V7.D[1]}, [X0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
MADD X0, X11, X18, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1 {V6.D[1]}, [X22]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X0, X10, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V17.D[1]}, [X0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
MADD X0, X11, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1 {V16.D[1]}, [X22]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X0, X10, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD V26.2D, V5.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X16, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X0, X15, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1 {V19.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X16, X12, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V18.D[1]}, [X22]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
FADD V4.2D, V4.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V27.2D, V6.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR W22, WZR, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X14, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V2.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
LDUR X16, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FSUB V4.2D, V5.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB V26.2D, V26.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V4.2D, V4.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V27.2D, V17.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR D3, [X16, X5,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X16, X16, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V4.2D, V4.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD V5.2D, V16.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V28.2D, V18.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL V18.2D, V26.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V7.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUB V5.2D, V17.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB V27.2D, V27.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1 {V3.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
MADD X16, X15, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FADD V5.2D, V5.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V27.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADD X16, X14, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V5.2D, V5.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR D21, [X16, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D20, [X16, X24,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X16, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDIV V5.2D, V5.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV V4.2D, V4.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMLA V7.2D, V3.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
LD1 {V21.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD W16, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X0, W16,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FCMLT V7.2D, V7.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1 {V20.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X16, X12, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W17, W1, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V22.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
MADD X16, X15, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X17, X17, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X17, X15, X17, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X16, X14, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D23, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD X16, X15, X18, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X17, X14, X17,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X17, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X16, X14, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X16, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD V6.2D, V22.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V5.2D, V4.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB V4.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1 {V23.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD W16, W1, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X16, X16, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDIV V4.2D, V4.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MADD X16, X15, X16, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X16, X14, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X16, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V24.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X16, X13, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V25.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
FSUB V6.2D, V23.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V16.2D, V25.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV V6.2D, V6.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL V16.2D, V4.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V18.2D, V18.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV V18.2D, V18.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL V17.2D, V6.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V20.2D, V4.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V19.2D, V19.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD V16.2D, V17.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V16.2D, V16.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV V19.2D, V19.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMLA V18.2D, V20.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FADD V5.2D, V18.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV V5.2D, V5.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FCMLE V16.2D, V5.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND V7.16B, V16.16B, V7.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
XTN V7.2S, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMOV W16, S7	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
TBZ W16, #0, 43cec8 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X16, X13, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X13, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MOV W16, V7.S[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1	scal (25.0%)
SBFM X17, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W16, #0, 43cba0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X16, X13, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X13, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X16, X17,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V16.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
B 43cba0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X16, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W26, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.EQ 43cab4 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	viscosity.cpp:36-64
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

51% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
80% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
83% of VPU divide and square root instructions are used in vector version.
67% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

46: addition or subtraction (6 inside FMA instructions)
38: multiply (6 inside FMA instructions)
18: divide
2: square root

The binary loop is loading 412 bytes. The binary loop is storing 116 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	242
loop length	968
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	15.33	15.17	15.17	15.17	23.00	15.17	23.25	23.25	23.25	23.25	21.17	20.83	21.00	5.50	5.50
cycles	3.00	3.00	15.33	15.17	15.17	15.17	23.00	15.17	23.25	23.25	23.25	23.25	21.17	20.83	21.00	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

44.97-110.46

Cycles summary

Front-end	30.25
Overall L1	44.97-110.46

Vectorization ratios

INT

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	40%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	51%
load	0%
store	0%
mul	100%
add-sub	80%
fma	60%
div/sqrt	83%
other	67%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 110.46 cycles. At this rate:

3% of peak load performance is reached (3.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43cba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVZ X17, #35260	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X13, X16, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV V0.2D, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X27, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X6, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVK X17, #38872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X3, X0, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB W13, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W26, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVK X17, #53938	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W13, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W13, W24, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X16, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVK X17, #15516	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X24, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X25, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
DUP V1.2D, X17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STUR W23, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X1, X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 43cc48 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMLT V17.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS V4.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS V6.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDP X1, X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDUR W23, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X25, X13, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X6, X6, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMAXNM V4.2D, V4.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V6.2D, V6.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FNEG V18.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MADD X18, X1, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X16, X1, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
BIT V4.16B, V18.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V18.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X18, X21, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X21, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X18, X17,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FCMLT V17.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
BIT V6.16B, V18.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL V17.2D, V4.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA V17.2D, V6.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FSQRT V17.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	3.50-7.52	vect (100.0%)
FMUL V2.2D, V17.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V3.2D, V17.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV V2.2D, V2.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV V3.2D, V3.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FABS V2.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS V3.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMINNM V2.2D, V2.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V3.2D, V16.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL V2.2D, V2.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V2.2D, V2.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V2.2D, V2.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
USHLL V3.2D, V7.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (50.0%)
SHL V3.2D, V3.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
CMLT V3.2D, V3.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND V2.16B, V2.16B, V3.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR D2, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ST1 {V2.D[1]}, [X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	4	1	scal (50.0%)
CMP X13, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 43cef0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X0, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X19, X17, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD X18, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W17, W13, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W13, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W5, W23, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X21, X18, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
SBFM X27, X5, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W25, W23, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X18, X9, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X28, X25, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X4, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X22, X8, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X23, X8, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W4, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X25, X25, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD W24, W13, W19, W17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W7, W24, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D4, [X22, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD W26, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D6, [X22, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D2, [X12, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D22, [X12, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD W2, W13, W21, W17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W17, W2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X17, X17, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X13, X5,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X18, X23, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V4.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD W18, W5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X20, X18, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X18, X4, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X4, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X30, X9, X18, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X16, X8, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X8, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W30, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D5, [X16, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D7, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD X16, X11, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X10, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D17, [X16, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D16, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD X16, X11, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X16, X10, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D19, [X16, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D18, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LD1 {V5.D[1]}, [X4]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
SBFM X4, X30, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X23, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V7.D[1]}, [X0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
MADD X0, X11, X18, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1 {V6.D[1]}, [X22]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X0, X10, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V17.D[1]}, [X0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
MADD X0, X11, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1 {V16.D[1]}, [X22]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X0, X10, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD V26.2D, V5.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X16, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X0, X15, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1 {V19.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X16, X12, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V18.D[1]}, [X22]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
FADD V4.2D, V4.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V27.2D, V6.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR W22, WZR, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X14, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V2.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
LDUR X16, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FSUB V4.2D, V5.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB V26.2D, V26.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V4.2D, V4.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V27.2D, V17.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR D3, [X16, X5,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X16, X16, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V4.2D, V4.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD V5.2D, V16.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V28.2D, V18.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL V18.2D, V26.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V7.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUB V5.2D, V17.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB V27.2D, V27.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1 {V3.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
MADD X16, X15, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FADD V5.2D, V5.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V27.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADD X16, X14, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V5.2D, V5.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR D21, [X16, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D20, [X16, X24,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X16, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDIV V5.2D, V5.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV V4.2D, V4.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMLA V7.2D, V3.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
LD1 {V21.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD W16, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X0, W16,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FCMLT V7.2D, V7.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1 {V20.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X16, X12, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W17, W1, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V22.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
MADD X16, X15, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X17, X17, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X17, X15, X17, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X16, X14, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D23, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD X16, X15, X18, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X17, X14, X17,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X17, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X16, X14, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X16, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD V6.2D, V22.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V5.2D, V4.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB V4.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1 {V23.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD W16, W1, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X16, X16, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDIV V4.2D, V4.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MADD X16, X15, X16, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X16, X14, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X16, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V24.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
ADD X16, X13, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V25.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
FSUB V6.2D, V23.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V16.2D, V25.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV V6.2D, V6.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL V16.2D, V4.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V18.2D, V18.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV V18.2D, V18.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL V17.2D, V6.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V20.2D, V4.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V19.2D, V19.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD V16.2D, V17.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V16.2D, V16.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV V19.2D, V19.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMLA V18.2D, V20.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FADD V5.2D, V18.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV V5.2D, V5.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FCMLE V16.2D, V5.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND V7.16B, V16.16B, V7.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
XTN V7.2S, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMOV W16, S7	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
TBZ W16, #0, 43cec8 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X16, X13, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X13, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X16, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MOV W16, V7.S[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1	scal (25.0%)
SBFM X17, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W16, #0, 43cba0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X16, X13, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X13, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X16, X17,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V16.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
B 43cba0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X16, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W26, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.EQ 43cab4 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code