OV - exec - Loop 261

	Loop Id: 261	Module: exec	Source: initialise_chunk.cpp:78-82 [...]	Coverage: 0.02%

0x425c84 ADD	X7, X18, #1

0x425c88 SDIV	X22, X18, X23

0x425c8c LDR	D0, [X20]    [5]

0x425c90 LDR	D1, [X19]    [10]

0x425c94 SUBS	X6, X6, #2

0x425c98 ADD	X18, X18, #2

0x425c9c FMUL	D0, D1, D0

0x425ca0 SBFM	X24, X22, #0, #31

0x425ca4 SDIV	X7, X7, X23

0x425ca8 SBFM	X25, X7, #0, #31

0x425cac MADD	X26, X9, X24, XZR

0x425cb0 MADD	X27, X9, X25, XZR

0x425cb4 ADD	X26, X8, X26,LSL #3

0x425cb8 ADD	X27, X8, X27,LSL #3

0x425cbc MADD	X28, X2, X7, X3

0x425cc0 ADD	X28, X28, X4

0x425cc4 SBFM	X28, X28, #29, #63

0x425cc8 MADD	X30, X2, X22, X3

0x425ccc SBFM	X30, X30, #29, #63

0x425cd0 STR	D0, [X26, X30]    [8]

0x425cd4 ADD	X3, X3, X5

0x425cd8 STR	D0, [X27, X28]    [9]

0x425cdc LDR	D0, [X10, X22,SXTW #3]    [4]

0x425ce0 LDR	D1, [X10, X7,SXTW #3]    [4]

0x425ce4 MADD	X7, X12, X24, XZR

0x425ce8 MADD	X22, X12, X25, XZR

0x425cec ADD	X7, X11, X7,LSL #3

0x425cf0 STR	D0, [X7, X30]    [3]

0x425cf4 ADD	X7, X11, X22,LSL #3

0x425cf8 MADD	X22, X15, X25, XZR

0x425cfc STR	D1, [X7, X28]    [2]

0x425d00 MADD	X7, X15, X24, XZR

0x425d04 LDR	D0, [X13, X30]    [7]

0x425d08 LDR	D1, [X13, X28]    [7]

0x425d0c ADD	X22, X14, X22,LSL #3

0x425d10 ADD	X7, X14, X7,LSL #3

0x425d14 STR	D0, [X7, X30]    [1]

0x425d18 STR	D1, [X22, X28]    [6]

0x425d1c B.NE	425c84

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp: 78 - 82

--------------------------------------------------------------------------------

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.05 - 4.00
Bottlenecks	P8, P10,
Function	initialise_chunk(int, global_variables&) [clone .omp_outlined.8]
Source	initialise_chunk.cpp:78-82,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	10.00 - 40.00
CQA cycles if no scalar integer	5.00 - 20.00
CQA cycles if FP arith vectorized	5.00 - 20.00
CQA cycles if fully vectorized	10.00 - 40.00
Front-end cycles	4.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.00
P3 cycles	3.08
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	10.00
P7 cycles	2.92
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.10 - 0.03
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.40 - 9.60
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	48.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	7.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	55.56
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.05 - 4.00
Bottlenecks	P8, P10,
Function	initialise_chunk(int, global_variables&) [clone .omp_outlined.8]
Source	initialise_chunk.cpp:78-82,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	10.00 - 40.00
CQA cycles if no scalar integer	5.00 - 20.00
CQA cycles if FP arith vectorized	5.00 - 20.00
CQA cycles if fully vectorized	10.00 - 40.00
Front-end cycles	4.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.00
P3 cycles	3.08
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	10.00
P7 cycles	2.92
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.10 - 0.03
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.40 - 9.60
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	48.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	7.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	55.56
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	initialise_chunk(int, global_variables&) [clone .omp_outlined.8]
Source file and lines	initialise_chunk.cpp:78-82
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:78-82
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 20.00 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 48 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	3.00	3.08	3.00	3.00	10.00	2.92	3.00	3.00	0.50	0.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	3.00	3.08	3.00	3.00	10.00	2.92	3.00	3.00	0.50	0.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.88
Data deps.	1.00
Overall L1	10.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 425c84

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X7, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X22, X18, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR D0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
SUBS X6, X6, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X18, X18, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMUL D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
SBFM X24, X22, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SDIV X7, X7, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X25, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X26, X9, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X27, X9, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X26, X8, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X8, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X28, X2, X7, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X28, X28, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X28, X28, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X30, X2, X22, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X30, X30, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X26, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X3, X3, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR D0, [X27, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D0, [X10, X22,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X10, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X7, X12, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X22, X12, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X7, X11, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X7, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X7, X11, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X22, X15, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
STR D1, [X7, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X7, X15, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X13, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X22, X14, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X14, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X7, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D1, [X22, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B.NE 425c84 <_Z16initialise_chunkiR16global_variables.omp_outlined.8+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	initialise_chunk(int, global_variables&) [clone .omp_outlined.8]
Source file and lines	initialise_chunk.cpp:78-82
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:78-82
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 48 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	3.00	3.08	3.00	3.00	10.00	2.92	3.00	3.00	0.50	0.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	3.00	3.08	3.00	3.00	10.00	2.92	3.00	3.00	0.50	0.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.88
Data deps.	1.00
Overall L1	10.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 425c84

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X7, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X22, X18, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR D0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
SUBS X6, X6, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X18, X18, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMUL D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
SBFM X24, X22, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SDIV X7, X7, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X25, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X26, X9, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X27, X9, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X26, X8, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X8, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X28, X2, X7, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X28, X28, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X28, X28, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X30, X2, X22, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X30, X30, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X26, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X3, X3, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR D0, [X27, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D0, [X10, X22,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X10, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X7, X12, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X22, X12, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X7, X11, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X7, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X7, X11, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X22, X15, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
STR D1, [X7, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X7, X15, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X13, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X22, X14, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X14, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X7, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D1, [X22, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B.NE 425c84 <_Z16initialise_chunkiR16global_variables.omp_outlined.8+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code