OV - exec - Loop 244

	Loop Id: 244	Module: exec	Source: generate_chunk.cpp:75-80 [...]	Coverage: 0.05%

0x42402c ADD	X23, X3, #1

0x424030 SDIV	X25, X3, X24

0x424034 LDR	D0, [X8]    [1]

0x424038 SUBS	X22, X22, #2

0x42403c ADD	X3, X3, #2

0x424040 MADD	X26, X6, X25, X7

0x424044 SBFM	X25, X25, #0, #31

0x424048 MADD	X28, X10, X25, XZR

0x42404c SDIV	X23, X23, X24

0x424050 SBFM	X26, X26, #29, #63

0x424054 ADD	X28, X9, X28,LSL #3

0x424058 STR	D0, [X28, X26]    [12]

0x42405c MADD	X28, X13, X25, XZR

0x424060 ADD	X28, X12, X28,LSL #3

0x424064 MADD	X27, X6, X23, X7

0x424068 SBFM	X23, X23, #0, #31

0x42406c MADD	X30, X10, X23, XZR

0x424070 ADD	X27, X27, X20

0x424074 ADD	X30, X9, X30,LSL #3

0x424078 SBFM	X27, X27, #29, #63

0x42407c STR	D0, [X30, X27]    [4]

0x424080 LDR	D0, [X11]    [5]

0x424084 MADD	X30, X13, X23, XZR

0x424088 ADD	X7, X7, X21

0x42408c ADD	X30, X12, X30,LSL #3

0x424090 STR	D0, [X28, X26]    [11]

0x424094 STR	D0, [X30, X27]    [3]

0x424098 MADD	X28, X16, X25, XZR

0x42409c MADD	X30, X16, X23, XZR

0x4240a0 MADD	X25, X0, X25, XZR

0x4240a4 MADD	X23, X0, X23, XZR

0x4240a8 LDR	D0, [X14]    [7]

0x4240ac ADD	X28, X15, X28,LSL #3

0x4240b0 ADD	X30, X15, X30,LSL #3

0x4240b4 ADD	X25, X18, X25,LSL #3

0x4240b8 ADD	X23, X18, X23,LSL #3

0x4240bc STR	D0, [X28, X26]    [10]

0x4240c0 STR	D0, [X30, X27]    [2]

0x4240c4 LDR	D0, [X17]    [9]

0x4240c8 STR	D0, [X25, X26]    [8]

0x4240cc STR	D0, [X23, X27]    [6]

0x4240d0 B.NE	42402c

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 75 - 80

--------------------------------------------------------------------------------

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

78:       field.density0(i, j) = state_density[0];

79:       field.xvel0(i, j) = state_xvel[0];

80:       field.yvel0(i, j) = state_yvel[0];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.40 - 2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.33
Bottlenecks	P8, P10,
Function	generate_chunk(int, global_variables&) [clone .omp_outlined]
Source	generate_chunk.cpp:75-80,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	12.00 - 40.00
CQA cycles if no scalar integer	5.00 - 20.00
CQA cycles if FP arith vectorized	12.00 - 40.00
CQA cycles if fully vectorized	6.00 - 20.00
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.50
P3 cycles	3.42
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	12.00
P7 cycles	3.42
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.40 - 8.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	64.00
Stride 0	4.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	2.40 - 2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.33
Bottlenecks	P8, P10,
Function	generate_chunk(int, global_variables&) [clone .omp_outlined]
Source	generate_chunk.cpp:75-80,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	12.00 - 40.00
CQA cycles if no scalar integer	5.00 - 20.00
CQA cycles if FP arith vectorized	12.00 - 40.00
CQA cycles if fully vectorized	6.00 - 20.00
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.50
P3 cycles	3.42
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	12.00
P7 cycles	3.42
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.40 - 8.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	64.00
Stride 0	4.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk(int, global_variables&) [clone .omp_outlined]
Source file and lines	generate_chunk.cpp:75-80
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75-80
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 20.00 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 40.00 to 20.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	3.50	3.42	3.33	3.33	12.00	3.42	4.00	4.00	0.00	0.00	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	3.50	3.42	3.33	3.33	12.00	3.42	4.00	4.00	0.00	0.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	12.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42402c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X23, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X25, X3, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
SUBS X22, X22, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X3, X3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X26, X6, X25, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SBFM X25, X25, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X28, X10, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SDIV X23, X23, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X26, X26, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X28, X9, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR D0, [X28, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X28, X13, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X28, X12, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X27, X6, X23, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SBFM X23, X23, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X30, X10, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X27, X27, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X30, X9, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X27, X27, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR D0, [X30, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X30, X13, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X7, X7, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X30, X12, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR D0, [X28, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X30, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X28, X16, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X30, X16, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X25, X0, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X23, X0, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR D0, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X28, X15, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X30, X15, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X25, X18, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X23, X18, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR D0, [X28, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X30, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D0, [X25, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X23, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
B.NE 42402c <_Z14generate_chunkiR16global_variables.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	generate_chunk(int, global_variables&) [clone .omp_outlined]
Source file and lines	generate_chunk.cpp:75-80
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75-80
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	3.50	3.42	3.33	3.33	12.00	3.42	4.00	4.00	0.00	0.00	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	3.50	3.42	3.33	3.33	12.00	3.42	4.00	4.00	0.00	0.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	12.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42402c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X23, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X25, X3, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
SUBS X22, X22, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X3, X3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X26, X6, X25, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SBFM X25, X25, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X28, X10, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SDIV X23, X23, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X26, X26, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X28, X9, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR D0, [X28, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X28, X13, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X28, X12, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X27, X6, X23, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SBFM X23, X23, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X30, X10, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X27, X27, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X30, X9, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X27, X27, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR D0, [X30, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X30, X13, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X7, X7, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X30, X12, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR D0, [X28, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X30, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X28, X16, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X30, X16, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X25, X0, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X23, X0, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR D0, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X28, X15, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X30, X15, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X25, X18, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X23, X18, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR D0, [X28, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X30, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D0, [X25, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X23, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
B.NE 42402c <_Z14generate_chunkiR16global_variables.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code