OV - exec - Loop 204

	Loop Id: 204	Module: exec	Source: build_field.cpp:119-128 [...]	Coverage: 0.01%

0x420060 ADD	X28, X7, #1

0x420064 SDIV	X30, X7, X21

0x420068 MOVZ	X19, #1

0x42006c SUBS	X27, X27, #2

0x420070 ADD	X7, X7, #2

0x420074 SBFM	X22, X30, #0, #31

0x420078 SDIV	X28, X28, X21

0x42007c MADD	X30, X23, X30, X24

0x420080 SBFM	X30, X30, #29, #63

0x420084 MADD	X20, X23, X28, X24

0x420088 SBFM	X28, X28, #0, #31

0x42008c MADD	X25, X8, X28, XZR

0x420090 MADD	X26, X16, X28, XZR

0x420094 ADD	X20, X20, X19

0x420098 MADD	X19, X8, X22, XZR

0x42009c SBFM	X20, X20, #29, #63

0x4200a0 ADD	X19, X9, X19,LSL #3

0x4200a4 STR	XZR, [X19, X30]    [11]

0x4200a8 ADD	X19, X9, X25,LSL #3

0x4200ac MADD	X25, X16, X22, XZR

0x4200b0 STR	XZR, [X19, X20]    [10]

0x4200b4 MADD	X19, X10, X22, XZR

0x4200b8 ADD	X25, X17, X25,LSL #3

0x4200bc ADD	X19, X11, X19,LSL #3

0x4200c0 STR	XZR, [X19, X30]    [5]

0x4200c4 MADD	X19, X10, X28, XZR

0x4200c8 ADD	X19, X11, X19,LSL #3

0x4200cc STR	XZR, [X19, X20]    [4]

0x4200d0 MADD	X19, X12, X22, XZR

0x4200d4 ADD	X19, X13, X19,LSL #3

0x4200d8 STR	XZR, [X19, X30]    [3]

0x4200dc MADD	X19, X12, X28, XZR

0x4200e0 ADD	X19, X13, X19,LSL #3

0x4200e4 STR	XZR, [X19, X20]    [2]

0x4200e8 MADD	X19, X14, X22, XZR

0x4200ec ADD	X19, X15, X19,LSL #3

0x4200f0 STR	XZR, [X19, X30]    [1]

0x4200f4 MADD	X19, X14, X28, XZR

0x4200f8 ADD	X19, X15, X19,LSL #3

0x4200fc STR	XZR, [X19, X20]    [16]

0x420100 ADD	X19, X17, X26,LSL #3

0x420104 STR	XZR, [X25, X30]    [9]

0x420108 MADD	X25, X18, X28, XZR

0x42010c MADD	X26, X2, X28, XZR

0x420110 STR	XZR, [X19, X20]    [15]

0x420114 MADD	X19, X18, X22, XZR

0x420118 ADD	X25, X1, X25,LSL #3

0x42011c ADD	X19, X1, X19,LSL #3

0x420120 STR	XZR, [X19, X30]    [14]

0x420124 MADD	X19, X2, X22, XZR

0x420128 STR	XZR, [X25, X20]    [8]

0x42012c ADD	X25, X0, X26,LSL #3

0x420130 ADD	X19, X0, X19,LSL #3

0x420134 STR	XZR, [X19, X30]    [13]

0x420138 MADD	X19, X5, X22, XZR

0x42013c MADD	X22, X5, X28, XZR

0x420140 STR	XZR, [X25, X20]    [7]

0x420144 ADD	X19, X3, X19,LSL #3

0x420148 ADD	X22, X3, X22,LSL #3

0x42014c STR	XZR, [X19, X30]    [12]

0x420150 MOVZ	X19, #2

0x420154 STR	XZR, [X22, X20]    [6]

0x420158 ADD	X24, X24, X19

0x42015c B.NE	420060

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp: 119 - 128

--------------------------------------------------------------------------------

119:     for (int j = (0); j < (yrange); j++) {

120:       for (int i = (0); i < (xrange); i++) {

121:         field.density0(i, j) = 0.0;

122:         field.density1(i, j) = 0.0;

123:         field.energy0(i, j) = 0.0;

124:         field.energy1(i, j) = 0.0;

125:         field.pressure(i, j) = 0.0;

126:         field.viscosity(i, j) = 0.0;

127:         field.soundspeed(i, j) = 0.0;

128:         field.volume(i, j) = 0.0;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.08 - 1.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P8, P10,
Function	build_field(global_variables&) [clone .omp_outlined.2]
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	20.00 - 40.00
CQA cycles if no scalar integer	20.00 - 40.00
CQA cycles if FP arith vectorized	20.00 - 40.00
CQA cycles if fully vectorized	18.50 - 30.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.50
P3 cycles	5.42
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	20.00
P7 cycles	5.42
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	8.00
P16 cycles	8.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	64.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.20 - 6.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	16.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	52.17
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.08 - 1.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P8, P10,
Function	build_field(global_variables&) [clone .omp_outlined.2]
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	20.00 - 40.00
CQA cycles if no scalar integer	20.00 - 40.00
CQA cycles if FP arith vectorized	20.00 - 40.00
CQA cycles if fully vectorized	18.50 - 30.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.50
P3 cycles	5.42
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	20.00
P7 cycles	5.42
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	8.00
P16 cycles	8.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	64.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.20 - 6.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	16.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	52.17
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field(global_variables&) [clone .omp_outlined.2]
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-128
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 40.00 to 30.00 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 128 bytes.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	5.50	5.42	5.33	5.33	20.00	5.42	0.00	0.00	0.00	0.00	8.00	8.00	0.00	8.00	8.00
cycles	0.50	0.50	5.50	5.42	5.33	5.33	20.00	5.42	0.00	0.00	0.00	0.00	8.00	8.00	0.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.00
Data deps.	1.00
Overall L1	20.00-40.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P15	P16	Latency	Recip. throughput	Vectorization
ADD X28, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (50.0%)
SDIV X30, X7, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	5-20	5-20	N/A
MOVZ X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUBS X27, X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	1	0.33	scal (50.0%)
ADD X7, X7, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (50.0%)
SBFM X22, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SDIV X28, X28, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	5-20	5-20	scal (50.0%)
MADD X30, X23, X30, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
SBFM X30, X30, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MADD X20, X23, X28, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
SBFM X28, X28, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (100.0%)
MADD X25, X8, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
MADD X26, X16, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
ADD X20, X20, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MADD X19, X8, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
SBFM X20, X20, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X19, X9, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X19, X9, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MADD X25, X16, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X10, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X25, X17, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X19, X11, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X10, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X11, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X12, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X13, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X12, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X13, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X14, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X15, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X14, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X15, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X19, X17, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X25, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X25, X18, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
MADD X26, X2, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X18, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X25, X1, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X19, X1, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X2, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
STR XZR, [X25, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X25, X0, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X19, X0, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X5, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
MADD X22, X5, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
STR XZR, [X25, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X19, X3, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X22, X3, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X24, X24, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
B.NE 420060 <_Z11build_fieldR16global_variables.omp_outlined.2+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	build_field(global_variables&) [clone .omp_outlined.2]
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-128
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 128 bytes.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	5.50	5.42	5.33	5.33	20.00	5.42	0.00	0.00	0.00	0.00	8.00	8.00	0.00	8.00	8.00
cycles	0.50	0.50	5.50	5.42	5.33	5.33	20.00	5.42	0.00	0.00	0.00	0.00	8.00	8.00	0.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.00
Data deps.	1.00
Overall L1	20.00-40.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P15	P16	Latency	Recip. throughput	Vectorization
ADD X28, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (50.0%)
SDIV X30, X7, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	5-20	5-20	N/A
MOVZ X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUBS X27, X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	1	0.33	scal (50.0%)
ADD X7, X7, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (50.0%)
SBFM X22, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SDIV X28, X28, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	5-20	5-20	scal (50.0%)
MADD X30, X23, X30, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
SBFM X30, X30, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MADD X20, X23, X28, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
SBFM X28, X28, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (100.0%)
MADD X25, X8, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
MADD X26, X16, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
ADD X20, X20, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MADD X19, X8, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
SBFM X20, X20, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X19, X9, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X19, X9, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MADD X25, X16, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X10, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X25, X17, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X19, X11, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X10, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X11, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X12, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X13, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X12, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X13, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X14, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X15, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X14, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X19, X15, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X19, X17, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X25, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X25, X18, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
MADD X26, X2, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
STR XZR, [X19, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X18, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
ADD X25, X1, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X19, X1, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X2, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
STR XZR, [X25, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X25, X0, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X19, X0, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MADD X19, X5, X22, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
MADD X22, X5, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	N/A
STR XZR, [X25, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X19, X3, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X22, X3, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (50.0%)
ADD X24, X24, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
B.NE 420060 <_Z11build_fieldR16global_variables.omp_outlined.2+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code