OV - exec - Loop 202

	Loop Id: 202	Module: exec	Source: build_field.cpp:101-113 [...]	Coverage: 0.02%

0x41fd00 LDP	X8, X9, [SP, #40]    [7]

0x41fd04 ADD	X19, X26, #1

0x41fd08 SUBS	X27, X27, #2

0x41fd0c SDIV	X20, X26, X9

0x41fd10 ADD	X26, X26, #2

0x41fd14 MADD	X22, X8, X20, X28

0x41fd18 SDIV	X30, X19, X9

0x41fd1c LDUR	X9, [X29, #472]    [24]

0x41fd20 SBFM	X19, X20, #0, #31

0x41fd24 MADD	X20, X9, X19, XZR

0x41fd28 SBFM	X22, X22, #29, #63

0x41fd2c ADD	X20, X13, X20,LSL #3

0x41fd30 STR	XZR, [X20, X22]    [8]

0x41fd34 MADD	X20, X8, X30, X28

0x41fd38 MOVZ	X8, #1

0x41fd3c ADD	X8, X20, X8

0x41fd40 SBFM	X20, X30, #0, #31

0x41fd44 MADD	X30, X9, X20, XZR

0x41fd48 ADD	X9, X13, X30,LSL #3

0x41fd4c SBFM	X30, X8, #29, #63

0x41fd50 STR	XZR, [X9, X30]    [6]

0x41fd54 LDR	X9, [SP, #56]    [7]

0x41fd58 MADD	X8, X9, X19, XZR

0x41fd5c ADD	X8, X11, X8,LSL #3

0x41fd60 STR	XZR, [X8, X22]    [23]

0x41fd64 MADD	X8, X9, X20, XZR

0x41fd68 ADD	X8, X11, X8,LSL #3

0x41fd6c STR	XZR, [X8, X30]    [22]

0x41fd70 MADD	X8, X10, X19, XZR

0x41fd74 ADD	X8, X12, X8,LSL #3

0x41fd78 STR	XZR, [X8, X22]    [16]

0x41fd7c MADD	X8, X10, X20, XZR

0x41fd80 ADD	X8, X12, X8,LSL #3

0x41fd84 STR	XZR, [X8, X30]    [15]

0x41fd88 MADD	X8, X14, X19, XZR

0x41fd8c ADD	X8, X15, X8,LSL #3

0x41fd90 STR	XZR, [X8, X22]    [14]

0x41fd94 MADD	X8, X14, X20, XZR

0x41fd98 ADD	X8, X15, X8,LSL #3

0x41fd9c STR	XZR, [X8, X30]    [13]

0x41fda0 MADD	X8, X16, X19, XZR

0x41fda4 ADD	X8, X17, X8,LSL #3

0x41fda8 STR	XZR, [X8, X22]    [12]

0x41fdac MADD	X8, X16, X20, XZR

0x41fdb0 ADD	X8, X17, X8,LSL #3

0x41fdb4 STR	XZR, [X8, X30]    [5]

0x41fdb8 MADD	X8, X18, X19, XZR

0x41fdbc ADD	X8, X1, X8,LSL #3

0x41fdc0 STR	XZR, [X8, X22]    [4]

0x41fdc4 MADD	X8, X18, X20, XZR

0x41fdc8 ADD	X8, X1, X8,LSL #3

0x41fdcc STR	XZR, [X8, X30]    [3]

0x41fdd0 MADD	X8, X2, X19, XZR

0x41fdd4 ADD	X8, X0, X8,LSL #3

0x41fdd8 STR	XZR, [X8, X22]    [2]

0x41fddc MADD	X8, X2, X20, XZR

0x41fde0 ADD	X8, X0, X8,LSL #3

0x41fde4 STR	XZR, [X8, X30]    [1]

0x41fde8 MADD	X8, X3, X19, XZR

0x41fdec ADD	X8, X4, X8,LSL #3

0x41fdf0 STR	XZR, [X8, X22]    [21]

0x41fdf4 MADD	X8, X3, X20, XZR

0x41fdf8 ADD	X8, X4, X8,LSL #3

0x41fdfc STR	XZR, [X8, X30]    [20]

0x41fe00 MADD	X8, X5, X19, XZR

0x41fe04 ADD	X8, X6, X8,LSL #3

0x41fe08 STR	XZR, [X8, X22]    [19]

0x41fe0c MADD	X8, X5, X20, XZR

0x41fe10 ADD	X8, X6, X8,LSL #3

0x41fe14 STR	XZR, [X8, X30]    [18]

0x41fe18 MADD	X8, X7, X19, XZR

0x41fe1c ADD	X8, X23, X8,LSL #3

0x41fe20 STR	XZR, [X8, X22]    [17]

0x41fe24 MADD	X8, X7, X20, XZR

0x41fe28 ADD	X8, X23, X8,LSL #3

0x41fe2c STR	XZR, [X8, X30]    [11]

0x41fe30 MADD	X8, X24, X19, XZR

0x41fe34 ADD	X8, X21, X8,LSL #3

0x41fe38 STR	XZR, [X8, X22]    [10]

0x41fe3c MADD	X8, X24, X20, XZR

0x41fe40 ADD	X8, X21, X8,LSL #3

0x41fe44 STR	XZR, [X8, X30]    [9]

0x41fe48 MOVZ	X8, #2

0x41fe4c ADD	X28, X28, X8

0x41fe50 B.NE	41fd00

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp: 101 - 113

--------------------------------------------------------------------------------

101:     for (int j = (0); j < (yrange + 1); j++) {

102:       for (int i = (0); i < (xrange + 1); i++) {

103:         field.work_array1(i, j) = 0.0;

104:         field.work_array2(i, j) = 0.0;

105:         field.work_array3(i, j) = 0.0;

106:         field.work_array4(i, j) = 0.0;

107:         field.work_array5(i, j) = 0.0;

108:         field.work_array6(i, j) = 0.0;

109:         field.work_array7(i, j) = 0.0;

110:         field.xvel0(i, j) = 0.0;

111:         field.xvel1(i, j) = 0.0;

112:         field.yvel0(i, j) = 0.0;

113:         field.yvel1(i, j) = 0.0;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.36 - 1.54
Bottlenecks	P8, P10,
Function	build_field(global_variables&) [clone .omp_outlined]
Source	build_field.cpp:101-113,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	26.00 - 40.00
CQA cycles if no scalar integer	26.00 - 40.00
CQA cycles if FP arith vectorized	26.00 - 40.00
CQA cycles if fully vectorized	26.00 - 40.00
Front-end cycles	10.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	6.67
P3 cycles	6.58
P4 cycles	6.67
P5 cycles	6.50
P6 cycles	26.00
P7 cycles	6.58
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	11.00
P13 cycles	11.00
P14 cycles	3.00
P15 cycles	11.00
P16 cycles	11.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	85.00
Nb uops	85.00
Nb loads	NA
Nb stores	22.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.20 - 8.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	176.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	22.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	51.92
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.36 - 1.54
Bottlenecks	P8, P10,
Function	build_field(global_variables&) [clone .omp_outlined]
Source	build_field.cpp:101-113,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	26.00 - 40.00
CQA cycles if no scalar integer	26.00 - 40.00
CQA cycles if FP arith vectorized	26.00 - 40.00
CQA cycles if fully vectorized	26.00 - 40.00
Front-end cycles	10.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	6.67
P3 cycles	6.58
P4 cycles	6.67
P5 cycles	6.50
P6 cycles	26.00
P7 cycles	6.58
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	11.00
P13 cycles	11.00
P14 cycles	3.00
P15 cycles	11.00
P16 cycles	11.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	85.00
Nb uops	85.00
Nb loads	NA
Nb stores	22.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.20 - 8.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	176.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	22.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	51.92
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field(global_variables&) [clone .omp_outlined]
Source file and lines	build_field.cpp:101-113
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:101-113
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 51% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 176 bytes.

General properties

nb instructions	85
loop length	340
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	6.67	6.58	6.67	6.50	26.00	6.58	0.00	0.00	0.00	0.00	11.00	11.00	3.00	11.00	11.00
cycles	0.50	0.50	6.67	6.58	6.67	6.50	26.00	6.58	0.00	0.00	0.00	0.00	11.00	11.00	3.00	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.63
Data deps.	1.00
Overall L1	26.00-40.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fd00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDP X8, X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X19, X26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUBS X27, X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X20, X26, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
ADD X26, X26, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X22, X8, X20, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SDIV X30, X19, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X19, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X20, X9, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SBFM X22, X22, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X20, X13, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X20, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X20, X8, X30, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MOVZ X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X8, X20, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X20, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X30, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X9, X13, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X30, X8, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X9, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X8, X9, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X11, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X11, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X10, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X12, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X10, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X12, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X14, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X15, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X14, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X15, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X16, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X17, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X16, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X17, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X18, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X1, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X18, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X1, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X2, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X0, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X2, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X0, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X3, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X4, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X3, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X4, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X5, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X6, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X5, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X6, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X7, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X23, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X7, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X23, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X24, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X21, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X24, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X21, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X28, X28, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B.NE 41fd00 <_Z11build_fieldR16global_variables.omp_outlined+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	build_field(global_variables&) [clone .omp_outlined]
Source file and lines	build_field.cpp:101-113
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:101-113
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 51% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 176 bytes.

General properties

nb instructions	85
loop length	340
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	6.67	6.58	6.67	6.50	26.00	6.58	0.00	0.00	0.00	0.00	11.00	11.00	3.00	11.00	11.00
cycles	0.50	0.50	6.67	6.58	6.67	6.50	26.00	6.58	0.00	0.00	0.00	0.00	11.00	11.00	3.00	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.63
Data deps.	1.00
Overall L1	26.00-40.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fd00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDP X8, X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X19, X26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUBS X27, X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X20, X26, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
ADD X26, X26, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X22, X8, X20, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SDIV X30, X19, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X19, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X20, X9, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SBFM X22, X22, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X20, X13, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X20, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X20, X8, X30, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MOVZ X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X8, X20, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X20, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X30, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X9, X13, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X30, X8, #29, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X9, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X8, X9, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X11, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X11, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X10, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X12, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X10, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X12, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X14, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X15, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X14, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X15, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X16, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X17, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X16, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X17, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X18, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X1, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X18, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X1, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X2, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X0, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X2, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X0, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X3, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X4, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X3, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X4, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X5, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X6, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X5, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X6, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X7, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X23, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X7, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X23, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X24, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X21, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD X8, X24, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X8, X21, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X28, X28, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B.NE 41fd00 <_Z11build_fieldR16global_variables.omp_outlined+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code