OV - exec - Loop 200

	Loop Id: 200	Module: exec	Source: advec_mom.cpp:219-221 [...]	Coverage: 4.62%

0x41f7c0 SUB	X4, X1, #1

0x41f7c4 SDIV	X7, X1, X25

0x41f7c8 SUBS	X3, X3, #2

0x41f7cc ADD	W20, W23, W7

0x41f7d0 SDIV	X6, X4, X25

0x41f7d4 ADD	W4, W26, W1

0x41f7d8 ADD	X1, X1, #2

0x41f7dc ADD	W5, W23, W6

0x41f7e0 SBFM	X20, X20, #0, #31

0x41f7e4 SBFM	X27, X5, #0, #31

0x41f7e8 MADD	X28, X9, X20, XZR

0x41f7ec MADD	X0, X11, X20, XZR

0x41f7f0 MADD	X5, X9, X27, XZR

0x41f7f4 ADD	X0, X10, X0,LSL #3

0x41f7f8 ADD	X30, X8, X5,LSL #3

0x41f7fc ADD	X5, X8, X28,LSL #3

0x41f800 MADD	X28, X11, X27, XZR

0x41f804 ADD	X28, X10, X28,LSL #3

0x41f808 MADD	W21, W2, W7, W4

0x41f80c ADD	W7, W22, W7

0x41f810 SBFM	X7, X7, #0, #31

0x41f814 ADD	W21, W21, #1

0x41f818 MADD	X7, X13, X7, XZR

0x41f81c SBFM	X21, X21, #61, #31

0x41f820 ADD	X0, X0, X21

0x41f824 ADD	X7, X12, X7,LSL #3

0x41f828 ADD	X5, X5, X21

0x41f82c MADD	W4, W2, W6, W4

0x41f830 ADD	W6, W22, W6

0x41f834 SBFM	X6, X6, #0, #31

0x41f838 MADD	X6, X13, X6, XZR

0x41f83c ADD	X6, X12, X6,LSL #3

0x41f840 LDR	D0, [X30, X4,SXTW #3]    [4]

0x41f844 LDR	D2, [X6, X4,SXTW #3]    [3]

0x41f848 MADD	X6, X13, X20, XZR

0x41f84c LDR	D1, [X28, X4,SXTW #3]    [10]

0x41f850 ADD	X6, X12, X6,LSL #3

0x41f854 ADD	X6, X6, X21

0x41f858 LD1	{V0.D[1]}, [X5]    [1]

0x41f85c LD1	{V1.D[1]}, [X0]    [8]

0x41f860 ADD	X0, X7, X21

0x41f864 LD1	{V2.D[1]}, [X0]    [7]

0x41f868 MADD	X0, X13, X27, XZR

0x41f86c ADD	X0, X12, X0,LSL #3

0x41f870 FMLA	V2.2D, V1.2D, V0.2D

0x41f874 LDR	D0, [X0, X4,SXTW #3]    [6]

0x41f878 MADD	X0, X15, X27, XZR

0x41f87c ADD	X0, X14, X0,LSL #3

0x41f880 LDR	D1, [X0, X4,SXTW #3]    [5]

0x41f884 LD1	{V0.D[1]}, [X6]    [2]

0x41f888 MADD	X6, X15, X20, XZR

0x41f88c ADD	X6, X14, X6,LSL #3

0x41f890 ADD	X6, X6, X21

0x41f894 LD1	{V1.D[1]}, [X6]    [9]

0x41f898 FSUB	V0.2D, V2.2D, V0.2D

0x41f89c FDIV	V0.2D, V0.2D, V1.2D

0x41f8a0 STR	D0, [X30, X4,SXTW #3]    [4]

0x41f8a4 ST1	{V0.D[1]}, [X5]    [1]

0x41f8a8 B.NE	41f7c0

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 219 - 221

--------------------------------------------------------------------------------

219:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

220:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

221:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i + 0, j - 1) - mom_flux(i, j)) / node_mass_post(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.50 - 6.72
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14 - 1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.36
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.22]
Source	advec_mom.cpp:219-221,context.h:69-69
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	3
CQA cycles	14.00 - 46.99
CQA cycles if no scalar integer	4.00 - 6.99
CQA cycles if FP arith vectorized	14.00 - 46.99
CQA cycles if fully vectorized	12.25 - 36.99
Front-end cycles	7.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.83
P3 cycles	5.75
P4 cycles	5.83
P5 cycles	5.83
P6 cycles	14.00
P7 cycles	5.75
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	13.50 - 46.99
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.57 - 0.17
Nb FLOP add-sub	2.00
Nb FLOP mul	0.00
Nb FLOP fma	2.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.21 - 7.43
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.00
Stride indirect	5.00
Vectorization ratio all	10.71
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	14.29
Vectorization ratio fma	33.33
Vectorization ratio div_sqrt	50.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	58.93
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	46.43
Vector-efficiency ratio fma	58.33
Vector-efficiency ratio div_sqrt	75.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	3.50 - 6.72
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14 - 1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.36
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.22]
Source	advec_mom.cpp:219-221,context.h:69-69
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	3
CQA cycles	14.00 - 46.99
CQA cycles if no scalar integer	4.00 - 6.99
CQA cycles if FP arith vectorized	14.00 - 46.99
CQA cycles if fully vectorized	12.25 - 36.99
Front-end cycles	7.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.83
P3 cycles	5.75
P4 cycles	5.83
P5 cycles	5.83
P6 cycles	14.00
P7 cycles	5.75
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	13.50 - 46.99
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.57 - 0.17
Nb FLOP add-sub	2.00
Nb FLOP mul	0.00
Nb FLOP fma	2.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.21 - 7.43
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.00
Stride indirect	5.00
Vectorization ratio all	10.71
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	14.29
Vectorization ratio fma	33.33
Vectorization ratio div_sqrt	50.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	58.93
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	46.43
Vector-efficiency ratio fma	58.33
Vector-efficiency ratio div_sqrt	75.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.22]
Source file and lines	advec_mom.cpp:219-221
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:219-221
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 3 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 46.99 to 6.99 cycles (6.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 46.99 to 36.99 cycles (1.27x speedup).

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
14% of VPU addition or subtraction instructions are used in vector version.
33% of VPU fused multiply-add instructions are used in vector version.
50% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (2 inside FMA instructions)
2: multiply (all inside FMA instructions)
2: divide

The binary loop is loading 80 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	5.83	5.75	5.83	5.83	14.00	5.75	2.50	2.50	2.50	2.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	5.83	5.75	5.83	5.83	14.00	5.75	2.50	2.50	2.50	2.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	13.50-46.99
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.38
Data deps.	1.00
Overall L1	14.00-46.99

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	33%
div/sqrt	50%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 46.99 cycles. At this rate:

1% of peak load performance is reached (1.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.51 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB X4, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X7, X1, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
SUBS X3, X3, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD W20, W23, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X6, X4, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD W4, W26, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W5, W23, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X20, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X27, X5, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X28, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X0, X11, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X5, X9, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X10, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X8, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X8, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X28, X11, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X28, X10, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W21, W2, W7, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W7, W22, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X7, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W21, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X7, X13, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
SBFM X21, X21, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD X0, X0, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X12, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X5, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W4, W2, W6, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W6, W22, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X6, X6, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X6, X13, X6, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X6, X12, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D0, [X30, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X6, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X6, X13, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D1, [X28, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X6, X12, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X6, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V0.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V1.D[1]}, [X0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X0, X7, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V2.D[1]}, [X0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X0, X13, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X12, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLA V2.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D0, [X0, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X0, X15, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X14, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X0, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LD1 {V0.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X6, X15, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X6, X14, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X6, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
FSUB V0.2D, V2.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FDIV V0.2D, V0.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
STR D0, [X30, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V0.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
B.NE 41f7c0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.22+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.22]
Source file and lines	advec_mom.cpp:219-221
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:219-221
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 3 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 46.99 to 6.99 cycles (6.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
14% of VPU addition or subtraction instructions are used in vector version.
33% of VPU fused multiply-add instructions are used in vector version.
50% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (2 inside FMA instructions)
2: multiply (all inside FMA instructions)
2: divide

The binary loop is loading 80 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	5.83	5.75	5.83	5.83	14.00	5.75	2.50	2.50	2.50	2.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	5.83	5.75	5.83	5.83	14.00	5.75	2.50	2.50	2.50	2.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	13.50-46.99
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.38
Data deps.	1.00
Overall L1	14.00-46.99

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	33%
div/sqrt	50%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 46.99 cycles. At this rate:

1% of peak load performance is reached (1.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.51 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB X4, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X7, X1, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
SUBS X3, X3, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD W20, W23, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X6, X4, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD W4, W26, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W5, W23, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X20, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X27, X5, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X28, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X0, X11, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X5, X9, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X10, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X8, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X8, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X28, X11, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X28, X10, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W21, W2, W7, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W7, W22, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X7, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W21, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X7, X13, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
SBFM X21, X21, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD X0, X0, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X12, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X5, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W4, W2, W6, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W6, W22, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X6, X6, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X6, X13, X6, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X6, X12, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D0, [X30, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X6, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X6, X13, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D1, [X28, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X6, X12, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X6, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V0.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V1.D[1]}, [X0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X0, X7, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V2.D[1]}, [X0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X0, X13, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X12, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLA V2.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D0, [X0, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X0, X15, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X14, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X0, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LD1 {V0.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X6, X15, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X6, X14, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X6, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
FSUB V0.2D, V2.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FDIV V0.2D, V0.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
STR D0, [X30, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V0.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
B.NE 41f7c0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.22+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code