OV - exec - Loop 194

	Loop Id: 194	Module: exec	Source: advec_mom.cpp:168-172 [...]	Coverage: 3.01%

0x41ef60 ADD	X2, X1, X3

0x41ef64 LDR	X18, [SP, #32]    [7]

0x41ef68 ADD	X7, X2, #1

0x41ef6c SDIV	X2, X2, X24

0x41ef70 ADD	W25, W18, W3

0x41ef74 ADD	X3, X3, #2

0x41ef78 ADD	W21, W22, W2

0x41ef7c SDIV	X20, X7, X24

0x41ef80 ADD	W19, W22, W20

0x41ef84 MADD	W30, W5, W2, W25

0x41ef88 SUB	W2, W21, #1

0x41ef8c SBFM	X27, X2, #0, #31

0x41ef90 ADD	W7, W30, #1

0x41ef94 MADD	X2, X9, X27, XZR

0x41ef98 ADD	X6, X8, X2,LSL #3

0x41ef9c MADD	W28, W5, W20, W25

0x41efa0 SUB	W20, W19, #1

0x41efa4 SBFM	X25, X20, #0, #31

0x41efa8 MADD	X20, X9, X25, XZR

0x41efac ADD	W26, W28, #2

0x41efb0 ADD	X2, X8, X20,LSL #3

0x41efb4 SBFM	X20, X26, #61, #31

0x41efb8 SBFM	X26, X21, #0, #31

0x41efbc SBFM	X21, X19, #0, #31

0x41efc0 LDR	D1, [X6, X7,SXTW #3]    [4]

0x41efc4 LDR	D3, [X6, X30,SXTW #3]    [4]

0x41efc8 MADD	X19, X9, X26, XZR

0x41efcc MADD	X18, X9, X21, XZR

0x41efd0 ADD	X4, X2, X20

0x41efd4 MADD	X6, X11, X26, XZR

0x41efd8 ADD	X19, X8, X19,LSL #3

0x41efdc ADD	X18, X8, X18,LSL #3

0x41efe0 ADD	X6, X10, X6,LSL #3

0x41efe4 LDR	D2, [X19, X7,SXTW #3]    [18]

0x41efe8 LDR	D16, [X6, X7,SXTW #3]    [3]

0x41efec LDR	D6, [X19, X30,SXTW #3]    [18]

0x41eff0 MADD	X19, X11, X21, XZR

0x41eff4 LDR	D7, [X6, X30,SXTW #3]    [3]

0x41eff8 ADD	X19, X10, X19,LSL #3

0x41effc LD1	{V1.D[1]}, [X4]    [21]

0x41f000 ADD	X4, X18, X20

0x41f004 ADD	X6, X19, X20

0x41f008 LD1	{V2.D[1]}, [X4]    [20]

0x41f00c MADD	X4, X11, X27, XZR

0x41f010 LD1	{V16.D[1]}, [X6]    [2]

0x41f014 ADD	X4, X10, X4,LSL #3

0x41f018 LDR	D4, [X4, X7,SXTW #3]    [19]

0x41f01c LDR	D5, [X4, X30,SXTW #3]    [19]

0x41f020 MADD	X4, X11, X25, XZR

0x41f024 ADD	X4, X10, X4,LSL #3

0x41f028 ADD	X6, X4, X20

0x41f02c LD1	{V4.D[1]}, [X6]    [1]

0x41f030 ADD	W6, W28, #1

0x41f034 SBFM	X6, X6, #61, #31

0x41f038 ADD	X2, X2, X6

0x41f03c ADD	X18, X18, X6

0x41f040 LD1	{V3.D[1]}, [X2]    [13]

0x41f044 ADD	X2, X4, X6

0x41f048 LD1	{V6.D[1]}, [X18]    [6]

0x41f04c ADD	X18, X19, X6

0x41f050 LD1	{V5.D[1]}, [X2]    [12]

0x41f054 LD1	{V7.D[1]}, [X18]    [5]

0x41f058 MADD	X18, X13, X26, XZR

0x41f05c ADD	X18, X12, X18,LSL #3

0x41f060 FMUL	V1.2D, V4.2D, V1.2D

0x41f064 FMLA	V1.2D, V16.2D, V2.2D

0x41f068 FMLA	V1.2D, V5.2D, V3.2D

0x41f06c FMLA	V1.2D, V7.2D, V6.2D

0x41f070 FMUL	V1.2D, V1.2D, V0.2D

0x41f074 STR	D1, [X18, X7,SXTW #3]    [17]

0x41f078 MADD	X18, X13, X21, XZR

0x41f07c ADD	X18, X12, X18,LSL #3

0x41f080 ADD	X18, X18, X20

0x41f084 ST1	{V1.D[1]}, [X18]    [16]

0x41f088 MADD	X18, X15, X27, XZR

0x41f08c ADD	X18, X14, X18,LSL #3

0x41f090 LDR	D2, [X18, X7,SXTW #3]    [15]

0x41f094 MADD	X18, X15, X25, XZR

0x41f098 ADD	X18, X14, X18,LSL #3

0x41f09c ADD	X18, X18, X20

0x41f0a0 LD1	{V2.D[1]}, [X18]    [14]

0x41f0a4 MADD	X18, X15, X26, XZR

0x41f0a8 ADD	X18, X14, X18,LSL #3

0x41f0ac LDR	D3, [X18, X7,SXTW #3]    [11]

0x41f0b0 MADD	X18, X15, X21, XZR

0x41f0b4 ADD	X18, X14, X18,LSL #3

0x41f0b8 ADD	X18, X18, X20

0x41f0bc FSUB	V1.2D, V1.2D, V2.2D

0x41f0c0 LD1	{V3.D[1]}, [X18]    [10]

0x41f0c4 MADD	X18, X17, X26, XZR

0x41f0c8 ADD	X18, X16, X18,LSL #3

0x41f0cc FADD	V1.2D, V1.2D, V3.2D

0x41f0d0 STR	D1, [X18, X7,SXTW #3]    [9]

0x41f0d4 MADD	X18, X17, X21, XZR

0x41f0d8 ADD	X18, X16, X18,LSL #3

0x41f0dc ADD	X18, X18, X20

0x41f0e0 ST1	{V1.D[1]}, [X18]    [8]

0x41f0e4 LDR	X18, [SP, #40]    [7]

0x41f0e8 CMP	X18, X3

0x41f0ec B.NE	41ef60

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 168 - 172

--------------------------------------------------------------------------------

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.22 - 4.44
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.10 - 1.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60 - 2.00
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.18]
Source	advec_mom.cpp:168-172,context.h:69-69
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	3
CQA cycles	20.00 - 40.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	20.00 - 40.00
CQA cycles if fully vectorized	18.25 - 30.00
Front-end cycles	12.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	9.17
P3 cycles	9.25
P4 cycles	9.17
P5 cycles	9.17
P6 cycles	20.00
P7 cycles	9.25
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	5.25
P11 cycles	5.25
P12 cycles	8.67
P13 cycles	8.67
P14 cycles	8.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	100.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	1.00 - 0.50
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.60 - 11.20
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	48.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	8.00
Vectorization ratio all	16.28
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	33.33
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	61.05
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	75.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	2.22 - 4.44
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.10 - 1.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60 - 2.00
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.18]
Source	advec_mom.cpp:168-172,context.h:69-69
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	3
CQA cycles	20.00 - 40.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	20.00 - 40.00
CQA cycles if fully vectorized	18.25 - 30.00
Front-end cycles	12.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	9.17
P3 cycles	9.25
P4 cycles	9.17
P5 cycles	9.17
P6 cycles	20.00
P7 cycles	9.25
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	5.25
P11 cycles	5.25
P12 cycles	8.67
P13 cycles	8.67
P14 cycles	8.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	100.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	1.00 - 0.50
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.60 - 11.20
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	48.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	8.00
Vectorization ratio all	16.28
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	33.33
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	61.05
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	75.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.18]
Source file and lines	advec_mom.cpp:168-172
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168-172
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 3 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 9.00 cycles (4.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 61% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 40.00 to 30.00 cycles (1.33x speedup).

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
33% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

10: addition or subtraction (6 inside FMA instructions)
10: multiply (6 inside FMA instructions)

The binary loop is loading 176 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	100
loop length	400
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	9.17	9.25	9.17	9.17	20.00	9.25	5.25	5.25	5.25	5.25	8.67	8.67	8.67	0.00	0.00
cycles	0.50	0.50	9.17	9.25	9.17	9.17	20.00	9.25	5.25	5.25	5.25	5.25	8.67	8.67	8.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.50
Data deps.	1.00
Overall L1	20.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	0%
store	0%
mul	100%
add-sub	33%
fma	60%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

4% of peak load performance is reached (4.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ef60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X2, X1, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X18, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X7, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X2, X2, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD W25, W18, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X3, X3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W21, W22, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X20, X7, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD W19, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W30, W5, W2, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SUB W2, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X27, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W7, W30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X2, X9, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X6, X8, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W28, W5, W20, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W20, W19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X25, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X20, X9, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD W26, W28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X2, X8, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X20, X26, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X26, X21, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X21, X19, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR D1, [X6, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X6, X30,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X19, X9, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X18, X9, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X2, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X6, X11, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X19, X8, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X8, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X10, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D2, [X19, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D16, [X6, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D6, [X19, X30,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X19, X11, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D7, [X6, X30,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X19, X10, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X4]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X4, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X19, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V2.D[1]}, [X4]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X4, X11, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LD1 {V16.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X4, X10, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D4, [X4, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D5, [X4, X30,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X4, X11, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X10, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X4, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V4.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD W6, W28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X6, X6, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X2, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V3.D[1]}, [X2]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X2, X4, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V6.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X18, X19, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V5.D[1]}, [X2]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V7.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X18, X13, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X12, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V1.2D, V4.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V1.2D, V16.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V1.2D, V5.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V1.2D, V7.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V1.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D1, [X18, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X18, X13, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X12, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1 {V1.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
MADD X18, X15, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X14, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D2, [X18, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X18, X15, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X14, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V2.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X18, X15, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X14, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D3, [X18, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X18, X15, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X14, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FSUB V1.2D, V1.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1 {V3.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X18, X17, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X16, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD V1.2D, V1.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR D1, [X18, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X18, X17, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X16, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1 {V1.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDR X18, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X18, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41ef60 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.18]
Source file and lines	advec_mom.cpp:168-172
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168-172
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 3 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 9.00 cycles (4.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
33% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

10: addition or subtraction (6 inside FMA instructions)
10: multiply (6 inside FMA instructions)

The binary loop is loading 176 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	100
loop length	400
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	9.17	9.25	9.17	9.17	20.00	9.25	5.25	5.25	5.25	5.25	8.67	8.67	8.67	0.00	0.00
cycles	0.50	0.50	9.17	9.25	9.17	9.17	20.00	9.25	5.25	5.25	5.25	5.25	8.67	8.67	8.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.50
Data deps.	1.00
Overall L1	20.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	0%
store	0%
mul	100%
add-sub	33%
fma	60%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

4% of peak load performance is reached (4.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ef60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X2, X1, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X18, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X7, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X2, X2, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD W25, W18, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X3, X3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W21, W22, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X20, X7, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD W19, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W30, W5, W2, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SUB W2, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X27, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W7, W30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X2, X9, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X6, X8, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W28, W5, W20, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W20, W19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X25, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X20, X9, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD W26, W28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X2, X8, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X20, X26, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X26, X21, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X21, X19, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR D1, [X6, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X6, X30,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X19, X9, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X18, X9, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X2, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X6, X11, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X19, X8, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X8, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X10, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D2, [X19, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D16, [X6, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D6, [X19, X30,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X19, X11, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D7, [X6, X30,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X19, X10, X19,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X4]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X4, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X19, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V2.D[1]}, [X4]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X4, X11, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LD1 {V16.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X4, X10, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D4, [X4, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D5, [X4, X30,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X4, X11, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X10, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X4, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V4.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD W6, W28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X6, X6, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X2, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V3.D[1]}, [X2]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X2, X4, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V6.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X18, X19, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V5.D[1]}, [X2]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V7.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X18, X13, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X12, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V1.2D, V4.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V1.2D, V16.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V1.2D, V5.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V1.2D, V7.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V1.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D1, [X18, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X18, X13, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X12, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1 {V1.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
MADD X18, X15, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X14, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D2, [X18, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X18, X15, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X14, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V2.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X18, X15, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X14, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D3, [X18, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X18, X15, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X14, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FSUB V1.2D, V1.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1 {V3.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X18, X17, X26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X16, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD V1.2D, V1.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR D1, [X18, X7,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X18, X17, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X16, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1 {V1.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDR X18, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X18, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41ef60 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code