OV - exec - Loop 180

	Loop Id: 180	Module: exec	Source: advec_mom.cpp:72-75 [...]	Coverage: 2.12%

0x41dc40 ADD	X6, X18, X1

0x41dc44 ADD	W25, W5, W1

0x41dc48 ADD	W26, W4, W1

0x41dc4c ADD	X1, X1, #2

0x41dc50 ADD	X7, X6, #1

0x41dc54 SDIV	X6, X6, X24

0x41dc58 ADD	W20, W23, W6

0x41dc5c SDIV	X7, X7, X24

0x41dc60 SBFM	X20, X20, #0, #31

0x41dc64 ADD	W21, W23, W7

0x41dc68 MADD	X27, X9, X20, XZR

0x41dc6c SBFM	X21, X21, #0, #31

0x41dc70 MADD	X28, X9, X21, XZR

0x41dc74 ADD	X27, X8, X27,LSL #3

0x41dc78 ADD	X28, X8, X28,LSL #3

0x41dc7c MADD	W25, W3, W6, W25

0x41dc80 LDR	D0, [X27, X25,SXTW #3]    [8]

0x41dc84 MADD	X27, X11, X20, XZR

0x41dc88 ADD	X27, X10, X27,LSL #3

0x41dc8c MADD	W7, W3, W7, W26

0x41dc90 SBFM	X30, X7, #61, #31

0x41dc94 LDR	D1, [X28, X30]    [9]

0x41dc98 ADD	W7, W7, #1

0x41dc9c STR	D0, [X27, X25,SXTW #3]    [7]

0x41dca0 MADD	X27, X11, X21, XZR

0x41dca4 MOV	V0.D[1], V1.D[0]

0x41dca8 ADD	X27, X10, X27,LSL #3

0x41dcac STR	D1, [X27, X30]    [6]

0x41dcb0 MADD	X27, X13, X21, XZR

0x41dcb4 ADD	X27, X12, X27,LSL #3

0x41dcb8 ADD	X7, X27, W7,SXTW #3

0x41dcbc MADD	W6, W3, W6, W26

0x41dcc0 MADD	X26, X13, X20, XZR

0x41dcc4 ADD	X26, X12, X26,LSL #3

0x41dcc8 LDR	D1, [X26, X6,SXTW #3]    [5]

0x41dccc LDR	D2, [X26, X25,SXTW #3]    [5]

0x41dcd0 ADD	X6, X27, X30

0x41dcd4 LD1	{V1.D[1]}, [X7]    [4]

0x41dcd8 LD1	{V2.D[1]}, [X6]    [2]

0x41dcdc MADD	X7, X15, X21, XZR

0x41dce0 MADD	X6, X15, X20, XZR

0x41dce4 ADD	X7, X14, X7,LSL #3

0x41dce8 ADD	X6, X14, X6,LSL #3

0x41dcec ADD	X7, X7, X30

0x41dcf0 FADD	V0.2D, V1.2D, V0.2D

0x41dcf4 FSUB	V0.2D, V0.2D, V2.2D

0x41dcf8 STR	D0, [X6, X25,SXTW #3]    [1]

0x41dcfc ST1	{V0.D[1]}, [X7]    [3]

0x41dd00 CMP	X2, X1

0x41dd04 B.NE	41dc40

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 72 - 75

--------------------------------------------------------------------------------

72:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

73:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

74:         post_vol(i, j) = volume(i, j);

75:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.90 - 12.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.08
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.6]
Source	advec_mom.cpp:72-75,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	13.00 - 40.00
CQA cycles if no scalar integer	3.33
CQA cycles if FP arith vectorized	13.00 - 40.00
CQA cycles if fully vectorized	13.00 - 40.00
Front-end cycles	6.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	4.67
P5 cycles	4.50
P6 cycles	13.00
P7 cycles	4.50
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	2.25
P11 cycles	2.25
P12 cycles	3.33
P13 cycles	3.33
P14 cycles	3.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.31 - 0.10
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.20 - 6.77
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	40.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	6.00
Vectorization ratio all	11.76
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	58.82
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	83.33

Metric	Value
CQA speedup if no scalar integer	3.90 - 12.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.08
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.6]
Source	advec_mom.cpp:72-75,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	13.00 - 40.00
CQA cycles if no scalar integer	3.33
CQA cycles if FP arith vectorized	13.00 - 40.00
CQA cycles if fully vectorized	13.00 - 40.00
Front-end cycles	6.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	4.67
P5 cycles	4.50
P6 cycles	13.00
P7 cycles	4.50
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	2.25
P11 cycles	2.25
P12 cycles	3.33
P13 cycles	3.33
P14 cycles	3.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.31 - 0.10
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.20 - 6.77
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	40.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	6.00
Vectorization ratio all	11.76
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	58.82
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	83.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.6]
Source file and lines	advec_mom.cpp:72-75
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 3.33 cycles (12.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 58% of vector register length is used (average across all VPU instructions).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary loop is loading 48 bytes. The binary loop is storing 40 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	4.67	4.67	4.67	4.50	13.00	4.50	2.25	2.25	2.25	2.25	3.33	3.33	3.33	0.00	0.00
cycles	0.50	0.50	4.67	4.67	4.67	4.50	13.00	4.50	2.25	2.25	2.25	2.25	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.25
Data deps.	1.00
Overall L1	13.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dc40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X6, X18, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W25, W5, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W26, W4, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X6, X6, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD W20, W23, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X7, X7, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X20, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W21, W23, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X27, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X21, X21, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X28, X9, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X27, X8, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X8, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W25, W3, W6, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X27, X25,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X27, X11, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X27, X10, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W7, W3, W7, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X30, X7, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X28, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD W7, W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X27, X25,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X27, X11, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MOV V0.D[1], V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X27, X10, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D1, [X27, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X27, X13, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X27, X12, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X27, W7,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
MADD W6, W3, W6, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X26, X13, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X26, X12, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X26, X6,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X26, X25,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X6, X27, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X7]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V2.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X7, X15, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X6, X15, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X7, X14, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X14, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X7, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V0.2D, V0.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR D0, [X6, X25,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V0.D[1]}, [X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41dc40 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.6]
Source file and lines	advec_mom.cpp:72-75
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 58% of vector register length is used (average across all VPU instructions).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary loop is loading 48 bytes. The binary loop is storing 40 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	4.67	4.67	4.67	4.50	13.00	4.50	2.25	2.25	2.25	2.25	3.33	3.33	3.33	0.00	0.00
cycles	0.50	0.50	4.67	4.67	4.67	4.50	13.00	4.50	2.25	2.25	2.25	2.25	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.25
Data deps.	1.00
Overall L1	13.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dc40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X6, X18, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W25, W5, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W26, W4, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X6, X6, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD W20, W23, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X7, X7, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X20, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W21, W23, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X27, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X21, X21, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X28, X9, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X27, X8, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X8, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W25, W3, W6, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X27, X25,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X27, X11, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X27, X10, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W7, W3, W7, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X30, X7, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X28, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD W7, W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X27, X25,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X27, X11, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MOV V0.D[1], V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X27, X10, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D1, [X27, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X27, X13, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X27, X12, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X27, W7,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
MADD W6, W3, W6, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X26, X13, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X26, X12, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X26, X6,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X26, X25,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X6, X27, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X7]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V2.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X7, X15, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X6, X15, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X7, X14, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X14, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X7, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V0.2D, V0.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR D0, [X6, X25,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V0.D[1]}, [X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41dc40 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code