OV - exec - Loop 167

	Loop Id: 167	Module: exec	Source: advec_cell.cpp:147-150 [...]	Coverage: 1.10%

0x41c2e0 SDIV	X5, X18, X25

0x41c2e4 ADD	X4, X18, #1

0x41c2e8 SUBS	X3, X3, #2

0x41c2ec ADD	W7, W23, W5

0x41c2f0 SDIV	X6, X4, X25

0x41c2f4 ADD	W4, W24, W18

0x41c2f8 SBFM	X7, X7, #0, #31

0x41c2fc ADD	W20, W23, W6

0x41c300 MADD	X27, X9, X7, XZR

0x41c304 SBFM	X20, X20, #0, #31

0x41c308 MADD	X28, X9, X20, XZR

0x41c30c ADD	X27, X8, X27,LSL #3

0x41c310 ADD	X28, X8, X28,LSL #3

0x41c314 MADD	W21, W2, W5, W4

0x41c318 LDR	D0, [X27, X21,SXTW #3]    [10]

0x41c31c ADD	W4, W26, W18

0x41c320 ADD	X18, X18, #2

0x41c324 MADD	W4, W2, W6, W4

0x41c328 SBFM	X30, X4, #61, #31

0x41c32c ADD	X1, X28, X30

0x41c330 LD1	{V0.D[1]}, [X1]    [9]

0x41c334 ADD	W1, W22, W5

0x41c338 ADD	W5, W22, W6

0x41c33c SBFM	X1, X1, #0, #31

0x41c340 SBFM	X5, X5, #0, #31

0x41c344 MADD	X1, X11, X1, XZR

0x41c348 MADD	X5, X11, X5, XZR

0x41c34c ADD	X1, X10, X1,LSL #3

0x41c350 ADD	X5, X10, X5,LSL #3

0x41c354 ADD	X5, X5, X30

0x41c358 LDR	D1, [X1, X21,SXTW #3]    [8]

0x41c35c MADD	X1, X11, X7, XZR

0x41c360 ADD	X1, X10, X1,LSL #3

0x41c364 LD1	{V1.D[1]}, [X5]    [1]

0x41c368 MADD	X5, X11, X20, XZR

0x41c36c ADD	X5, X10, X5,LSL #3

0x41c370 ADD	X5, X5, X30

0x41c374 FADD	V0.2D, V1.2D, V0.2D

0x41c378 LDR	D1, [X1, X21,SXTW #3]    [5]

0x41c37c MADD	X1, X13, X7, XZR

0x41c380 ADD	X1, X12, X1,LSL #3

0x41c384 LD1	{V1.D[1]}, [X5]    [7]

0x41c388 MADD	X5, X13, X20, XZR

0x41c38c ADD	X5, X12, X5,LSL #3

0x41c390 FSUB	V0.2D, V0.2D, V1.2D

0x41c394 STR	D0, [X1, X21,SXTW #3]    [4]

0x41c398 ADD	X1, X5, X30

0x41c39c MADD	X5, X15, X20, XZR

0x41c3a0 ST1	{V0.D[1]}, [X1]    [3]

0x41c3a4 MADD	X1, X15, X7, XZR

0x41c3a8 LDR	D0, [X27, X21,SXTW #3]    [10]

0x41c3ac LDR	D1, [X28, X4,SXTW #3]    [11]

0x41c3b0 ADD	X5, X14, X5,LSL #3

0x41c3b4 ADD	X1, X14, X1,LSL #3

0x41c3b8 STR	D0, [X1, X21,SXTW #3]    [2]

0x41c3bc STR	D1, [X5, X4,SXTW #3]    [6]

0x41c3c0 B.NE	41c2e0

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 147 - 150

--------------------------------------------------------------------------------

147:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

148:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

149:           pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

150:           post_vol(i, j) = volume(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.50 - 10.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.04 - 1.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.86
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.10]
Source	advec_cell.cpp:147-150,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	14.00 - 40.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	14.00 - 40.00
CQA cycles if fully vectorized	13.50 - 30.00
Front-end cycles	7.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.67
P3 cycles	5.58
P4 cycles	5.67
P5 cycles	5.50
P6 cycles	14.00
P7 cycles	5.58
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	2.25
P11 cycles	2.25
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.29 - 0.10
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.60 - 7.43
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	40.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	7.00
Vectorization ratio all	9.09
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	33.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	59.09
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	58.33
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	3.50 - 10.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.04 - 1.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.86
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.10]
Source	advec_cell.cpp:147-150,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	14.00 - 40.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	14.00 - 40.00
CQA cycles if fully vectorized	13.50 - 30.00
Front-end cycles	7.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.67
P3 cycles	5.58
P4 cycles	5.67
P5 cycles	5.50
P6 cycles	14.00
P7 cycles	5.58
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	2.25
P11 cycles	2.25
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.29 - 0.10
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.60 - 7.43
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	40.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	7.00
Vectorization ratio all	9.09
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	33.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	59.09
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	58.33
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.10]
Source file and lines	advec_cell.cpp:147-150
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:147-150
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 4.00 cycles (10.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 59% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 40.00 to 30.00 cycles (1.33x speedup).

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
33% of VPU addition or subtraction instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary loop is loading 64 bytes. The binary loop is storing 40 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	5.67	5.58	5.67	5.50	14.00	5.58	2.25	2.25	2.25	2.25	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	5.67	5.58	5.67	5.50	14.00	5.58	2.25	2.25	2.25	2.25	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.13
Data deps.	1.00
Overall L1	14.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c2e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SDIV X5, X18, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD X4, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X3, X3, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD W7, W23, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X6, X4, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD W4, W24, W18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X7, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W20, W23, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X27, X9, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X20, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X28, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X27, X8, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X8, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W21, W2, W5, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X27, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD W4, W26, W18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W4, W2, W6, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X30, X4, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD X1, X28, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V0.D[1]}, [X1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD W1, W22, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W5, W22, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X1, X1, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X5, X5, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X1, X11, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X5, X11, X5, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X10, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X10, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X1, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X1, X11, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X10, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X5, X11, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X10, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D1, [X1, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X1, X13, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X12, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X5, X13, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X12, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FSUB V0.2D, V0.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR D0, [X1, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X5, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X5, X15, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ST1 {V0.D[1]}, [X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
MADD X1, X15, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X27, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X28, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X5, X14, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X14, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X1, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D1, [X5, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B.NE 41c2e0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.10+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.10]
Source file and lines	advec_cell.cpp:147-150
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:147-150
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
33% of VPU addition or subtraction instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary loop is loading 64 bytes. The binary loop is storing 40 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	5.67	5.58	5.67	5.50	14.00	5.58	2.25	2.25	2.25	2.25	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	5.67	5.58	5.67	5.50	14.00	5.58	2.25	2.25	2.25	2.25	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.13
Data deps.	1.00
Overall L1	14.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c2e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SDIV X5, X18, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD X4, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X3, X3, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD W7, W23, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV X6, X4, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD W4, W24, W18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X7, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W20, W23, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X27, X9, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X20, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X28, X9, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X27, X8, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X8, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W21, W2, W5, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X27, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD W4, W26, W18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W4, W2, W6, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X30, X4, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD X1, X28, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V0.D[1]}, [X1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD W1, W22, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W5, W22, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X1, X1, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X5, X5, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X1, X11, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X5, X11, X5, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X10, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X10, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X1, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X1, X11, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X10, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X5, X11, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X10, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D1, [X1, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X1, X13, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X12, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V1.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X5, X13, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X12, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FSUB V0.2D, V0.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR D0, [X1, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X5, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X5, X15, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ST1 {V0.D[1]}, [X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
MADD X1, X15, X7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X27, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X28, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X5, X14, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X14, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X1, X21,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D1, [X5, X4,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B.NE 41c2e0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.10+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code