OV - exec - Loop 159

	Loop Id: 159	Module: exec	Source: advec_cell.cpp:66-110 [...]	Coverage: 3.26%

0x41b600 LDUR	X8, [X29, #456]    [21]

0x41b604 ORR	X11, XZR, X26

0x41b608 ORR	X17, XZR, X30

0x41b60c ORR	X18, XZR, X15

0x41b610 LDR	X1, [SP, #72]    [6]

0x41b614 ADD	X10, X8, X7

0x41b618 LDR	X8, [SP, #40]    [6]

0x41b61c SDIV	X5, X10, X26

0x41b620 ADD	X2, X10, #1

0x41b624 ADD	W6, W22, W5

0x41b628 SDIV	X2, X2, X26

0x41b62c ADD	W19, W22, W2

0x41b630 SBFM	X30, X6, #0, #31

0x41b634 SBFM	X27, X19, #0, #31

0x41b638 MADD	X23, X15, X27, XZR

0x41b63c MADD	W20, W21, W5, W10

0x41b640 MADD	W10, W21, W2, W10

0x41b644 ADD	W10, W10, #1

0x41b648 FMOV	S7, W20

0x41b64c MOV	V7.S[1], W10

0x41b650 ADD	W10, W8, W7

0x41b654 LDR	X8, [SP, #48]    [6]

0x41b658 ADD	X7, X7, #2

0x41b65c ADD	X24, X8, X23,LSL #3

0x41b660 ADD	V7.2S, V1.2S, V7.2S

0x41b664 SSHLL	V7.2D, V7.2S, #32

0x41b668 MADD	W5, W21, W5, W10

0x41b66c ADD	W26, W5, #1

0x41b670 MADD	W10, W21, W2, W10

0x41b674 SBFM	X2, X26, #0, #31

0x41b678 ADD	W10, W10, #2

0x41b67c SBFM	X5, X10, #0, #31

0x41b680 SBFM	X28, X10, #61, #31

0x41b684 FMOV	D18, X2

0x41b688 MADD	X2, X12, X30, XZR

0x41b68c ADD	X2, X9, X2,LSL #3

0x41b690 LDR	D16, [X2, X26,SXTW #3]    [13]

0x41b694 MADD	X2, X16, X27, XZR

0x41b698 FMOV	S17, W26

0x41b69c MOV	V18.D[1], X5

0x41b6a0 MADD	X5, X12, X27, XZR

0x41b6a4 ADD	X5, X9, X5,LSL #3

0x41b6a8 MOV	V17.S[1], W10

0x41b6ac ADD	X10, X5, X28

0x41b6b0 ADD	X5, X14, X2,LSL #3

0x41b6b4 ADD	V20.2S, V17.2S, V2.2S

0x41b6b8 ADD	V17.2S, V17.2S, V3.2S

0x41b6bc SMIN	V20.2S, V0.2S, V20.2S

0x41b6c0 SSHLL	V17.2D, V17.2S, #32

0x41b6c4 LD1	{V16.D[1]}, [X10]    [16]

0x41b6c8 MADD	X10, X16, X30, XZR

0x41b6cc SSHLL	V20.2D, V20.2S, #32

0x41b6d0 ADD	X19, X14, X10,LSL #3

0x41b6d4 FCMGT	V19.2D, V16.2D, #0

0x41b6d8 FABS	V22.2D, V16.2D

0x41b6dc ORR	V21.16B, V19.16B, V19.16B

0x41b6e0 BIF	V17.16B, V20.16B, V19.16B

0x41b6e4 BSL	V21.16B, V18.16B, V7.16B

0x41b6e8 BIT	V18.16B, V7.16B, V19.16B

0x41b6ec BIF	V7.16B, V20.16B, V19.16B

0x41b6f0 LDR	D19, [X13, X26,SXTW #3]    [10]

0x41b6f4 FMOV	X2, D18

0x41b6f8 MOV	X10, V18.D[1]

0x41b6fc FMOV	X20, D7

0x41b700 LDR	D18, [X19, X2,LSL #3]    [20]

0x41b704 ADD	X6, X5, X10,LSL #3

0x41b708 ADD	X5, X13, X28

0x41b70c ADD	X25, X24, X10,LSL #3

0x41b710 LD1	{V19.D[1]}, [X5]    [19]

0x41b714 MOV	X5, V7.D[1]

0x41b718 LDR	D7, [X13, X20,LSL #3]    [10]

0x41b71c ADD	X5, X13, X5,LSL #3

0x41b720 LD1	{V18.D[1]}, [X6]    [4]

0x41b724 LD1	{V7.D[1]}, [X5]    [18]

0x41b728 MADD	X5, X15, X30, XZR

0x41b72c ORR	X15, XZR, X14

0x41b730 ORR	X14, XZR, X12

0x41b734 ORR	X12, XZR, X9

0x41b738 ORR	W9, WZR, W22

0x41b73c FMOV	X22, D17

0x41b740 ADD	X20, X8, X5,LSL #3

0x41b744 MOV	X5, V17.D[1]

0x41b748 FMOV	X8, D21

0x41b74c LDR	D20, [X20, X2,LSL #3]    [7]

0x41b750 ADD	X23, X24, X5,LSL #3

0x41b754 FDIV	V18.2D, V22.2D, V18.2D

0x41b758 LD1	{V20.D[1]}, [X25]    [17]

0x41b75c FMLA	V19.2D, V19.2D, V18.2D

0x41b760 FSUB	V17.2D, V5.2D, V18.2D

0x41b764 FSUB	V18.2D, V4.2D, V18.2D

0x41b768 FNEG	V24.2D, V18.2D

0x41b76c FDIV	V7.2D, V19.2D, V7.2D

0x41b770 LDR	D19, [X20, X22,LSL #3]    [7]

0x41b774 LD1	{V19.D[1]}, [X23]    [11]

0x41b778 MOV	X23, V21.D[1]

0x41b77c LDR	D21, [X20, X8,LSL #3]    [7]

0x41b780 ADD	X24, X24, X23,LSL #3

0x41b784 LD1	{V21.D[1]}, [X24]    [12]

0x41b788 MADD	X24, X1, X30, XZR

0x41b78c FSUB	V22.2D, V20.2D, V19.2D

0x41b790 FABD	V19.2D, V20.2D, V19.2D

0x41b794 ADD	X24, X0, X24,LSL #3

0x41b798 FSUB	V23.2D, V21.2D, V20.2D

0x41b79c FABD	V21.2D, V21.2D, V20.2D

0x41b7a0 FMINNM	V25.2D, V19.2D, V21.2D

0x41b7a4 FMUL	V19.2D, V19.2D, V7.2D

0x41b7a8 FMUL	V22.2D, V23.2D, V22.2D

0x41b7ac FCMGT	V23.2D, V23.2D, #0

0x41b7b0 FMLA	V19.2D, V21.2D, V17.2D

0x41b7b4 BIF	V18.16B, V24.16B, V23.16B

0x41b7b8 FCMLE	V22.2D, V22.2D, #0

0x41b7bc FMUL	V19.2D, V19.2D, V6.2D

0x41b7c0 FMINNM	V19.2D, V25.2D, V19.2D

0x41b7c4 FMUL	V18.2D, V19.2D, V18.2D

0x41b7c8 BIC	V18.16B, V18.16B, V22.16B

0x41b7cc FADD	V18.2D, V18.2D, V20.2D

0x41b7d0 FMUL	V16.2D, V18.2D, V16.2D

0x41b7d4 STR	D16, [X24, X26,SXTW #3]    [3]

0x41b7d8 MADD	X24, X1, X27, XZR

0x41b7dc LDR	X1, [SP, #64]    [6]

0x41b7e0 FABS	V25.2D, V16.2D

0x41b7e4 ADD	X24, X0, X24,LSL #3

0x41b7e8 ADD	X24, X24, X28

0x41b7ec ST1	{V16.D[1]}, [X24]    [2]

0x41b7f0 MADD	X24, X3, X30, XZR

0x41b7f4 LDR	D21, [X20, X2,LSL #3]    [7]

0x41b7f8 LDR	D22, [X19, X2,LSL #3]    [20]

0x41b7fc ADD	X24, X1, X24,LSL #3

0x41b800 LDR	D20, [X24, X2,LSL #3]    [1]

0x41b804 LDR	D18, [X24, X22,LSL #3]    [1]

0x41b808 LDR	D19, [X24, X8,LSL #3]    [1]

0x41b80c MADD	X8, X3, X27, XZR

0x41b810 ORR	W22, WZR, W9

0x41b814 ORR	X9, XZR, X12

0x41b818 ORR	X12, XZR, X14

0x41b81c ORR	X14, XZR, X15

0x41b820 ORR	X15, XZR, X18

0x41b824 LDUR	X18, [X29, #464]    [21]

0x41b828 ADD	X8, X1, X8,LSL #3

0x41b82c ADD	X10, X8, X10,LSL #3

0x41b830 LD1	{V21.D[1]}, [X25]    [17]

0x41b834 LD1	{V22.D[1]}, [X6]    [4]

0x41b838 LD1	{V20.D[1]}, [X10]    [15]

0x41b83c ADD	X10, X8, X5,LSL #3

0x41b840 ADD	X8, X8, X23,LSL #3

0x41b844 LD1	{V18.D[1]}, [X10]    [14]

0x41b848 LD1	{V19.D[1]}, [X8]    [9]

0x41b84c MADD	X8, X18, X30, XZR

0x41b850 ORR	X30, XZR, X17

0x41b854 ADD	X8, X17, X8,LSL #3

0x41b858 FMUL	V21.2D, V22.2D, V21.2D

0x41b85c FDIV	V21.2D, V25.2D, V21.2D

0x41b860 FSUB	V23.2D, V20.2D, V18.2D

0x41b864 FABD	V18.2D, V20.2D, V18.2D

0x41b868 FSUB	V24.2D, V19.2D, V20.2D

0x41b86c FABD	V19.2D, V19.2D, V20.2D

0x41b870 FMUL	V7.2D, V18.2D, V7.2D

0x41b874 FMUL	V23.2D, V24.2D, V23.2D

0x41b878 FCMGT	V24.2D, V24.2D, #0

0x41b87c FMLA	V7.2D, V19.2D, V17.2D

0x41b880 FCMLE	V17.2D, V23.2D, #0

0x41b884 FMUL	V7.2D, V7.2D, V6.2D

0x41b888 FSUB	V21.2D, V4.2D, V21.2D

0x41b88c FNEG	V22.2D, V21.2D

0x41b890 BIF	V21.16B, V22.16B, V24.16B

0x41b894 FMINNM	V22.2D, V18.2D, V19.2D

0x41b898 FMINNM	V7.2D, V22.2D, V7.2D

0x41b89c FMUL	V7.2D, V21.2D, V7.2D

0x41b8a0 BIC	V7.16B, V7.16B, V17.16B

0x41b8a4 FADD	V7.2D, V7.2D, V20.2D

0x41b8a8 FMUL	V7.2D, V7.2D, V16.2D

0x41b8ac STR	D7, [X8, X26,SXTW #3]    [8]

0x41b8b0 MADD	X8, X18, X27, XZR

0x41b8b4 ORR	X26, XZR, X11

0x41b8b8 ADD	X8, X17, X8,LSL #3

0x41b8bc ADD	X8, X8, X28

0x41b8c0 ST1	{V7.D[1]}, [X8]    [5]

0x41b8c4 LDUR	X8, [X29, #448]    [21]

0x41b8c8 CMP	X8, X7

0x41b8cc B.NE	41b600

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 66 - 110

--------------------------------------------------------------------------------

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.08 - 2.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01 - 2.71
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.4]
Source	advec_cell.cpp:66-110,context.h:46-46,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.50 - 60.98
CQA cycles if no scalar integer	20.75 - 20.98
CQA cycles if FP arith vectorized	22.50 - 60.98
CQA cycles if fully vectorized	21.00 - 60.98
Front-end cycles	22.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	10.67
P3 cycles	10.58
P4 cycles	10.67
P5 cycles	10.50
P6 cycles	21.00
P7 cycles	10.58
P8 cycles	22.25
P9 cycles	22.25
P10 cycles	22.25
P11 cycles	22.25
P12 cycles	11.67
P13 cycles	11.67
P14 cycles	11.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	20.49 - 60.98
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	180.00
Nb uops	180.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.58 - 0.95
Nb FLOP add-sub	18.00
Nb FLOP mul	22.00
Nb FLOP fma	6.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.85 - 13.16
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	48.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	7.00
Vectorization ratio all	49.58
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.85
Vector-efficiency ratio all	72.06
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	72.46

Metric	Value
CQA speedup if no scalar integer	1.08 - 2.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01 - 2.71
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.4]
Source	advec_cell.cpp:66-110,context.h:46-46,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.50 - 60.98
CQA cycles if no scalar integer	20.75 - 20.98
CQA cycles if FP arith vectorized	22.50 - 60.98
CQA cycles if fully vectorized	21.00 - 60.98
Front-end cycles	22.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	10.67
P3 cycles	10.58
P4 cycles	10.67
P5 cycles	10.50
P6 cycles	21.00
P7 cycles	10.58
P8 cycles	22.25
P9 cycles	22.25
P10 cycles	22.25
P11 cycles	22.25
P12 cycles	11.67
P13 cycles	11.67
P14 cycles	11.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	20.49 - 60.98
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	180.00
Nb uops	180.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.58 - 0.95
Nb FLOP add-sub	18.00
Nb FLOP mul	22.00
Nb FLOP fma	6.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.85 - 13.16
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	48.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	7.00
Vectorization ratio all	49.58
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.85
Vector-efficiency ratio all	72.06
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	72.46

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.4]
Source file and lines	advec_cell.cpp:66-110
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66-110
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 60.98 to 20.98 cycles (2.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 72% of vector register length is used (average across all VPU instructions).

Details

49% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58 FP arithmetical operations:

24: addition or subtraction (6 inside FMA instructions)
28: multiply (6 inside FMA instructions)
6: divide

The binary loop is loading 248 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	180
loop length	720
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

22.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	10.67	10.58	10.67	10.50	21.00	10.58	22.25	22.25	22.25	22.25	11.67	11.67	11.67	0.00	0.00
cycles	0.50	0.50	10.67	10.58	10.67	10.50	21.00	10.58	22.25	22.25	22.25	22.25	11.67	11.67	11.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	20.49-60.98
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	22.50
Data deps.	2.00
Overall L1	22.50-60.98

Vectorization ratios

INT

all	23%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	86%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	70%

INT+FP

all	49%
load	0%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.98 cycles. At this rate:

4% of peak load performance is reached (4.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b600

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR X11, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X17, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X18, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X10, X8, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SDIV X5, X10, X26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD X2, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W6, W22, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X2, X2, X26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD W19, W22, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X30, X6, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X27, X19, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X23, X15, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD W20, W21, W5, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD W10, W21, W2, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W10, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S7, W20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV V7.S[1], W10	1	0	0	0	0	0	0	1	0	0.25	0.25	0.25	0.25	0	0	0	5	1	scal (25.0%)
ADD W10, W8, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X7, X7, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, X8, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD V7.2S, V1.2S, V7.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V7.2D, V7.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MADD W5, W21, W5, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W26, W5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W10, W21, W2, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X2, X26, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W10, W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X5, X10, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X28, X10, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
FMOV D18, X2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
MADD X2, X12, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X2, X9, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X2, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X2, X16, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
FMOV S17, W26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV V18.D[1], X5	1	0	0	0	0	0	0	1	0	0.25	0.25	0.25	0.25	0	0	0	5	1	scal (50.0%)
MADD X5, X12, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X9, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV V17.S[1], W10	1	0	0	0	0	0	0	1	0	0.25	0.25	0.25	0.25	0	0	0	5	1	scal (25.0%)
ADD X10, X5, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X14, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD V20.2S, V17.2S, V2.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ADD V17.2S, V17.2S, V3.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SMIN V20.2S, V0.2S, V20.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V17.2D, V17.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
LD1 {V16.D[1]}, [X10]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X10, X16, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SSHLL V20.2D, V20.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X19, X14, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FCMGT V19.2D, V16.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABS V22.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V21.16B, V19.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BIF V17.16B, V20.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BSL V21.16B, V18.16B, V7.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BIT V18.16B, V7.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BIF V7.16B, V20.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D19, [X13, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X2, D18	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
MOV X10, V18.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMOV X20, D7	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D18, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X6, X5, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X13, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X24, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V19.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MOV X5, V7.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D7, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X5, X13, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V18.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V7.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X5, X15, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR X15, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X14, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W9, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV X22, D17	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
ADD X20, X8, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV X5, V17.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMOV X8, D21	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D20, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X23, X24, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FDIV V18.2D, V22.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1 {V20.D[1]}, [X25]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
FMLA V19.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FSUB V17.2D, V5.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V18.2D, V4.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FNEG V24.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FDIV V7.2D, V19.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LDR D19, [X20, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LD1 {V19.D[1]}, [X23]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MOV X23, V21.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D21, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X24, X24, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V21.D[1]}, [X24]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X24, X1, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
FSUB V22.2D, V20.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABD V19.2D, V20.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD X24, X0, X24,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FSUB V23.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABD V21.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM V25.2D, V19.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V19.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V22.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FCMGT V23.2D, V23.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V19.2D, V21.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
BIF V18.16B, V24.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLE V22.2D, V22.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V19.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMINNM V19.2D, V25.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V18.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
BIC V18.16B, V18.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V18.2D, V18.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V16.2D, V18.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D16, [X24, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X24, X1, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X1, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
FABS V25.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD X24, X0, X24,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, X24, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1 {V16.D[1]}, [X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
MADD X24, X3, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D21, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D22, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X24, X1, X24,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D18, [X24, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D19, [X24, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X8, X3, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR W22, WZR, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X14, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X15, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDUR X18, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X8, X1, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X8, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V21.D[1]}, [X25]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V22.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V20.D[1]}, [X10]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X10, X8, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V18.D[1]}, [X10]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V19.D[1]}, [X8]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X8, X18, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR X30, XZR, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X17, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V21.2D, V22.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV V21.2D, V25.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUB V23.2D, V20.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABD V18.2D, V20.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V24.2D, V19.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABD V19.2D, V19.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V7.2D, V18.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V23.2D, V24.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FCMGT V24.2D, V24.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V7.2D, V19.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FCMLE V17.2D, V23.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V7.2D, V7.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FSUB V21.2D, V4.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FNEG V22.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BIF V21.16B, V22.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM V22.2D, V18.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM V7.2D, V22.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V7.2D, V21.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
BIC V7.16B, V7.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V7.2D, V7.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V7.2D, V7.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D7, [X8, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X8, X18, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR X26, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X17, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1 {V7.D[1]}, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X8, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41b600 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.4]
Source file and lines	advec_cell.cpp:66-110
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66-110
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 72% of vector register length is used (average across all VPU instructions).

Details

49% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58 FP arithmetical operations:

24: addition or subtraction (6 inside FMA instructions)
28: multiply (6 inside FMA instructions)
6: divide

The binary loop is loading 248 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	180
loop length	720
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

22.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	10.67	10.58	10.67	10.50	21.00	10.58	22.25	22.25	22.25	22.25	11.67	11.67	11.67	0.00	0.00
cycles	0.50	0.50	10.67	10.58	10.67	10.50	21.00	10.58	22.25	22.25	22.25	22.25	11.67	11.67	11.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	20.49-60.98
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	22.50
Data deps.	2.00
Overall L1	22.50-60.98

Vectorization ratios

INT

all	23%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	86%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	70%

INT+FP

all	49%
load	0%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.98 cycles. At this rate:

4% of peak load performance is reached (4.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b600

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR X11, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X17, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X18, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X10, X8, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SDIV X5, X10, X26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD X2, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W6, W22, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X2, X2, X26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD W19, W22, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X30, X6, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X27, X19, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X23, X15, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD W20, W21, W5, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD W10, W21, W2, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W10, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S7, W20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV V7.S[1], W10	1	0	0	0	0	0	0	1	0	0.25	0.25	0.25	0.25	0	0	0	5	1	scal (25.0%)
ADD W10, W8, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X7, X7, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, X8, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD V7.2S, V1.2S, V7.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V7.2D, V7.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MADD W5, W21, W5, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W26, W5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W10, W21, W2, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X2, X26, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W10, W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X5, X10, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X28, X10, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
FMOV D18, X2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
MADD X2, X12, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X2, X9, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X2, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X2, X16, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
FMOV S17, W26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV V18.D[1], X5	1	0	0	0	0	0	0	1	0	0.25	0.25	0.25	0.25	0	0	0	5	1	scal (50.0%)
MADD X5, X12, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X9, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV V17.S[1], W10	1	0	0	0	0	0	0	1	0	0.25	0.25	0.25	0.25	0	0	0	5	1	scal (25.0%)
ADD X10, X5, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X14, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD V20.2S, V17.2S, V2.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ADD V17.2S, V17.2S, V3.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SMIN V20.2S, V0.2S, V20.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V17.2D, V17.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
LD1 {V16.D[1]}, [X10]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X10, X16, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SSHLL V20.2D, V20.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X19, X14, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FCMGT V19.2D, V16.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABS V22.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V21.16B, V19.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BIF V17.16B, V20.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BSL V21.16B, V18.16B, V7.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BIT V18.16B, V7.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BIF V7.16B, V20.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D19, [X13, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X2, D18	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
MOV X10, V18.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMOV X20, D7	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D18, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X6, X5, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X13, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X24, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V19.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MOV X5, V7.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D7, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X5, X13, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V18.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V7.D[1]}, [X5]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X5, X15, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR X15, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X14, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W9, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV X22, D17	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
ADD X20, X8, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV X5, V17.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMOV X8, D21	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D20, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X23, X24, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FDIV V18.2D, V22.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1 {V20.D[1]}, [X25]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
FMLA V19.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FSUB V17.2D, V5.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V18.2D, V4.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FNEG V24.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FDIV V7.2D, V19.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LDR D19, [X20, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LD1 {V19.D[1]}, [X23]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MOV X23, V21.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D21, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X24, X24, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V21.D[1]}, [X24]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X24, X1, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
FSUB V22.2D, V20.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABD V19.2D, V20.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD X24, X0, X24,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FSUB V23.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABD V21.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM V25.2D, V19.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V19.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V22.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FCMGT V23.2D, V23.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V19.2D, V21.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
BIF V18.16B, V24.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLE V22.2D, V22.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V19.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMINNM V19.2D, V25.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V18.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
BIC V18.16B, V18.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V18.2D, V18.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V16.2D, V18.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D16, [X24, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X24, X1, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X1, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
FABS V25.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD X24, X0, X24,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, X24, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1 {V16.D[1]}, [X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
MADD X24, X3, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D21, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D22, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X24, X1, X24,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D18, [X24, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D19, [X24, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MADD X8, X3, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR W22, WZR, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X14, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X15, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDUR X18, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X8, X1, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X8, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V21.D[1]}, [X25]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V22.D[1]}, [X6]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V20.D[1]}, [X10]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
ADD X10, X8, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1 {V18.D[1]}, [X10]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
LD1 {V19.D[1]}, [X8]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
MADD X8, X18, X30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR X30, XZR, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X17, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V21.2D, V22.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV V21.2D, V25.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUB V23.2D, V20.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABD V18.2D, V20.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V24.2D, V19.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABD V19.2D, V19.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V7.2D, V18.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V23.2D, V24.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FCMGT V24.2D, V24.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V7.2D, V19.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FCMLE V17.2D, V23.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V7.2D, V7.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FSUB V21.2D, V4.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FNEG V22.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BIF V21.16B, V22.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM V22.2D, V18.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM V7.2D, V22.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V7.2D, V21.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
BIC V7.16B, V7.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V7.2D, V7.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V7.2D, V7.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D7, [X8, X26,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X8, X18, X27, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR X26, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X17, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1 {V7.D[1]}, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X8, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41b600 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code