OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 3.91% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41f200 SUB	SP, SP, #144

0x41f204 STP	X29, X30, [SP, #48]

0x41f208 STP	X28, X27, [SP, #64]

0x41f20c STP	X26, X25, [SP, #80]

0x41f210 STP	X24, X23, [SP, #96]

0x41f214 STP	X22, X21, [SP, #112]

0x41f218 STP	X20, X19, [SP, #128]

0x41f21c ADD	X29, SP, #48

0x41f220 LDR	W8, [X3]

0x41f224 LDR	W22, [X2]

0x41f228 LDR	W25, [X4]

0x41f22c ADD	W8, W8, #3

0x41f230 LDR	W9, [X5]

0x41f234 ADD	W23, W25, #1

0x41f238 ADD	W9, W9, #3

0x41f23c SUBS	W8, W8, W22

0x41f240 CCMP	W9, W23, #4, #12

0x41f244 B.LE	41f2c0

0x41f248 LDR	W19, [X0]

0x41f24c SUB	W24, W9, W23

0x41f250 MOVN	X9, #0

0x41f254 ORR	X20, XZR, X7

0x41f258 ORR	X21, XZR, X6

0x41f25c ADRP	X0,

0x41f260 ADD	X0, X0, #216

0x41f264 ADD	X3, SP, #20

0x41f268 SUB	X4, X29, #8

0x41f26c STR	WZR, [SP, #20]

0x41f270 ORR	W1, WZR, W19

0x41f274 UMADDL	X26, W24, W8, X9

0x41f278 MOVZ	W8, #1

0x41f27c SUB	X5, X29, #16

0x41f280 ADD	X6, SP, #24

0x41f284 MOVZ	W2, #34

0x41f288 MOVZ	W7, #1

0x41f28c STP	X26, XZR, [X29, #1008]

0x41f290 STR	X8, [SP, #24]

0x41f294 STR	X8, [SP]

0x41f298 BL	4034d0

0x41f29c LDP	X8, X2, [X29, #1008]

0x41f2a0 CMP	X8, X26

0x41f2a4 CSEL	X17, X8, X26, #11

0x41f2a8 CMP	X2, X17

0x41f2ac B.LE	41f2e0

  (197) 0x41f2b0 ADRP	X0,

  (197) 0x41f2b4 ADD	X0, X0, #240

  (197) 0x41f2b8 ORR	W1, WZR, W19

  (197) 0x41f2bc BL	403400

  (197) 0x41f2c0 LDP	X20, X19, [SP, #128]

  (197) 0x41f2c4 LDP	X22, X21, [SP, #112]

  (197) 0x41f2c8 LDP	X24, X23, [SP, #96]

  (197) 0x41f2cc LDP	X26, X25, [SP, #80]

  (197) 0x41f2d0 LDP	X28, X27, [SP, #64]

  (197) 0x41f2d4 LDP	X29, X30, [SP, #48]

  (197) 0x41f2d8 ADD	SP, SP, #144

  (197) 0x41f2dc RET

  (197) 0x41f2e0 LDP	X13, X16, [X29, #104]

  (197) 0x41f2e4 LDR	X14, [X29, #96]

  (197) 0x41f2e8 LDR	X8, [X21, #16]

  (197) 0x41f2ec ADD	X17, X17, #1

  (197) 0x41f2f0 ORR	X18, XZR, X2

  (197) 0x41f2f4 SUB	X0, X17, X2

  (197) 0x41f2f8 LDR	X9, [X21]

  (197) 0x41f2fc LDR	X10, [X20, #16]

  (197) 0x41f300 LDR	X11, [X20]

  (197) 0x41f304 LDR	X12, [X13, #16]

  (197) 0x41f308 LDR	X13, [X13]

  (197) 0x41f30c LDR	X14, [X14, #8]

  (197) 0x41f310 LDR	X15, [X16, #16]

  (197) 0x41f314 LDR	X16, [X16]

  (197) 0x41f318 CMP	X0, #2

  (197) 0x41f31c B.CC	41f588

  (197) 0x41f320 ORR	X4, XZR, #3840

  (197) 0x41f324 AND	X1, X0, #8127

  (197) 0x41f328 MOVI	V0.2S, #1

  (197) 0x41f32c MOVI	V1.2D, #-1

  (197) 0x41f330 MOVI	V2.2S, #2

  (197) 0x41f334 FMOV	V3.2D, #2.0000000

  (197) 0x41f338 SUB	W3, WZR, W24

  (197) 0x41f33c MOVK	X4, #16325

  (197) 0x41f340 ADD	X18, X2, X1

  (197) 0x41f344 ADD	X2, X2, #1

  (197) 0x41f348 DUP	V4.2D, X4

  (197) 0x41f34c ORR	X4, XZR, X1

  (197) 0x41f350 B	41f400

0x41f354 HINT	#0

0x41f358 HINT	#0

0x41f35c HINT	#0

    (198) 0x41f360 MADD	X27, X11, X27, XZR

    (198) 0x41f364 MADD	X26, X11, X26, XZR

    (198) 0x41f368 FABS	V19.2D, V5.2D

    (198) 0x41f36c FABS	V16.2D, V16.2D

    (198) 0x41f370 SBFM	X20, X20, #0, #31

    (198) 0x41f374 SUBS	X4, X4, #2

    (198) 0x41f378 ADD	X2, X2, #2

    (198) 0x41f37c ADD	X27, X10, X27,LSL #3

    (198) 0x41f380 ADD	X26, X10, X26,LSL #3

    (198) 0x41f384 ORR	V23.16B, V16.16B, V16.16B

    (198) 0x41f388 MADD	X7, X16, X7, XZR

    (198) 0x41f38c MADD	X6, X16, X6, XZR

    (198) 0x41f390 ADD	X7, X15, X7,LSL #3

    (198) 0x41f394 ADD	X6, X15, X6,LSL #3

    (198) 0x41f398 LDR	D20, [X27, X5,SXTW #3]

    (198) 0x41f39c ADD	X21, X26, X21

    (198) 0x41f3a0 ADD	X7, X7, X20,LSL #3

    (198) 0x41f3a4 LD1	{V20.D[1]}, [X21]

    (198) 0x41f3a8 FDIV	V19.2D, V19.2D, V20.2D

    (198) 0x41f3ac FABS	V20.2D, V17.2D

    (198) 0x41f3b0 FCMGT	V17.2D, V17.2D, #0

    (198) 0x41f3b4 FSUB	V22.2D, V3.2D, V19.2D

    (198) 0x41f3b8 FMLA	V23.2D, V16.2D, V19.2D

    (198) 0x41f3bc FMUL	V22.2D, V20.2D, V22.2D

    (198) 0x41f3c0 FDIV	V18.2D, V23.2D, V18.2D

    (198) 0x41f3c4 FDIV	V22.2D, V22.2D, V21.2D

    (198) 0x41f3c8 FMUL	V21.2D, V21.2D, V4.2D

    (198) 0x41f3cc FADD	V18.2D, V18.2D, V22.2D

    (198) 0x41f3d0 FMUL	V18.2D, V21.2D, V18.2D

    (198) 0x41f3d4 FMINNM	V16.2D, V18.2D, V16.2D

    (198) 0x41f3d8 FMINNM	V16.2D, V16.2D, V20.2D

    (198) 0x41f3dc FNEG	V18.2D, V16.2D

    (198) 0x41f3e0 BIF	V16.16B, V18.16B, V17.16B

    (198) 0x41f3e4 AND	V7.16B, V16.16B, V7.16B

    (198) 0x41f3e8 FMLS	V7.2D, V7.2D, V19.2D

    (198) 0x41f3ec FADD	V6.2D, V7.2D, V6.2D

    (198) 0x41f3f0 FMUL	V5.2D, V6.2D, V5.2D

    (198) 0x41f3f4 STR	D5, [X6, X5,SXTW #3]

    (198) 0x41f3f8 ST1	{V5.D[1]}, [X7]

    (198) 0x41f3fc B.EQ	41f580

    (198) 0x41f400 SUB	X5, X2, #1

    (198) 0x41f404 SDIV	X7, X2, X24

    (198) 0x41f408 ADD	W21, W22, W7

    (198) 0x41f40c SDIV	X5, X5, X24

    (198) 0x41f410 ADD	W20, W22, W5

    (198) 0x41f414 SBFM	X6, X20, #0, #31

    (198) 0x41f418 FMOV	S6, W20

    (198) 0x41f41c ADD	W20, W25, W2

    (198) 0x41f420 MADD	W7, W3, W7, W20

    (198) 0x41f424 MADD	W5, W3, W5, W20

    (198) 0x41f428 ADD	W20, W7, #1

    (198) 0x41f42c SBFM	X7, X21, #0, #31

    (198) 0x41f430 MADD	X26, X9, X7, XZR

    (198) 0x41f434 ADD	X26, X8, X26,LSL #3

    (198) 0x41f438 MOV	V6.S[1], W21

    (198) 0x41f43c MADD	X21, X9, X6, XZR

    (198) 0x41f440 ADD	X27, X8, X21,LSL #3

    (198) 0x41f444 LDR	D5, [X27, X5,SXTW #3]

    (198) 0x41f448 SBFM	X21, X20, #61, #31

    (198) 0x41f44c ADD	X26, X26, X21

    (198) 0x41f450 ADD	V19.2S, V6.2S, V0.2S

    (198) 0x41f454 ADD	V20.2S, V6.2S, V1.2S

    (198) 0x41f458 ADD	V21.2S, V6.2S, V2.2S

    (198) 0x41f45c SSHLL	V17.2D, V19.2S, #32

    (198) 0x41f460 LD1	{V5.D[1]}, [X26]

    (198) 0x41f464 FCMLT	V16.2D, V5.2D, #0

    (198) 0x41f468 ORR	V6.16B, V16.16B, V16.16B

    (198) 0x41f46c FMOV	D7, X6

    (198) 0x41f470 XTN	V18.2S, V16.2D

    (198) 0x41f474 MOV	V7.D[1], X7

    (198) 0x41f478 ORR	V22.16B, V16.16B, V16.16B

    (198) 0x41f47c BSL	V6.16B, V17.16B, V7.16B

    (198) 0x41f480 BSL	V22.16B, V7.16B, V17.16B

    (198) 0x41f484 ORR	V7.8B, V18.8B, V18.8B

    (198) 0x41f488 FMOV	X27, D6

    (198) 0x41f48c MOV	X26, V6.D[1]

    (198) 0x41f490 BSL	V7.8B, V21.8B, V20.8B

    (198) 0x41f494 MADD	X28, X13, X27, XZR

    (198) 0x41f498 MADD	X30, X13, X26, XZR

    (198) 0x41f49c ADD	X28, X12, X28,LSL #3

    (198) 0x41f4a0 ADD	X30, X12, X30,LSL #3

    (198) 0x41f4a4 ADD	X30, X30, X21

    (198) 0x41f4a8 LDR	D6, [X28, X5,SXTW #3]

    (198) 0x41f4ac SMOV	X28, V7.S[0]

    (198) 0x41f4b0 MADD	X28, X13, X28, XZR

    (198) 0x41f4b4 ADD	X28, X12, X28,LSL #3

    (198) 0x41f4b8 LD1	{V6.D[1]}, [X30]

    (198) 0x41f4bc SMOV	X30, V7.S[1]

    (198) 0x41f4c0 LDR	D7, [X28, X5,SXTW #3]

    (198) 0x41f4c4 MOV	X28, V22.D[1]

    (198) 0x41f4c8 MADD	X30, X13, X30, XZR

    (198) 0x41f4cc MADD	X28, X13, X28, XZR

    (198) 0x41f4d0 ADD	X30, X12, X30,LSL #3

    (198) 0x41f4d4 ADD	X28, X12, X28,LSL #3

    (198) 0x41f4d8 ADD	X30, X30, X21

    (198) 0x41f4dc ADD	X28, X28, X21

    (198) 0x41f4e0 LD1	{V7.D[1]}, [X30]

    (198) 0x41f4e4 FMOV	X30, D22

    (198) 0x41f4e8 MADD	X30, X13, X30, XZR

    (198) 0x41f4ec ADD	X30, X12, X30,LSL #3

    (198) 0x41f4f0 FSUB	V16.2D, V6.2D, V7.2D

    (198) 0x41f4f4 LDR	D7, [X30, X5,SXTW #3]

    (198) 0x41f4f8 LD1	{V7.D[1]}, [X28]

    (198) 0x41f4fc FSUB	V17.2D, V7.2D, V6.2D

    (198) 0x41f500 FMUL	V7.2D, V17.2D, V16.2D

    (198) 0x41f504 FCMGT	V7.2D, V7.2D, #0

    (198) 0x41f508 XTN	V22.2S, V7.2D

    (198) 0x41f50c FMOV	W28, S22

    (198) 0x41f510 TBNZ	W28, #0, 41f540

    (198) 0x41f514 MOV	W28, V22.S[1]

    (198) 0x41f518 TBNZ	W28, #0, 41f54c

    (198) 0x41f51c BIF	V19.8B, V20.8B, V18.8B

    (198) 0x41f520 FMOV	W28, S22

    (198) 0x41f524 TBNZ	W28, #0, 41f560

    (198) 0x41f528 MOV	W28, V22.S[1]

    (198) 0x41f52c TBZ	W28, #0, 41f360

    (198) 0x41f530 B	41f570

0x41f534 HINT	#0

0x41f538 HINT	#0

0x41f53c HINT	#0

    (198) 0x41f540 LDR	D21, [X14, X6,LSL #3]

    (198) 0x41f544 MOV	W28, V22.S[1]

    (198) 0x41f548 TBZ	W28, #0, 41f51c

    (198) 0x41f54c ADD	X28, X14, X7,LSL #3

    (198) 0x41f550 LD1	{V21.D[1]}, [X28]

    (198) 0x41f554 BIF	V19.8B, V20.8B, V18.8B

    (198) 0x41f558 FMOV	W28, S22

    (198) 0x41f55c TBZ	W28, #0, 41f528

    (198) 0x41f560 FMOV	W28, S19

    (198) 0x41f564 LDR	D18, [X14, X28,SXTW #3]

    (198) 0x41f568 MOV	W28, V22.S[1]

    (198) 0x41f56c TBZ	W28, #0, 41f360

    (198) 0x41f570 MOV	W28, V19.S[1]

    (198) 0x41f574 ADD	X28, X14, W28,SXTW #3

    (198) 0x41f578 LD1	{V18.D[1]}, [X28]

    (198) 0x41f57c B	41f360

  (197) 0x41f580 CMP	X0, X1

  (197) 0x41f584 B.EQ	41f2b0

(196) 0x41f588 FMOV	D0, #2.0000000

(196) 0x41f58c ORR	X1, XZR, #3840

(196) 0x41f590 SUB	W0, WZR, W24

(196) 0x41f594 MOVK	X1, #16325

(196) 0x41f598 B	41f5c4

0x41f59c HINT	#0

(196) 0x41f5a0 FMSUB	D2, D2, D6, D6

(196) 0x41f5a4 MADD	X3, X16, X3, XZR

(196) 0x41f5a8 ADD	X18, X18, #1

(196) 0x41f5ac ADD	X3, X15, X3,LSL #3

(196) 0x41f5b0 FADD	D2, D2, D3

(196) 0x41f5b4 FMUL	D1, D2, D1

(196) 0x41f5b8 STR	D1, [X3, X2,SXTW #3]

(196) 0x41f5bc CMP	X17, X18

(196) 0x41f5c0 B.EQ	41f2b0

(196) 0x41f5c4 SDIV	X2, X18, X24

(196) 0x41f5c8 ADD	W3, W23, W18

(196) 0x41f5cc ADD	W4, W22, W2

(196) 0x41f5d0 MADD	W2, W0, W2, W3

(196) 0x41f5d4 SBFM	X3, X4, #0, #31

(196) 0x41f5d8 ADD	W4, W4, #1

(196) 0x41f5dc MADD	X5, X9, X3, XZR

(196) 0x41f5e0 ADD	X5, X8, X5,LSL #3

(196) 0x41f5e4 LDR	D1, [X5, X2,SXTW #3]

(196) 0x41f5e8 SBFM	X5, X4, #0, #31

(196) 0x41f5ec FCMP	D1, #0

(196) 0x41f5f0 B.GE	41f600

(196) 0x41f5f4 ADD	W7, W3, #2

(196) 0x41f5f8 ORR	X6, XZR, X3

(196) 0x41f5fc B	41f610

(196) 0x41f600 SUB	W4, W3, #1

(196) 0x41f604 ORR	X6, XZR, X5

(196) 0x41f608 ORR	X5, XZR, X3

(196) 0x41f60c ORR	W7, WZR, W4

(196) 0x41f610 MADD	X20, X11, X5, XZR

(196) 0x41f614 MADD	X5, X13, X5, XZR

(196) 0x41f618 FABS	D2, D1

(196) 0x41f61c MOVI	D6, #0

(196) 0x41f620 ADD	X20, X10, X20,LSL #3

(196) 0x41f624 ADD	X5, X12, X5,LSL #3

(196) 0x41f628 LDR	D3, [X20, X2,SXTW #3]

(196) 0x41f62c FDIV	D2, D2, D3

(196) 0x41f630 LDR	D3, [X5, X2,SXTW #3]

(196) 0x41f634 SBFM	X5, X7, #0, #31

(196) 0x41f638 MADD	X5, X13, X5, XZR

(196) 0x41f63c ADD	X5, X12, X5,LSL #3

(196) 0x41f640 LDR	D4, [X5, X2,SXTW #3]

(196) 0x41f644 MADD	X5, X13, X6, XZR

(196) 0x41f648 ADD	X5, X12, X5,LSL #3

(196) 0x41f64c FSUB	D5, D3, S4

(196) 0x41f650 LDR	D4, [X5, X2,SXTW #3]

(196) 0x41f654 FSUB	D4, D4, S3

(196) 0x41f658 FMUL	D7, D4, D5

(196) 0x41f65c FCMP	D7, #0

(196) 0x41f660 B.LE	41f5a0

(196) 0x41f664 LDR	D6, [X14, X3,LSL #3]

(196) 0x41f668 FABS	D5, D5

(196) 0x41f66c LDR	D18, [X14, X4,SXTW #3]

(196) 0x41f670 FABS	D7, D4

(196) 0x41f674 FSUB	D16, D0, S2

(196) 0x41f678 FCMP	D4, #0

(196) 0x41f67c FMADD	D17, D2, D5, D5

(196) 0x41f680 FMUL	D16, D7, D16

(196) 0x41f684 FDIV	D16, D16, D6

(196) 0x41f688 FDIV	D17, D17, D18

(196) 0x41f68c FADD	D16, D17, D16

(196) 0x41f690 FMOV	D17, X1

(196) 0x41f694 FMUL	D6, D6, D17

(196) 0x41f698 FMUL	D6, D6, D16

(196) 0x41f69c FMINNM	D5, D6, D5

(196) 0x41f6a0 FMINNM	D5, D5, D7

(196) 0x41f6a4 FNEG	D6, D5

(196) 0x41f6a8 FCSEL	D6, D5, D6, #12

(196) 0x41f6ac B	41f5a0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.50 to 4.12 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	51
loop length	204
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	5.00	5.00
cycles	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

6% of peak load performance is reached (6.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W25, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41f2c0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46d25c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X26, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X2, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X17, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41f2e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	51
loop length	204
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	5.00	5.00
cycles	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

6% of peak load performance is reached (6.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W25, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41f2c0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46d25c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X26, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X2, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X17, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41f2e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.91	3.15
▼Loop 196 - advec_mom.cpp:180-211 - exec–	0.00	0.00
▼Loop 197 - advec_mom.cpp:180-211 - exec–	0.00	0.00
○Loop 198 - advec_mom.cpp:181-211 - exec	3.91	3.13

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code