OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 3.75% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41e490 SUB	SP, SP, #144

0x41e494 STP	X29, X30, [SP, #48]

0x41e498 STP	X28, X27, [SP, #64]

0x41e49c STP	X26, X25, [SP, #80]

0x41e4a0 STP	X24, X23, [SP, #96]

0x41e4a4 STP	X22, X21, [SP, #112]

0x41e4a8 STP	X20, X19, [SP, #128]

0x41e4ac ADD	X29, SP, #48

0x41e4b0 LDR	W8, [X2]

0x41e4b4 LDR	W9, [X5]

0x41e4b8 LDR	W23, [X4]

0x41e4bc ADD	W22, W8, #1

0x41e4c0 LDR	W8, [X3]

0x41e4c4 ADD	W9, W9, #3

0x41e4c8 ADD	W8, W8, #3

0x41e4cc SUBS	W8, W8, W22

0x41e4d0 CCMP	W9, W23, #4, #12

0x41e4d4 B.LE	41e550

0x41e4d8 LDR	W19, [X0]

0x41e4dc SUB	W24, W9, W23

0x41e4e0 MOVN	X9, #0

0x41e4e4 ORR	X20, XZR, X7

0x41e4e8 ORR	X21, XZR, X6

0x41e4ec ADRP	X0,

0x41e4f0 ADD	X0, X0, #4024

0x41e4f4 ADD	X3, SP, #20

0x41e4f8 SUB	X4, X29, #8

0x41e4fc STR	WZR, [SP, #20]

0x41e500 ORR	W1, WZR, W19

0x41e504 UMADDL	X25, W24, W8, X9

0x41e508 MOVZ	W8, #1

0x41e50c SUB	X5, X29, #16

0x41e510 ADD	X6, SP, #24

0x41e514 MOVZ	W2, #34

0x41e518 MOVZ	W7, #1

0x41e51c STP	X25, XZR, [X29, #1008]

0x41e520 STR	X8, [SP, #24]

0x41e524 STR	X8, [SP]

0x41e528 BL	4034d0

0x41e52c LDP	X8, X0, [X29, #1008]

0x41e530 CMP	X8, X25

0x41e534 CSEL	X17, X8, X25, #11

0x41e538 CMP	X0, X17

0x41e53c B.LE	41e570

    (186) 0x41e540 ADRP	X0,

    (186) 0x41e544 ADD	X0, X0, #4048

    (186) 0x41e548 ORR	W1, WZR, W19

    (186) 0x41e54c BL	403400

    (186) 0x41e550 LDP	X20, X19, [SP, #128]

    (186) 0x41e554 LDP	X22, X21, [SP, #112]

    (186) 0x41e558 LDP	X24, X23, [SP, #96]

    (186) 0x41e55c LDP	X26, X25, [SP, #80]

    (186) 0x41e560 LDP	X28, X27, [SP, #64]

    (186) 0x41e564 LDP	X29, X30, [SP, #48]

    (186) 0x41e568 ADD	SP, SP, #144

    (186) 0x41e56c RET

    (186) 0x41e570 LDP	X13, X16, [X29, #104]

    (186) 0x41e574 LDR	X14, [X29, #96]

    (186) 0x41e578 LDR	X8, [X21, #16]

    (186) 0x41e57c ADD	X17, X17, #1

    (186) 0x41e580 SUB	X1, X17, X0

    (186) 0x41e584 LDR	X9, [X21]

    (186) 0x41e588 LDR	X10, [X20, #16]

    (186) 0x41e58c LDR	X11, [X20]

    (186) 0x41e590 LDR	X12, [X13, #16]

    (186) 0x41e594 LDR	X13, [X13]

    (186) 0x41e598 LDR	X14, [X14, #8]

    (186) 0x41e59c LDR	X15, [X16, #16]

    (186) 0x41e5a0 LDR	X16, [X16]

    (186) 0x41e5a4 CMP	X1, #2

    (186) 0x41e5a8 B.CS	41e5b4

  (188) 0x41e5ac ORR	X18, XZR, X0

  (188) 0x41e5b0 B	41e7e8

    (186) 0x41e5b4 ORR	X4, XZR, #3840

    (186) 0x41e5b8 AND	X2, X1, #8127

    (186) 0x41e5bc MOVI	V0.2S, #1

    (186) 0x41e5c0 MOVI	V1.2D, #-1

    (186) 0x41e5c4 MOVI	V2.2S, #2

    (186) 0x41e5c8 FMOV	V3.2D, #2.0000000

    (186) 0x41e5cc SUB	W3, WZR, W24

    (186) 0x41e5d0 MOVK	X4, #16325

    (186) 0x41e5d4 ADD	X18, X0, X2

    (186) 0x41e5d8 DUP	V4.2D, X4

    (186) 0x41e5dc ORR	X4, XZR, X2

    (186) 0x41e5e0 B	41e680

      (189) 0x41e5e4 MADD	X26, X11, X6, XZR

      (189) 0x41e5e8 MADD	X27, X11, X20, XZR

      (189) 0x41e5ec FABS	V20.2D, V5.2D

      (189) 0x41e5f0 FABS	V16.2D, V16.2D

      (189) 0x41e5f4 SUBS	X4, X4, #2

      (189) 0x41e5f8 ADD	X0, X0, #2

      (189) 0x41e5fc ADD	X26, X10, X26,LSL #3

      (189) 0x41e600 ADD	X27, X10, X27,LSL #3

      (189) 0x41e604 ORR	V23.16B, V16.16B, V16.16B

      (189) 0x41e608 MADD	X20, X16, X20, XZR

      (189) 0x41e60c MADD	X6, X16, X6, XZR

      (189) 0x41e610 ADD	X20, X15, X20,LSL #3

      (189) 0x41e614 ADD	X6, X15, X6,LSL #3

      (189) 0x41e618 LDR	D21, [X26, X21,LSL #3]

      (189) 0x41e61c ADD	X25, X27, X25,LSL #3

      (189) 0x41e620 ADD	X7, X20, X7,LSL #3

      (189) 0x41e624 LD1	{V21.D[1]}, [X25]

      (189) 0x41e628 FDIV	V20.2D, V20.2D, V21.2D

      (189) 0x41e62c FABS	V21.2D, V17.2D

      (189) 0x41e630 FCMGT	V17.2D, V17.2D, #0

      (189) 0x41e634 FSUB	V22.2D, V3.2D, V20.2D

      (189) 0x41e638 FMLA	V23.2D, V16.2D, V20.2D

      (189) 0x41e63c FMUL	V22.2D, V21.2D, V22.2D

      (189) 0x41e640 FDIV	V19.2D, V23.2D, V19.2D

      (189) 0x41e644 FDIV	V22.2D, V22.2D, V18.2D

      (189) 0x41e648 FMUL	V18.2D, V18.2D, V4.2D

      (189) 0x41e64c FADD	V19.2D, V19.2D, V22.2D

      (189) 0x41e650 FMUL	V18.2D, V18.2D, V19.2D

      (189) 0x41e654 FMINNM	V16.2D, V18.2D, V16.2D

      (189) 0x41e658 FMINNM	V16.2D, V16.2D, V21.2D

      (189) 0x41e65c FNEG	V18.2D, V16.2D

      (189) 0x41e660 BIF	V16.16B, V18.16B, V17.16B

      (189) 0x41e664 AND	V7.16B, V16.16B, V7.16B

      (189) 0x41e668 FMLS	V7.2D, V7.2D, V20.2D

      (189) 0x41e66c FADD	V6.2D, V7.2D, V6.2D

      (189) 0x41e670 FMUL	V5.2D, V6.2D, V5.2D

      (189) 0x41e674 STR	D5, [X6, X5,LSL #3]

      (189) 0x41e678 ST1	{V5.D[1]}, [X7]

      (189) 0x41e67c B.EQ	41e7e0

      (189) 0x41e680 SDIV	X6, X0, X24

      (189) 0x41e684 ADD	X5, X0, #1

      (189) 0x41e688 ADD	W21, W23, W0

      (189) 0x41e68c ADD	W7, W22, W6

      (189) 0x41e690 SDIV	X5, X5, X24

      (189) 0x41e694 ADD	W20, W22, W5

      (189) 0x41e698 SBFM	X20, X20, #0, #31

      (189) 0x41e69c MADD	X27, X13, X20, XZR

      (189) 0x41e6a0 ADD	X27, X12, X27,LSL #3

      (189) 0x41e6a4 MADD	W25, W3, W6, W21

      (189) 0x41e6a8 SBFM	X6, X7, #0, #31

      (189) 0x41e6ac MADD	X7, X9, X6, XZR

      (189) 0x41e6b0 ADD	X7, X8, X7,LSL #3

      (189) 0x41e6b4 LDR	D5, [X7, X25,SXTW #3]

      (189) 0x41e6b8 MADD	X26, X13, X6, XZR

      (189) 0x41e6bc ADD	X26, X12, X26,LSL #3

      (189) 0x41e6c0 MADD	W5, W3, W5, W21

      (189) 0x41e6c4 ADD	W21, W5, #1

      (189) 0x41e6c8 SBFM	X5, X25, #0, #31

      (189) 0x41e6cc SBFM	X7, X21, #0, #31

      (189) 0x41e6d0 FMOV	S6, W25

      (189) 0x41e6d4 MADD	X25, X9, X20, XZR

      (189) 0x41e6d8 ADD	X25, X8, X25,LSL #3

      (189) 0x41e6dc MOV	V6.S[1], W21

      (189) 0x41e6e0 ADD	X21, X25, W21,SXTW #3

      (189) 0x41e6e4 ADD	V20.2S, V6.2S, V0.2S

      (189) 0x41e6e8 ADD	V21.2S, V6.2S, V1.2S

      (189) 0x41e6ec ADD	V6.2S, V6.2S, V2.2S

      (189) 0x41e6f0 LD1	{V5.D[1]}, [X21]

      (189) 0x41e6f4 SSHLL	V17.2D, V20.2S, #32

      (189) 0x41e6f8 FCMLT	V16.2D, V5.2D, #0

      (189) 0x41e6fc ORR	V18.16B, V16.16B, V16.16B

      (189) 0x41e700 XTN	V19.2S, V16.2D

      (189) 0x41e704 FMOV	D7, X5

      (189) 0x41e708 MOV	V7.D[1], X7

      (189) 0x41e70c BSL	V18.16B, V7.16B, V17.16B

      (189) 0x41e710 BIT	V7.16B, V17.16B, V16.16B

      (189) 0x41e714 ORR	V16.8B, V19.8B, V19.8B

      (189) 0x41e718 FMOV	X21, D7

      (189) 0x41e71c BSL	V16.8B, V6.8B, V21.8B

      (189) 0x41e720 MOV	X25, V7.D[1]

      (189) 0x41e724 ADD	X28, X27, X25,LSL #3

      (189) 0x41e728 LDR	D6, [X26, X21,LSL #3]

      (189) 0x41e72c FMOV	W30, S16

      (189) 0x41e730 LDR	D7, [X26, X30,SXTW #3]

      (189) 0x41e734 FMOV	X30, D18

      (189) 0x41e738 LD1	{V6.D[1]}, [X28]

      (189) 0x41e73c MOV	W28, V16.S[1]

      (189) 0x41e740 ADD	X28, X27, W28,SXTW #3

      (189) 0x41e744 LD1	{V7.D[1]}, [X28]

      (189) 0x41e748 FSUB	V16.2D, V6.2D, V7.2D

      (189) 0x41e74c LDR	D7, [X26, X30,LSL #3]

      (189) 0x41e750 MOV	X28, V18.D[1]

      (189) 0x41e754 ADD	X27, X27, X28,LSL #3

      (189) 0x41e758 LD1	{V7.D[1]}, [X27]

      (189) 0x41e75c FSUB	V17.2D, V7.2D, V6.2D

      (189) 0x41e760 FMUL	V7.2D, V17.2D, V16.2D

      (189) 0x41e764 FCMGT	V7.2D, V7.2D, #0

      (189) 0x41e768 XTN	V22.2S, V7.2D

      (189) 0x41e76c FMOV	W26, S22

      (189) 0x41e770 TBNZ	W26, #0, 41e7a0

      (189) 0x41e774 MOV	W26, V22.S[1]

      (189) 0x41e778 TBNZ	W26, #0, 41e7ac

      (189) 0x41e77c BIF	V20.8B, V21.8B, V19.8B

      (189) 0x41e780 FMOV	W26, S22

      (189) 0x41e784 TBNZ	W26, #0, 41e7c0

      (189) 0x41e788 MOV	W26, V22.S[1]

      (189) 0x41e78c TBZ	W26, #0, 41e5e4

      (189) 0x41e790 B	41e7d0

0x41e794 HINT	#0

0x41e798 HINT	#0

0x41e79c HINT	#0

      (189) 0x41e7a0 LDR	D18, [X14, X5,LSL #3]

      (189) 0x41e7a4 MOV	W26, V22.S[1]

      (189) 0x41e7a8 TBZ	W26, #0, 41e77c

      (189) 0x41e7ac ADD	X26, X14, X7,LSL #3

      (189) 0x41e7b0 LD1	{V18.D[1]}, [X26]

      (189) 0x41e7b4 BIF	V20.8B, V21.8B, V19.8B

      (189) 0x41e7b8 FMOV	W26, S22

      (189) 0x41e7bc TBZ	W26, #0, 41e788

      (189) 0x41e7c0 FMOV	W26, S20

      (189) 0x41e7c4 LDR	D19, [X14, X26,SXTW #3]

      (189) 0x41e7c8 MOV	W26, V22.S[1]

      (189) 0x41e7cc TBZ	W26, #0, 41e5e4

      (189) 0x41e7d0 MOV	W26, V20.S[1]

      (189) 0x41e7d4 ADD	X26, X14, W26,SXTW #3

      (189) 0x41e7d8 LD1	{V19.D[1]}, [X26]

      (189) 0x41e7dc B	41e5e4

    (186) 0x41e7e0 CMP	X1, X2

    (186) 0x41e7e4 B.EQ	41e540

  (188) 0x41e7e8 FMOV	D0, #2.0000000

  (188) 0x41e7ec ORR	X1, XZR, #3840

  (188) 0x41e7f0 SUB	W0, WZR, W24

  (188) 0x41e7f4 MOVK	X1, #16325

  (188) 0x41e7f8 B	41e824

0x41e7fc HINT	#0

  (188) 0x41e800 FMSUB	D2, D2, D6, D6

  (188) 0x41e804 MADD	X3, X16, X3, XZR

  (188) 0x41e808 ADD	X18, X18, #1

  (188) 0x41e80c ADD	X3, X15, X3,LSL #3

  (188) 0x41e810 FADD	D2, D2, D3

  (188) 0x41e814 FMUL	D1, D2, D1

  (188) 0x41e818 STR	D1, [X3, X2,LSL #3]

  (188) 0x41e81c CMP	X17, X18

  (188) 0x41e820 B.EQ	41e540

  (188) 0x41e824 SDIV	X6, X18, X24

  (188) 0x41e828 ADD	X4, X23, X18

  (188) 0x41e82c ADD	W3, W22, W6

  (188) 0x41e830 MADD	W5, W0, W6, W4

  (188) 0x41e834 SBFM	X3, X3, #0, #31

  (188) 0x41e838 MADD	X7, X9, X3, XZR

  (188) 0x41e83c SBFM	X2, X5, #0, #31

  (188) 0x41e840 ADD	X7, X8, X7,LSL #3

  (188) 0x41e844 LDR	D1, [X7, X5,SXTW #3]

  (188) 0x41e848 MADD	W5, W0, W6, WZR

  (188) 0x41e84c ADD	X4, X4, X5

  (188) 0x41e850 ADD	X4, X4, #1

  (188) 0x41e854 SBFM	X5, X4, #0, #31

  (188) 0x41e858 FCMP	D1, #0

  (188) 0x41e85c B.GE	41e880

  (188) 0x41e860 ADD	W7, W23, W18

  (188) 0x41e864 MADD	W6, W0, W6, W7

  (188) 0x41e868 ADD	W7, W6, #2

  (188) 0x41e86c ORR	X6, XZR, X2

  (188) 0x41e870 B	41e898

0x41e874 HINT	#0

0x41e878 HINT	#0

0x41e87c HINT	#0

(187) 0x41e880 MSUB	W4, W6, W24, W18

(187) 0x41e884 ORR	X6, XZR, X5

(187) 0x41e888 ORR	X5, XZR, X2

(187) 0x41e88c ADD	W4, W23, W4

(187) 0x41e890 SUB	W4, W4, #1

(187) 0x41e894 ORR	W7, WZR, W4

  (188) 0x41e898 MADD	X20, X11, X3, XZR

  (188) 0x41e89c FABS	D2, D1

  (188) 0x41e8a0 MOVI	D6, #0

  (188) 0x41e8a4 ADD	X20, X10, X20,LSL #3

  (188) 0x41e8a8 LDR	D3, [X20, X5,LSL #3]

  (188) 0x41e8ac MADD	X20, X13, X3, XZR

  (188) 0x41e8b0 ADD	X20, X12, X20,LSL #3

  (188) 0x41e8b4 LDR	D4, [X20, X7,SXTW #3]

  (188) 0x41e8b8 FDIV	D2, D2, D3

  (188) 0x41e8bc LDR	D3, [X20, X5,LSL #3]

  (188) 0x41e8c0 FSUB	D5, D3, S4

  (188) 0x41e8c4 LDR	D4, [X20, X6,LSL #3]

  (188) 0x41e8c8 FSUB	D4, D4, S3

  (188) 0x41e8cc FMUL	D7, D4, D5

  (188) 0x41e8d0 FCMP	D7, #0

  (188) 0x41e8d4 B.LE	41e800

  (188) 0x41e8d8 LDR	D6, [X14, X2,LSL #3]

  (188) 0x41e8dc FABS	D5, D5

  (188) 0x41e8e0 LDR	D18, [X14, X4,SXTW #3]

  (188) 0x41e8e4 FABS	D7, D4

  (188) 0x41e8e8 FSUB	D16, D0, S2

  (188) 0x41e8ec FCMP	D4, #0

  (188) 0x41e8f0 FMADD	D17, D2, D5, D5

  (188) 0x41e8f4 FMUL	D16, D7, D16

  (188) 0x41e8f8 FDIV	D16, D16, D6

  (188) 0x41e8fc FDIV	D17, D17, D18

  (188) 0x41e900 FADD	D16, D17, D16

  (188) 0x41e904 FMOV	D17, X1

  (188) 0x41e908 FMUL	D6, D6, D17

  (188) 0x41e90c FMUL	D6, D6, D16

  (188) 0x41e910 FMINNM	D5, D6, D5

  (188) 0x41e914 FMINNM	D5, D5, D7

  (188) 0x41e918 FNEG	D6, D5

  (188) 0x41e91c FCSEL	D6, D5, D6, #12

  (188) 0x41e920 B	41e800

0x41e924 HINT	#0

0x41e928 HINT	#0

0x41e92c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.50 to 4.15 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	5.00	5.00
cycles	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

6% of peak load performance is reached (6.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e490

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41e550 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c4ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #4024	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X25, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X0, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X17, X8, X25, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41e570 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	5.00	5.00
cycles	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

6% of peak load performance is reached (6.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e490

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41e550 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c4ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #4024	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X25, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X0, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X17, X8, X25, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41e570 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.75	3.02
▼Loop 187 - context.h:46-69 - exec–	0.00	0.00
▼Loop 188 - advec_mom.cpp:108-139 - exec–	0.00	0.00
▼Loop 186 - advec_mom.cpp:108-139 - exec–	0.00	0.00
○Loop 189 - advec_mom.cpp:109-139 - exec	3.75	3.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code