OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:157-202 [...]	Coverage (incl. loops): 3.71% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 157 - 202

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

164:             upwind = j - 2;

165:             donor = j - 1;

166:             downwind = j;

167:             dif = donor;

168:           } else {

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41c480 SUB	SP, SP, #240

0x41c484 STP	X29, X30, [SP, #144]

0x41c488 STP	X28, X27, [SP, #160]

0x41c48c STP	X26, X25, [SP, #176]

0x41c490 STP	X24, X23, [SP, #192]

0x41c494 STP	X22, X21, [SP, #208]

0x41c498 STP	X20, X19, [SP, #224]

0x41c49c ADD	X29, SP, #144

0x41c4a0 LDR	W24, [X2]

0x41c4a4 LDR	W19, [X3]

0x41c4a8 LDR	W10, [X4]

0x41c4ac ADD	W23, W24, #1

0x41c4b0 LDR	W9, [X5]

0x41c4b4 ADD	W8, W19, #4

0x41c4b8 ADD	W25, W10, #1

0x41c4bc ADD	W9, W9, #2

0x41c4c0 SUBS	W8, W8, W23

0x41c4c4 CCMP	W9, W25, #4, #12

0x41c4c8 B.LE	41c548

0x41c4cc LDR	W27, [X0]

0x41c4d0 SUB	W26, W9, W25

0x41c4d4 MOVN	X9, #0

0x41c4d8 ORR	X20, XZR, X7

0x41c4dc ORR	X21, XZR, X6

0x41c4e0 ADRP	X0,

0x41c4e4 ADD	X0, X0, #3448

0x41c4e8 SUB	X3, X29, #36

0x41c4ec SUB	X4, X29, #16

0x41c4f0 STUR	X10, [X29, #448]

0x41c4f4 STUR	WZR, [X29, #476]

0x41c4f8 ORR	W1, WZR, W27

0x41c4fc UMADDL	X22, W26, W8, X9

0x41c500 MOVZ	W8, #1

0x41c504 SUB	X5, X29, #24

0x41c508 SUB	X6, X29, #32

0x41c50c MOVZ	W2, #34

0x41c510 MOVZ	W7, #1

0x41c514 STP	X22, XZR, [X29, #1000]

0x41c518 STUR	X8, [X29, #480]

0x41c51c STR	X8, [SP]

0x41c520 BL	4034d0

0x41c524 LDP	X10, X8, [X29, #1000]

0x41c528 CMP	X10, X22

0x41c52c CSEL	X9, X10, X22, #11

0x41c530 CMP	X8, X9

0x41c534 B.LE	41c568

(169) 0x41c538 ADRP	X0,

(169) 0x41c53c ADD	X0, X0, #3472

(169) 0x41c540 ORR	W1, WZR, W27

(169) 0x41c544 BL	403400

(169) 0x41c548 LDP	X20, X19, [SP, #224]

(169) 0x41c54c LDP	X22, X21, [SP, #208]

(169) 0x41c550 LDP	X24, X23, [SP, #192]

(169) 0x41c554 LDP	X26, X25, [SP, #176]

(169) 0x41c558 LDP	X28, X27, [SP, #160]

(169) 0x41c55c LDP	X29, X30, [SP, #144]

(169) 0x41c560 ADD	SP, SP, #240

(169) 0x41c564 RET

(169) 0x41c568 LDP	X0, X10, [X29, #128]

(169) 0x41c56c LDR	X17, [X29, #120]

(169) 0x41c570 LDP	X13, X15, [X29, #96]

(169) 0x41c574 ADD	X9, X9, #1

(169) 0x41c578 ADD	W16, W19, #2

(169) 0x41c57c ORR	X4, XZR, X8

(169) 0x41c580 LDR	X11, [X21, #16]

(169) 0x41c584 LDR	X12, [X21]

(169) 0x41c588 LDR	X22, [X20, #16]

(169) 0x41c58c LDR	X28, [X20]

(169) 0x41c590 STUR	X9, [X29, #456]

(169) 0x41c594 SUB	X9, X9, X8

(169) 0x41c598 LDR	X13, [X13, #8]

(169) 0x41c59c LDR	X14, [X15, #16]

(169) 0x41c5a0 LDR	X15, [X15]

(169) 0x41c5a4 LDR	X30, [X17, #16]

(169) 0x41c5a8 LDR	X17, [X17]

(169) 0x41c5ac LDR	X18, [X0, #16]

(169) 0x41c5b0 LDR	X0, [X0]

(169) 0x41c5b4 LDR	X2, [X10, #16]

(169) 0x41c5b8 LDR	X3, [X10]

(169) 0x41c5bc CMP	X9, #2

(169) 0x41c5c0 B.CC	41c934

(169) 0x41c5c4 AND	X21, X9, #8127

(169) 0x41c5c8 ADD	X7, X8, #1

(169) 0x41c5cc DUP	V0.2S, W16

(169) 0x41c5d0 MOVI	V2.2S, #1

(169) 0x41c5d4 MVNI	V3.2S, #1

(169) 0x41c5d8 FMOV	V4.2D, #1.0000000

(169) 0x41c5dc FMOV	V5.2D, #2.0000000

(169) 0x41c5e0 STP	W16, W27, [SP, #32]

(169) 0x41c5e4 STR	X25, [SP, #40]

(169) 0x41c5e8 STP	X28, X22, [SP, #64]

(169) 0x41c5ec DUP	V1.2S, W24

(169) 0x41c5f0 STR	X30, [SP, #56]

(169) 0x41c5f4 ADD	X4, X8, X21

(169) 0x41c5f8 SUB	W8, WZR, W26

(169) 0x41c5fc STP	X21, X9, [SP, #16]

(169) 0x41c600 STP	W24, W8, [SP, #48]

(169) 0x41c604 ORR	X8, XZR, #3840

(169) 0x41c608 MOVK	X8, #16325

(169) 0x41c60c DUP	V6.2D, X8

(169) 0x41c610 HINT	#0

(169) 0x41c614 HINT	#0

(169) 0x41c618 HINT	#0

(169) 0x41c61c HINT	#0

  (171) 0x41c620 SUB	X8, X7, #1

  (171) 0x41c624 SDIV	X10, X7, X26

  (171) 0x41c628 LDUR	X16, [X29, #448]

  (171) 0x41c62c STUR	X21, [X29, #464]

  (171) 0x41c630 ORR	X21, XZR, X13

  (171) 0x41c634 ADD	W1, W16, W7

  (171) 0x41c638 LDR	W16, [SP, #52]

  (171) 0x41c63c ADD	X7, X7, #2

  (171) 0x41c640 ADD	W5, W23, W10

  (171) 0x41c644 SDIV	X9, X8, X26

  (171) 0x41c648 ADD	W8, W23, W9

  (171) 0x41c64c SBFM	X30, X5, #0, #31

  (171) 0x41c650 SBFM	X28, X8, #0, #31

  (171) 0x41c654 LDR	D7, [X13, X8,SXTW #3]

  (171) 0x41c658 MADD	X6, X12, X28, XZR

  (171) 0x41c65c MADD	W27, W16, W9, W1

  (171) 0x41c660 FMOV	S16, W9

  (171) 0x41c664 ADD	X9, X11, X6,LSL #3

  (171) 0x41c668 LDR	D18, [X9, X27,SXTW #3]

  (171) 0x41c66c FMOV	S17, W8

  (171) 0x41c670 MADD	W8, W16, W10, W1

  (171) 0x41c674 LDP	X9, X16, [SP, #64]

  (171) 0x41c678 MADD	X1, X17, X28, XZR

  (171) 0x41c67c MOV	V16.S[1], W10

  (171) 0x41c680 ADD	W10, W8, #1

  (171) 0x41c684 MADD	X8, X12, X30, XZR

  (171) 0x41c688 ADD	X8, X11, X8,LSL #3

  (171) 0x41c68c SBFM	X6, X10, #61, #31

  (171) 0x41c690 ADD	X8, X8, X6

  (171) 0x41c694 ADD	V16.2S, V1.2S, V16.2S

  (171) 0x41c698 SSHLL	V23.2D, V16.2S, #32

  (171) 0x41c69c LD1	{V18.D[1]}, [X8]

  (171) 0x41c6a0 FCMGT	V20.2D, V18.2D, #0

  (171) 0x41c6a4 ORR	V24.16B, V20.16B, V20.16B

  (171) 0x41c6a8 XTN	V21.2S, V20.2D

  (171) 0x41c6ac FMOV	D19, X28

  (171) 0x41c6b0 MOV	V19.D[1], X30

  (171) 0x41c6b4 BSL	V24.16B, V19.16B, V23.16B

  (171) 0x41c6b8 BIT	V19.16B, V23.16B, V20.16B

  (171) 0x41c6bc FABS	V20.2D, V18.2D

  (171) 0x41c6c0 FMOV	X25, D19

  (171) 0x41c6c4 MOV	X22, V19.D[1]

  (171) 0x41c6c8 MOV	V17.S[1], W5

  (171) 0x41c6cc ADD	V22.2S, V17.2S, V2.2S

  (171) 0x41c6d0 SMIN	V22.2S, V0.2S, V22.2S

  (171) 0x41c6d4 BIF	V16.8B, V22.8B, V21.8B

  (171) 0x41c6d8 ADD	V17.2S, V17.2S, V3.2S

  (171) 0x41c6dc BIF	V17.8B, V22.8B, V21.8B

  (171) 0x41c6e0 MADD	X8, X9, X25, XZR

  (171) 0x41c6e4 MADD	X9, X9, X22, XZR

  (171) 0x41c6e8 MADD	X24, X15, X25, XZR

  (171) 0x41c6ec ADD	X10, X16, X8,LSL #3

  (171) 0x41c6f0 ADD	X8, X16, X9,LSL #3

  (171) 0x41c6f4 FMOV	W9, S16

  (171) 0x41c6f8 ORR	X16, XZR, X12

  (171) 0x41c6fc ORR	W12, WZR, W23

  (171) 0x41c700 ORR	X23, XZR, X11

  (171) 0x41c704 ORR	X11, XZR, X26

  (171) 0x41c708 ADD	X24, X14, X24,LSL #3

  (171) 0x41c70c LDR	D19, [X10, X27,SXTW #3]

  (171) 0x41c710 ADD	X19, X8, X6

  (171) 0x41c714 ADD	X8, X13, W5,SXTW #3

  (171) 0x41c718 SMOV	X5, V17.S[1]

  (171) 0x41c71c LDR	D22, [X24, X27,SXTW #3]

  (171) 0x41c720 MADD	X20, X15, X5, XZR

  (171) 0x41c724 LD1	{V7.D[1]}, [X8]

  (171) 0x41c728 MOV	W8, V16.S[1]

  (171) 0x41c72c ADD	X8, X13, W8,SXTW #3

  (171) 0x41c730 ADD	X20, X14, X20,LSL #3

  (171) 0x41c734 ADD	X20, X20, X6

  (171) 0x41c738 LD1	{V19.D[1]}, [X19]

  (171) 0x41c73c FDIV	V19.2D, V20.2D, V19.2D

  (171) 0x41c740 LDR	D20, [X13, X9,SXTW #3]

  (171) 0x41c744 ORR	X13, XZR, X3

  (171) 0x41c748 ORR	X3, XZR, X2

  (171) 0x41c74c ORR	X2, XZR, X17

  (171) 0x41c750 LDR	X17, [SP, #56]

  (171) 0x41c754 ADD	X1, X17, X1,LSL #3

  (171) 0x41c758 LD1	{V20.D[1]}, [X8]

  (171) 0x41c75c SMOV	X8, V17.S[0]

  (171) 0x41c760 MADD	X9, X15, X8, XZR

  (171) 0x41c764 MADD	X8, X0, X8, XZR

  (171) 0x41c768 ADD	X9, X14, X9,LSL #3

  (171) 0x41c76c ADD	X8, X18, X8,LSL #3

  (171) 0x41c770 LDR	D17, [X9, X27,SXTW #3]

  (171) 0x41c774 FMOV	X9, D24

  (171) 0x41c778 MADD	X26, X15, X9, XZR

  (171) 0x41c77c FMLA	V7.2D, V7.2D, V19.2D

  (171) 0x41c780 FSUB	V16.2D, V5.2D, V19.2D

  (171) 0x41c784 FSUB	V19.2D, V4.2D, V19.2D

  (171) 0x41c788 ADD	X26, X14, X26,LSL #3

  (171) 0x41c78c LDR	D21, [X26, X27,SXTW #3]

  (171) 0x41c790 LD1	{V17.D[1]}, [X20]

  (171) 0x41c794 MOV	X20, V24.D[1]

  (171) 0x41c798 FDIV	V7.2D, V7.2D, V20.2D

  (171) 0x41c79c MADD	X26, X15, X20, XZR

  (171) 0x41c7a0 ADD	X26, X14, X26,LSL #3

  (171) 0x41c7a4 ADD	X26, X26, X6

  (171) 0x41c7a8 LD1	{V21.D[1]}, [X26]

  (171) 0x41c7ac MADD	X26, X15, X22, XZR

  (171) 0x41c7b0 ADD	X26, X14, X26,LSL #3

  (171) 0x41c7b4 ADD	X26, X26, X6

  (171) 0x41c7b8 LD1	{V22.D[1]}, [X26]

  (171) 0x41c7bc FSUB	V23.2D, V22.2D, V17.2D

  (171) 0x41c7c0 FSUB	V24.2D, V21.2D, V22.2D

  (171) 0x41c7c4 FABD	V17.2D, V22.2D, V17.2D

  (171) 0x41c7c8 FABD	V21.2D, V21.2D, V22.2D

  (171) 0x41c7cc FMUL	V23.2D, V24.2D, V23.2D

  (171) 0x41c7d0 FCMLE	V20.2D, V23.2D, #0

  (171) 0x41c7d4 FCMGT	V23.2D, V24.2D, #0

  (171) 0x41c7d8 FNEG	V24.2D, V19.2D

  (171) 0x41c7dc BIF	V19.16B, V24.16B, V23.16B

  (171) 0x41c7e0 FMINNM	V23.2D, V17.2D, V21.2D

  (171) 0x41c7e4 FMUL	V17.2D, V17.2D, V7.2D

  (171) 0x41c7e8 FMLA	V17.2D, V21.2D, V16.2D

  (171) 0x41c7ec FMUL	V17.2D, V17.2D, V6.2D

  (171) 0x41c7f0 FMINNM	V17.2D, V23.2D, V17.2D

  (171) 0x41c7f4 FMUL	V17.2D, V17.2D, V19.2D

  (171) 0x41c7f8 BIC	V17.16B, V17.16B, V20.16B

  (171) 0x41c7fc FADD	V17.2D, V17.2D, V22.2D

  (171) 0x41c800 FMUL	V17.2D, V17.2D, V18.2D

  (171) 0x41c804 STR	D17, [X1, X27,SXTW #3]

  (171) 0x41c808 MADD	X1, X2, X30, XZR

  (171) 0x41c80c FABS	V25.2D, V17.2D

  (171) 0x41c810 ADD	X1, X17, X1,LSL #3

  (171) 0x41c814 ORR	X17, XZR, X2

  (171) 0x41c818 ORR	X2, XZR, X3

  (171) 0x41c81c ORR	X3, XZR, X13

  (171) 0x41c820 ORR	X13, XZR, X21

  (171) 0x41c824 LDUR	X21, [X29, #464]

  (171) 0x41c828 ADD	X1, X1, X6

  (171) 0x41c82c ST1	{V17.D[1]}, [X1]

  (171) 0x41c830 MADD	X1, X0, X25, XZR

  (171) 0x41c834 LDR	D21, [X24, X27,SXTW #3]

  (171) 0x41c838 LDR	D22, [X10, X27,SXTW #3]

  (171) 0x41c83c LDR	D19, [X8, X27,SXTW #3]

  (171) 0x41c840 MADD	X8, X0, X9, XZR

  (171) 0x41c844 ADD	X1, X18, X1,LSL #3

  (171) 0x41c848 SUBS	X21, X21, #2

  (171) 0x41c84c ADD	X8, X18, X8,LSL #3

  (171) 0x41c850 LDR	D18, [X1, X27,SXTW #3]

  (171) 0x41c854 MADD	X1, X0, X22, XZR

  (171) 0x41c858 LDR	D20, [X8, X27,SXTW #3]

  (171) 0x41c85c MADD	X8, X0, X5, XZR

  (171) 0x41c860 ADD	X1, X18, X1,LSL #3

  (171) 0x41c864 ADD	X8, X18, X8,LSL #3

  (171) 0x41c868 ADD	X1, X1, X6

  (171) 0x41c86c ADD	X8, X8, X6

  (171) 0x41c870 LD1	{V21.D[1]}, [X26]

  (171) 0x41c874 LD1	{V22.D[1]}, [X19]

  (171) 0x41c878 LD1	{V19.D[1]}, [X8]

  (171) 0x41c87c MADD	X8, X0, X20, XZR

  (171) 0x41c880 ORR	X26, XZR, X11

  (171) 0x41c884 ORR	X11, XZR, X23

  (171) 0x41c888 ORR	W23, WZR, W12

  (171) 0x41c88c ORR	X12, XZR, X16

  (171) 0x41c890 ADD	X8, X18, X8,LSL #3

  (171) 0x41c894 LD1	{V18.D[1]}, [X1]

  (171) 0x41c898 ADD	X8, X8, X6

  (171) 0x41c89c LD1	{V20.D[1]}, [X8]

  (171) 0x41c8a0 MADD	X8, X3, X28, XZR

  (171) 0x41c8a4 ADD	X8, X2, X8,LSL #3

  (171) 0x41c8a8 FMUL	V21.2D, V22.2D, V21.2D

  (171) 0x41c8ac FSUB	V23.2D, V18.2D, V19.2D

  (171) 0x41c8b0 FABD	V19.2D, V18.2D, V19.2D

  (171) 0x41c8b4 FDIV	V21.2D, V25.2D, V21.2D

  (171) 0x41c8b8 FSUB	V24.2D, V20.2D, V18.2D

  (171) 0x41c8bc FABD	V20.2D, V20.2D, V18.2D

  (171) 0x41c8c0 FMUL	V7.2D, V19.2D, V7.2D

  (171) 0x41c8c4 FMLA	V7.2D, V20.2D, V16.2D

  (171) 0x41c8c8 FMUL	V23.2D, V24.2D, V23.2D

  (171) 0x41c8cc FCMGT	V24.2D, V24.2D, #0

  (171) 0x41c8d0 FCMLE	V16.2D, V23.2D, #0

  (171) 0x41c8d4 FMUL	V7.2D, V7.2D, V6.2D

  (171) 0x41c8d8 FSUB	V21.2D, V4.2D, V21.2D

  (171) 0x41c8dc FNEG	V22.2D, V21.2D

  (171) 0x41c8e0 BIF	V21.16B, V22.16B, V24.16B

  (171) 0x41c8e4 FMINNM	V22.2D, V19.2D, V20.2D

  (171) 0x41c8e8 FMINNM	V7.2D, V22.2D, V7.2D

  (171) 0x41c8ec FMUL	V7.2D, V21.2D, V7.2D

  (171) 0x41c8f0 BIC	V7.16B, V7.16B, V16.16B

  (171) 0x41c8f4 FADD	V7.2D, V7.2D, V18.2D

  (171) 0x41c8f8 FMUL	V7.2D, V7.2D, V17.2D

  (171) 0x41c8fc STR	D7, [X8, X27,SXTW #3]

  (171) 0x41c900 MADD	X8, X3, X30, XZR

  (171) 0x41c904 ADD	X8, X2, X8,LSL #3

  (171) 0x41c908 ADD	X8, X8, X6

  (171) 0x41c90c ST1	{V7.D[1]}, [X8]

  (171) 0x41c910 B.NE	41c620

(169) 0x41c914 LDP	X9, X8, [SP, #16]

(169) 0x41c918 LDR	W24, [SP, #48]

(169) 0x41c91c LDR	X25, [SP, #40]

(169) 0x41c920 LDP	W16, W27, [SP, #32]

(169) 0x41c924 LDP	X28, X22, [SP, #64]

(169) 0x41c928 LDR	X30, [SP, #56]

(169) 0x41c92c CMP	X8, X9

(169) 0x41c930 B.EQ	41c538

(169) 0x41c934 FMOV	D0, #2.0000000

(169) 0x41c938 FMOV	D1, #1.0000000

(169) 0x41c93c ORR	X6, XZR, #3840

(169) 0x41c940 SUB	W5, WZR, W26

(169) 0x41c944 MOVK	X6, #16325

(169) 0x41c948 B	41c970

  (170) 0x41c94c FADD	D3, D5, D6

  (170) 0x41c950 MADD	X8, X3, X20, XZR

  (170) 0x41c954 ADD	X4, X4, #1

  (170) 0x41c958 FMUL	D2, D3, D2

  (170) 0x41c95c ADD	X8, X2, X8,LSL #3

  (170) 0x41c960 STR	D2, [X8, X7,SXTW #3]

  (170) 0x41c964 LDUR	X8, [X29, #456]

  (170) 0x41c968 CMP	X8, X4

  (170) 0x41c96c B.EQ	41c538

  (170) 0x41c970 SDIV	X10, X4, X26

  (170) 0x41c974 ADD	W9, W25, W4

  (170) 0x41c978 ADD	W8, W23, W10

  (170) 0x41c97c MADD	W7, W5, W10, W9

  (170) 0x41c980 SBFM	X20, X8, #0, #31

  (170) 0x41c984 MADD	X8, X12, X20, XZR

  (170) 0x41c988 ADD	X8, X11, X8,LSL #3

  (170) 0x41c98c LDR	D2, [X8, X7,SXTW #3]

  (170) 0x41c990 FCMP	D2, #0

  (170) 0x41c994 B.LE	41c9ac

  (170) 0x41c998 ADD	W8, W24, W10

  (170) 0x41c99c SUB	W9, W20, #2

  (170) 0x41c9a0 ORR	X10, XZR, X20

  (170) 0x41c9a4 SBFM	X19, X8, #0, #31

  (170) 0x41c9a8 B	41c9c8

  (170) 0x41c9ac ADD	W8, W20, #1

  (170) 0x41c9b0 ADD	W9, W24, W10

  (170) 0x41c9b4 ORR	X19, XZR, X20

  (170) 0x41c9b8 CMP	W16, W8

  (170) 0x41c9bc SBFM	X10, X9, #0, #31

  (170) 0x41c9c0 CSINC	W8, W16, W20, #11

  (170) 0x41c9c4 ORR	W9, WZR, W8

  (170) 0x41c9c8 MADD	X1, X28, X19, XZR

  (170) 0x41c9cc FABS	D3, D2

  (170) 0x41c9d0 SBFM	X9, X9, #0, #31

  (170) 0x41c9d4 MADD	X21, X15, X9, XZR

  (170) 0x41c9d8 ADD	X1, X22, X1,LSL #3

  (170) 0x41c9dc LDR	D4, [X1, X7,SXTW #3]

  (170) 0x41c9e0 ADD	X21, X14, X21,LSL #3

  (170) 0x41c9e4 LDR	D5, [X21, X7,SXTW #3]

  (170) 0x41c9e8 MADD	X21, X15, X10, XZR

  (170) 0x41c9ec ADD	X21, X14, X21,LSL #3

  (170) 0x41c9f0 FDIV	D7, D3, D4

  (170) 0x41c9f4 LDR	D3, [X13, X20,LSL #3]

  (170) 0x41c9f8 LDR	D4, [X13, X8,SXTW #3]

  (170) 0x41c9fc MADD	X8, X15, X19, XZR

  (170) 0x41ca00 ADD	X8, X14, X8,LSL #3

  (170) 0x41ca04 LDR	D6, [X8, X7,SXTW #3]

  (170) 0x41ca08 FSUB	D16, D6, S5

  (170) 0x41ca0c LDR	D5, [X21, X7,SXTW #3]

  (170) 0x41ca10 FMADD	D3, D7, D3, D3

  (170) 0x41ca14 FSUB	D17, D5, S6

  (170) 0x41ca18 MOVI	D5, #0

  (170) 0x41ca1c FMUL	D18, D17, D16

  (170) 0x41ca20 FDIV	D3, D3, D4

  (170) 0x41ca24 FSUB	D4, D0, S7

  (170) 0x41ca28 FCMP	D18, #0

  (170) 0x41ca2c MOVI	D18, #0

  (170) 0x41ca30 B.LE	41ca68

  (170) 0x41ca34 FSUB	D7, D1, S7

  (170) 0x41ca38 FCMP	D17, #0

  (170) 0x41ca3c FABS	D16, D16

  (170) 0x41ca40 FABS	D17, D17

  (170) 0x41ca44 FNEG	D18, D7

  (170) 0x41ca48 FCSEL	D7, D7, D18, #12

  (170) 0x41ca4c FMINNM	D18, D16, D17

  (170) 0x41ca50 FMUL	D16, D16, D3

  (170) 0x41ca54 FMADD	D16, D17, D4, D16

  (170) 0x41ca58 FMOV	D17, X6

  (170) 0x41ca5c FMUL	D16, D16, D17

  (170) 0x41ca60 FMINNM	D16, D18, D16

  (170) 0x41ca64 FMUL	D18, D16, D7

  (170) 0x41ca68 FADD	D6, D18, D6

  (170) 0x41ca6c MADD	X21, X17, X20, XZR

  (170) 0x41ca70 MADD	X9, X0, X9, XZR

  (170) 0x41ca74 FMUL	D2, D6, D2

  (170) 0x41ca78 ADD	X21, X30, X21,LSL #3

  (170) 0x41ca7c ADD	X9, X18, X9,LSL #3

  (170) 0x41ca80 MADD	X19, X0, X19, XZR

  (170) 0x41ca84 ADD	X19, X18, X19,LSL #3

  (170) 0x41ca88 STR	D2, [X21, X7,SXTW #3]

  (170) 0x41ca8c LDR	D7, [X9, X7,SXTW #3]

  (170) 0x41ca90 MADD	X9, X0, X10, XZR

  (170) 0x41ca94 LDR	D6, [X19, X7,SXTW #3]

  (170) 0x41ca98 ADD	X9, X18, X9,LSL #3

  (170) 0x41ca9c LDR	D16, [X9, X7,SXTW #3]

  (170) 0x41caa0 FSUB	D7, D6, S7

  (170) 0x41caa4 FSUB	D16, D16, S6

  (170) 0x41caa8 FMUL	D17, D16, D7

  (170) 0x41caac FCMP	D17, #0

  (170) 0x41cab0 B.LE	41c94c

  (170) 0x41cab4 LDR	D17, [X8, X7,SXTW #3]

  (170) 0x41cab8 LDR	D18, [X1, X7,SXTW #3]

  (170) 0x41cabc FABS	D5, D2

  (170) 0x41cac0 FABS	D7, D7

  (170) 0x41cac4 FCMP	D16, #0

  (170) 0x41cac8 FABS	D16, D16

  (170) 0x41cacc FMUL	D3, D7, D3

  (170) 0x41cad0 FMADD	D3, D16, D4, D3

  (170) 0x41cad4 FMOV	D4, X6

  (170) 0x41cad8 FMUL	D17, D18, D17

  (170) 0x41cadc FMUL	D3, D3, D4

  (170) 0x41cae0 FDIV	D5, D5, D17

  (170) 0x41cae4 FSUB	D5, D1, S5

  (170) 0x41cae8 FNEG	D17, D5

  (170) 0x41caec FCSEL	D5, D5, D17, #12

  (170) 0x41caf0 FMINNM	D17, D7, D16

  (170) 0x41caf4 FMINNM	D3, D17, D3

  (170) 0x41caf8 FMUL	D5, D5, D3

  (170) 0x41cafc B	41c94c

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.83 to 4.37 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 0.50 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.58	4.58	4.50	4.50	4.42	4.42	0.00	0.00	0.00	0.00	5.83	5.50	5.67	5.50	5.50
cycles	1.50	1.50	4.58	4.58	4.50	4.50	4.42	4.42	0.00	0.00	0.00	0.00	5.83	5.50	5.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

6% of peak load performance is reached (6.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W19, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W10, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W19, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W25, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
CCMP W9, W25, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41c548 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W27, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W26, W9, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c4e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X22, W26, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X22, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [X29, #1000]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X10, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X9, X10, X22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LE 41c568 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 0.50 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.58	4.58	4.50	4.50	4.42	4.42	0.00	0.00	0.00	0.00	5.83	5.50	5.67	5.50	5.50
cycles	1.50	1.50	4.58	4.58	4.50	4.50	4.42	4.42	0.00	0.00	0.00	0.00	5.83	5.50	5.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

6% of peak load performance is reached (6.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W19, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W10, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W19, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W25, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
CCMP W9, W25, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41c548 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W27, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W26, W9, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c4e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X22, W26, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X22, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [X29, #1000]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X10, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X9, X10, X22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LE 41c568 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.71	2.99
▼Loop 169 - advec_cell.cpp:157-202 - exec–	0.00	0.00
○Loop 171 - advec_cell.cpp:158-202 - exec	3.71	2.97
○Loop 170 - advec_cell.cpp:158-202 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code