OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:136-140 [...]	Coverage (incl. loops): 1.30% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 136 - 140

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41be80 SUB	SP, SP, #192

0x41be84 STP	X29, X30, [SP, #96]

0x41be88 STP	X28, X27, [SP, #112]

0x41be8c STP	X26, X25, [SP, #128]

0x41be90 STP	X24, X23, [SP, #144]

0x41be94 STP	X22, X21, [SP, #160]

0x41be98 STP	X20, X19, [SP, #176]

0x41be9c ADD	X29, SP, #96

0x41bea0 LDR	W8, [X3]

0x41bea4 LDR	W22, [X2]

0x41bea8 LDR	W9, [X5]

0x41beac ADD	W8, W8, #4

0x41beb0 LDR	W23, [X4]

0x41beb4 ADD	W9, W9, #4

0x41beb8 CMP	W22, W8

0x41bebc CCMP	W23, W9, #0, #13

0x41bec0 B.GT	41c1b0

0x41bec4 SUB	W24, W22, #1

0x41bec8 SUB	W9, W9, W23

0x41becc LDR	W19, [X0]

0x41bed0 ORR	X21, XZR, X7

0x41bed4 ORR	X20, XZR, X6

0x41bed8 ADRP	X0,

0x41bedc ADD	X0, X0, #3304

0x41bee0 SUB	X3, X29, #28

0x41bee4 SUB	X4, X29, #8

0x41bee8 STUR	WZR, [X29, #484]

0x41beec ORR	W1, WZR, W19

0x41bef0 ADD	W25, W9, #1

0x41bef4 SUB	W8, W8, W24

0x41bef8 MOVN	X9, #0

0x41befc UMADDL	X26, W25, W8, X9

0x41bf00 MOVZ	W8, #1

0x41bf04 SUB	X5, X29, #16

0x41bf08 SUB	X6, X29, #24

0x41bf0c MOVZ	W2, #34

0x41bf10 MOVZ	W7, #1

0x41bf14 STP	X26, XZR, [X29, #1008]

0x41bf18 STUR	X8, [X29, #488]

0x41bf1c STR	X8, [SP]

0x41bf20 BL	4034d0

0x41bf24 LDP	X8, X1, [X29, #1008]

0x41bf28 CMP	X8, X26

0x41bf2c CSEL	X18, X8, X26, #11

0x41bf30 CMP	X1, X18

0x41bf34 B.GT	41c1a0

0x41bf38 LDP	X13, X17, [X29, #104]

0x41bf3c LDR	X11, [X29, #96]

0x41bf40 LDR	X8, [X21, #16]

0x41bf44 LDR	X9, [X21]

0x41bf48 LDR	X14, [X20, #16]

0x41bf4c LDR	X15, [X20]

0x41bf50 ADD	X20, X18, #1

0x41bf54 SUB	X18, X20, X1

0x41bf58 LDR	X10, [X11, #16]

0x41bf5c LDR	X11, [X11]

0x41bf60 LDR	X12, [X13, #16]

0x41bf64 LDR	X13, [X13]

0x41bf68 LDR	X16, [X17, #16]

0x41bf6c LDR	X17, [X17]

0x41bf70 CMP	X18, #2

0x41bf74 B.CS	41bf80

0x41bf78 ORR	X0, XZR, X1

0x41bf7c B	41c0fc

0x41bf80 STP	X18, X20, [SP, #16]

0x41bf84 AND	X18, X18, #8127

0x41bf88 SUB	W5, WZR, W25

0x41bf8c STR	W19, [SP, #36]

0x41bf90 ORR	X3, XZR, XZR

0x41bf94 ADD	X0, X1, X18

0x41bf98 STUR	X18, [X29, #472]

0x41bf9c ADD	W18, W23, W1

0x41bfa0 STR	X18, [SP, #48]

0x41bfa4 SUB	W18, W18, #1

0x41bfa8 STR	X18, [SP, #40]

(165) 0x41bfac ADD	X20, X1, X3

(165) 0x41bfb0 LDP	X2, X18, [SP, #40]

(165) 0x41bfb4 SDIV	X28, X20, X25

(165) 0x41bfb8 ADD	X20, X20, #1

(165) 0x41bfbc ADD	W21, W24, W28

(165) 0x41bfc0 SDIV	X30, X20, X25

(165) 0x41bfc4 ADD	W20, W2, W3

(165) 0x41bfc8 ADD	W2, W18, W3

(165) 0x41bfcc ADD	X3, X3, #2

(165) 0x41bfd0 SBFM	X21, X21, #0, #31

(165) 0x41bfd4 ADD	W26, W24, W30

(165) 0x41bfd8 MADD	X27, X9, X21, XZR

(165) 0x41bfdc SBFM	X26, X26, #0, #31

(165) 0x41bfe0 MADD	X4, X9, X26, XZR

(165) 0x41bfe4 MADD	X6, X13, X26, XZR

(165) 0x41bfe8 MADD	X7, X11, X26, XZR

(165) 0x41bfec ADD	X18, X8, X27,LSL #3

(165) 0x41bff0 ADD	X4, X8, X4,LSL #3

(165) 0x41bff4 ADD	X6, X12, X6,LSL #3

(165) 0x41bff8 ADD	X7, X10, X7,LSL #3

(165) 0x41bffc MADD	W20, W5, W28, W20

(165) 0x41c000 LDR	D0, [X18, X20,SXTW #3]

(165) 0x41c004 MADD	W19, W5, W30, W2

(165) 0x41c008 SBFM	X27, X19, #61, #31

(165) 0x41c00c ADD	W19, W19, #1

(165) 0x41c010 ADD	X18, X4, X27

(165) 0x41c014 ADD	W4, W22, W30

(165) 0x41c018 MADD	X30, X11, X21, XZR

(165) 0x41c01c ADD	X19, X6, W19,SXTW #3

(165) 0x41c020 ADD	X7, X7, X27

(165) 0x41c024 SBFM	X4, X4, #0, #31

(165) 0x41c028 ADD	X30, X10, X30,LSL #3

(165) 0x41c02c MADD	X4, X11, X4, XZR

(165) 0x41c030 LDR	D2, [X30, X20,SXTW #3]

(165) 0x41c034 ADD	X4, X10, X4,LSL #3

(165) 0x41c038 ADD	X4, X4, X27

(165) 0x41c03c LD1	{V0.D[1]}, [X18]

(165) 0x41c040 ADD	W18, W22, W28

(165) 0x41c044 SBFM	X18, X18, #0, #31

(165) 0x41c048 MADD	X18, X11, X18, XZR

(165) 0x41c04c ADD	X18, X10, X18,LSL #3

(165) 0x41c050 LD1	{V2.D[1]}, [X7]

(165) 0x41c054 MADD	W2, W5, W28, W2

(165) 0x41c058 MADD	X28, X13, X21, XZR

(165) 0x41c05c ADD	X28, X12, X28,LSL #3

(165) 0x41c060 LDR	D3, [X28, X2,SXTW #3]

(165) 0x41c064 LDR	D4, [X28, X20,SXTW #3]

(165) 0x41c068 ADD	X2, X6, X27

(165) 0x41c06c MADD	X6, X15, X26, XZR

(165) 0x41c070 LDR	D1, [X18, X20,SXTW #3]

(165) 0x41c074 ADD	X6, X14, X6,LSL #3

(165) 0x41c078 ADD	X6, X6, X27

(165) 0x41c07c LD1	{V3.D[1]}, [X19]

(165) 0x41c080 LD1	{V4.D[1]}, [X2]

(165) 0x41c084 MADD	X2, X15, X21, XZR

(165) 0x41c088 LD1	{V1.D[1]}, [X4]

(165) 0x41c08c ADD	X2, X14, X2,LSL #3

(165) 0x41c090 FADD	V0.2D, V1.2D, V0.2D

(165) 0x41c094 FADD	V1.2D, V2.2D, V4.2D

(165) 0x41c098 FADD	V0.2D, V0.2D, V3.2D

(165) 0x41c09c FSUB	V0.2D, V0.2D, V1.2D

(165) 0x41c0a0 STR	D0, [X2, X20,SXTW #3]

(165) 0x41c0a4 ST1	{V0.D[1]}, [X6]

(165) 0x41c0a8 MADD	X2, X17, X26, XZR

(165) 0x41c0ac LDR	D1, [X18, X20,SXTW #3]

(165) 0x41c0b0 LDR	D2, [X30, X20,SXTW #3]

(165) 0x41c0b4 MADD	X18, X17, X21, XZR

(165) 0x41c0b8 ADD	X2, X16, X2,LSL #3

(165) 0x41c0bc ADD	X18, X16, X18,LSL #3

(165) 0x41c0c0 ADD	X2, X2, X27

(165) 0x41c0c4 LD1	{V1.D[1]}, [X4]

(165) 0x41c0c8 LD1	{V2.D[1]}, [X7]

(165) 0x41c0cc FSUB	V0.2D, V0.2D, V1.2D

(165) 0x41c0d0 FADD	V0.2D, V0.2D, V2.2D

(165) 0x41c0d4 STR	D0, [X18, X20,SXTW #3]

(165) 0x41c0d8 LDUR	X18, [X29, #472]

(165) 0x41c0dc ST1	{V0.D[1]}, [X2]

(165) 0x41c0e0 CMP	X18, X3

(165) 0x41c0e4 B.NE	41bfac

0x41c0e8 LDP	X18, X20, [SP, #16]

0x41c0ec LDUR	X1, [X29, #472]

0x41c0f0 LDR	W19, [SP, #36]

0x41c0f4 CMP	X18, X1

0x41c0f8 B.EQ	41c1a0

0x41c0fc SUB	W1, WZR, W25

0x41c100 SUB	X2, X23, #1

(166) 0x41c104 SDIV	X18, X0, X25

(166) 0x41c108 ADD	W4, W2, W0

(166) 0x41c10c ADD	W7, W23, W0

(166) 0x41c110 ADD	X0, X0, #1

(166) 0x41c114 ADD	W3, W24, W18

(166) 0x41c118 MADD	W4, W1, W18, W4

(166) 0x41c11c SBFM	X3, X3, #0, #31

(166) 0x41c120 MADD	X5, X9, X3, XZR

(166) 0x41c124 MADD	X6, X11, X3, XZR

(166) 0x41c128 ADD	X5, X8, X5,LSL #3

(166) 0x41c12c ADD	X6, X10, X6,LSL #3

(166) 0x41c130 LDR	D0, [X5, X4,SXTW #3]

(166) 0x41c134 ADD	W5, W22, W18

(166) 0x41c138 MADD	W18, W1, W18, W7

(166) 0x41c13c MADD	X7, X13, X3, XZR

(166) 0x41c140 LDR	D2, [X6, X4,SXTW #3]

(166) 0x41c144 SBFM	X5, X5, #0, #31

(166) 0x41c148 MADD	X5, X11, X5, XZR

(166) 0x41c14c ADD	X7, X12, X7,LSL #3

(166) 0x41c150 LDR	D3, [X7, X18,SXTW #3]

(166) 0x41c154 LDR	D4, [X7, X4,SXTW #3]

(166) 0x41c158 MADD	X18, X15, X3, XZR

(166) 0x41c15c ADD	X5, X10, X5,LSL #3

(166) 0x41c160 LDR	D1, [X5, X4,SXTW #3]

(166) 0x41c164 ADD	X18, X14, X18,LSL #3

(166) 0x41c168 FADD	D0, D1, D0

(166) 0x41c16c FADD	D1, D2, D4

(166) 0x41c170 FADD	D0, D0, D3

(166) 0x41c174 FSUB	D0, D0, S1

(166) 0x41c178 STR	D0, [X18, X4,SXTW #3]

(166) 0x41c17c MADD	X18, X17, X3, XZR

(166) 0x41c180 LDR	D1, [X5, X4,SXTW #3]

(166) 0x41c184 LDR	D2, [X6, X4,SXTW #3]

(166) 0x41c188 ADD	X18, X16, X18,LSL #3

(166) 0x41c18c FSUB	D0, D0, S1

(166) 0x41c190 FADD	D0, D0, D2

(166) 0x41c194 STR	D0, [X18, X4,SXTW #3]

(166) 0x41c198 CMP	X20, X0

(166) 0x41c19c B.NE	41c104

0x41c1a0 ADRP	X0,

0x41c1a4 ADD	X0, X0, #3328

0x41c1a8 ORR	W1, WZR, W19

0x41c1ac BL	403400

0x41c1b0 LDP	X20, X19, [SP, #176]

0x41c1b4 LDP	X22, X21, [SP, #160]

0x41c1b8 LDP	X24, X23, [SP, #144]

0x41c1bc LDP	X26, X25, [SP, #128]

0x41c1c0 LDP	X28, X27, [SP, #112]

0x41c1c4 LDP	X29, X30, [SP, #96]

0x41c1c8 ADD	SP, SP, #192

0x41c1cc RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 50% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.17 to 9.83 cycles (1.44x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.17 to 1.00 cycles (14.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 264 bytes. The binary function is storing 176 bytes.

General properties

nb instructions	94
loop length	376
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	7.75	7.75	7.67	7.67	7.58	7.58	0.00	0.00	0.00	0.00	14.17	13.83	14.00	7.50	7.50
cycles	4.00	4.00	7.75	7.75	7.67	7.67	7.58	7.58	0.00	0.00	0.00	0.00	14.17	13.83	14.00	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Overall L1	14.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.17 cycles. At this rate:

19% of peak load performance is reached (18.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.42 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41be80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W9, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W23, W9, #0, #13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	1	scal (25.0%)
B.GT 41c1b0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W9, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46ced8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W25, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W8, W8, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
UMADDL X26, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X1, [X29, #1008]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X18, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X1, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41c1a0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X17, [X29, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X29, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X20, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X20, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X18, X20, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X11, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X13, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 41bf80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 41c0fc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X18, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X18, X18, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB W5, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR W19, [SP, #36]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X0, X1, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STUR X18, [X29, #472]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W18, W23, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W18, W18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR X18, [SP, #40]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X18, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X1, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W19, [SP, #36]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X18, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41c1a0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X2, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46c1a0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3328	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.17 to 1.00 cycles (14.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 264 bytes. The binary function is storing 176 bytes.

General properties

nb instructions	94
loop length	376
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	7.75	7.75	7.67	7.67	7.58	7.58	0.00	0.00	0.00	0.00	14.17	13.83	14.00	7.50	7.50
cycles	4.00	4.00	7.75	7.75	7.67	7.67	7.58	7.58	0.00	0.00	0.00	0.00	14.17	13.83	14.00	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Overall L1	14.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.17 cycles. At this rate:

19% of peak load performance is reached (18.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.42 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41be80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W9, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W23, W9, #0, #13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	1	scal (25.0%)
B.GT 41c1b0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W24, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W9, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46ced8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W25, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W8, W8, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
UMADDL X26, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X1, [X29, #1008]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X18, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X1, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41c1a0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X17, [X29, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X29, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X20, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X20, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X18, X20, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X11, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X13, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 41bf80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 41c0fc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X18, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X18, X18, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB W5, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR W19, [SP, #36]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X0, X1, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STUR X18, [X29, #472]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W18, W23, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W18, W18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STR X18, [SP, #40]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X18, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X1, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W19, [SP, #36]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X18, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41c1a0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X2, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46c1a0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3328	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.30	1.05
○Loop 165 - advec_cell.cpp:137-140 - exec	1.30	1.04
○Loop 166 - advec_cell.cpp:137-140 - exec	0.00	0.00

Report Configuration

Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code