OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:65-110 [...]	Coverage (incl. loops): 3.26% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 65 - 110

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65: #pragma omp parallel for simd collapse(2)

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

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46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41b450 SUB	SP, SP, #240

0x41b454 STP	X29, X30, [SP, #144]

0x41b458 STP	X28, X27, [SP, #160]

0x41b45c STP	X26, X25, [SP, #176]

0x41b460 STP	X24, X23, [SP, #192]

0x41b464 STP	X22, X21, [SP, #208]

0x41b468 STP	X20, X19, [SP, #224]

0x41b46c ADD	X29, SP, #144

0x41b470 LDR	W8, [X2]

0x41b474 LDR	W24, [X4]

0x41b478 LDR	W19, [X5]

0x41b47c ADD	W22, W8, #1

0x41b480 LDR	W8, [X3]

0x41b484 ADD	W9, W24, #1

0x41b488 ADD	W10, W19, #4

0x41b48c ADD	W8, W8, #2

0x41b490 SUBS	W8, W8, W22

0x41b494 CCMP	W10, W9, #4, #12

0x41b498 B.LE	41b518

0x41b49c LDR	W27, [X0]

0x41b4a0 SUB	W26, W10, W9

0x41b4a4 MOVN	X9, #0

0x41b4a8 ORR	X20, XZR, X7

0x41b4ac ORR	X21, XZR, X6

0x41b4b0 ADRP	X0,

0x41b4b4 ADD	X0, X0, #3160

0x41b4b8 SUB	X3, X29, #36

0x41b4bc SUB	X4, X29, #16

0x41b4c0 STUR	WZR, [X29, #476]

0x41b4c4 ORR	W1, WZR, W27

0x41b4c8 UMADDL	X23, W26, W8, X9

0x41b4cc MOVZ	W8, #1

0x41b4d0 SUB	X5, X29, #24

0x41b4d4 SUB	X6, X29, #32

0x41b4d8 MOVZ	W2, #34

0x41b4dc MOVZ	W7, #1

0x41b4e0 STP	X23, XZR, [X29, #1000]

0x41b4e4 STUR	X8, [X29, #480]

0x41b4e8 STR	X8, [SP]

0x41b4ec BL	4034d0

0x41b4f0 LDP	X9, X8, [X29, #1000]

0x41b4f4 CMP	X9, X23

0x41b4f8 STUR	X8, [X29, #456]

0x41b4fc CSEL	X10, X9, X23, #11

0x41b500 CMP	X8, X10

0x41b504 B.LE	41b538

    (160) 0x41b508 ADRP	X0,

    (160) 0x41b50c ADD	X0, X0, #3184

    (160) 0x41b510 ORR	W1, WZR, W27

    (160) 0x41b514 BL	403400

    (160) 0x41b518 LDP	X20, X19, [SP, #224]

    (160) 0x41b51c LDP	X22, X21, [SP, #208]

    (160) 0x41b520 LDP	X24, X23, [SP, #192]

    (160) 0x41b524 LDP	X26, X25, [SP, #176]

    (160) 0x41b528 LDP	X28, X27, [SP, #160]

    (160) 0x41b52c LDP	X29, X30, [SP, #144]

    (160) 0x41b530 ADD	SP, SP, #240

    (160) 0x41b534 RET

    (160) 0x41b538 LDP	X0, X2, [X29, #128]

    (160) 0x41b53c LDR	X17, [X29, #120]

    (160) 0x41b540 LDP	X13, X15, [X29, #96]

    (160) 0x41b544 ADD	W11, W19, #2

    (160) 0x41b548 LDUR	X8, [X29, #456]

    (160) 0x41b54c LDR	X9, [X21, #16]

    (160) 0x41b550 LDR	X12, [X21]

    (160) 0x41b554 LDR	X14, [X20, #16]

    (160) 0x41b558 LDR	X16, [X20]

    (160) 0x41b55c LDR	X18, [X17, #16]

    (160) 0x41b560 LDR	X1, [X17]

    (160) 0x41b564 LDR	X3, [X0, #16]

    (160) 0x41b568 LDR	X17, [X0]

    (160) 0x41b56c ADD	X0, X10, #1

    (160) 0x41b570 LDR	X13, [X13, #8]

    (160) 0x41b574 LDR	X28, [X15, #16]

    (160) 0x41b578 LDR	X15, [X15]

    (160) 0x41b57c SUB	X10, X0, X8

    (160) 0x41b580 LDR	X30, [X2, #16]

    (160) 0x41b584 LDR	X8, [X2]

    (160) 0x41b588 STUR	X8, [X29, #464]

    (160) 0x41b58c CMP	X10, #2

    (160) 0x41b590 B.CS	41b59c

  (162) 0x41b594 LDUR	X4, [X29, #456]

  (162) 0x41b598 B	41b8f4

    (160) 0x41b59c LDUR	X8, [X29, #456]

    (160) 0x41b5a0 STP	X10, X0, [SP, #8]

    (160) 0x41b5a4 AND	X10, X10, #8127

    (160) 0x41b5a8 DUP	V0.2S, W11

    (160) 0x41b5ac MOVI	V2.2S, #1

    (160) 0x41b5b0 MVNI	V3.2S, #1

    (160) 0x41b5b4 FMOV	V4.2D, #1.0000000

    (160) 0x41b5b8 FMOV	V5.2D, #2.0000000

    (160) 0x41b5bc SUB	W21, WZR, W26

    (160) 0x41b5c0 STP	W11, W27, [SP, #24]

    (160) 0x41b5c4 ORR	X7, XZR, XZR

    (160) 0x41b5c8 DUP	V1.2S, W24

    (160) 0x41b5cc STUR	X10, [X29, #448]

    (160) 0x41b5d0 STP	X3, X1, [SP, #64]

    (160) 0x41b5d4 ORR	X0, XZR, X18

    (160) 0x41b5d8 ORR	X3, XZR, X17

    (160) 0x41b5dc ADD	X4, X8, X10

    (160) 0x41b5e0 ORR	X10, XZR, #3840

    (160) 0x41b5e4 ADD	W8, W24, W8

    (160) 0x41b5e8 STP	X28, X17, [SP, #48]

    (160) 0x41b5ec MOVK	X10, #16325

    (160) 0x41b5f0 STP	X24, X8, [SP, #32]

    (160) 0x41b5f4 DUP	V6.2D, X10

    (160) 0x41b5f8 HINT	#0

    (160) 0x41b5fc HINT	#0

      (159) 0x41b600 LDUR	X8, [X29, #456]

      (159) 0x41b604 ORR	X11, XZR, X26

      (159) 0x41b608 ORR	X17, XZR, X30

      (159) 0x41b60c ORR	X18, XZR, X15

      (159) 0x41b610 LDR	X1, [SP, #72]

      (159) 0x41b614 ADD	X10, X8, X7

      (159) 0x41b618 LDR	X8, [SP, #40]

      (159) 0x41b61c SDIV	X5, X10, X26

      (159) 0x41b620 ADD	X2, X10, #1

      (159) 0x41b624 ADD	W6, W22, W5

      (159) 0x41b628 SDIV	X2, X2, X26

      (159) 0x41b62c ADD	W19, W22, W2

      (159) 0x41b630 SBFM	X30, X6, #0, #31

      (159) 0x41b634 SBFM	X27, X19, #0, #31

      (159) 0x41b638 MADD	X23, X15, X27, XZR

      (159) 0x41b63c MADD	W20, W21, W5, W10

      (159) 0x41b640 MADD	W10, W21, W2, W10

      (159) 0x41b644 ADD	W10, W10, #1

      (159) 0x41b648 FMOV	S7, W20

      (159) 0x41b64c MOV	V7.S[1], W10

      (159) 0x41b650 ADD	W10, W8, W7

      (159) 0x41b654 LDR	X8, [SP, #48]

      (159) 0x41b658 ADD	X7, X7, #2

      (159) 0x41b65c ADD	X24, X8, X23,LSL #3

      (159) 0x41b660 ADD	V7.2S, V1.2S, V7.2S

      (159) 0x41b664 SSHLL	V7.2D, V7.2S, #32

      (159) 0x41b668 MADD	W5, W21, W5, W10

      (159) 0x41b66c ADD	W26, W5, #1

      (159) 0x41b670 MADD	W10, W21, W2, W10

      (159) 0x41b674 SBFM	X2, X26, #0, #31

      (159) 0x41b678 ADD	W10, W10, #2

      (159) 0x41b67c SBFM	X5, X10, #0, #31

      (159) 0x41b680 SBFM	X28, X10, #61, #31

      (159) 0x41b684 FMOV	D18, X2

      (159) 0x41b688 MADD	X2, X12, X30, XZR

      (159) 0x41b68c ADD	X2, X9, X2,LSL #3

      (159) 0x41b690 LDR	D16, [X2, X26,SXTW #3]

      (159) 0x41b694 MADD	X2, X16, X27, XZR

      (159) 0x41b698 FMOV	S17, W26

      (159) 0x41b69c MOV	V18.D[1], X5

      (159) 0x41b6a0 MADD	X5, X12, X27, XZR

      (159) 0x41b6a4 ADD	X5, X9, X5,LSL #3

      (159) 0x41b6a8 MOV	V17.S[1], W10

      (159) 0x41b6ac ADD	X10, X5, X28

      (159) 0x41b6b0 ADD	X5, X14, X2,LSL #3

      (159) 0x41b6b4 ADD	V20.2S, V17.2S, V2.2S

      (159) 0x41b6b8 ADD	V17.2S, V17.2S, V3.2S

      (159) 0x41b6bc SMIN	V20.2S, V0.2S, V20.2S

      (159) 0x41b6c0 SSHLL	V17.2D, V17.2S, #32

      (159) 0x41b6c4 LD1	{V16.D[1]}, [X10]

      (159) 0x41b6c8 MADD	X10, X16, X30, XZR

      (159) 0x41b6cc SSHLL	V20.2D, V20.2S, #32

      (159) 0x41b6d0 ADD	X19, X14, X10,LSL #3

      (159) 0x41b6d4 FCMGT	V19.2D, V16.2D, #0

      (159) 0x41b6d8 FABS	V22.2D, V16.2D

      (159) 0x41b6dc ORR	V21.16B, V19.16B, V19.16B

      (159) 0x41b6e0 BIF	V17.16B, V20.16B, V19.16B

      (159) 0x41b6e4 BSL	V21.16B, V18.16B, V7.16B

      (159) 0x41b6e8 BIT	V18.16B, V7.16B, V19.16B

      (159) 0x41b6ec BIF	V7.16B, V20.16B, V19.16B

      (159) 0x41b6f0 LDR	D19, [X13, X26,SXTW #3]

      (159) 0x41b6f4 FMOV	X2, D18

      (159) 0x41b6f8 MOV	X10, V18.D[1]

      (159) 0x41b6fc FMOV	X20, D7

      (159) 0x41b700 LDR	D18, [X19, X2,LSL #3]

      (159) 0x41b704 ADD	X6, X5, X10,LSL #3

      (159) 0x41b708 ADD	X5, X13, X28

      (159) 0x41b70c ADD	X25, X24, X10,LSL #3

      (159) 0x41b710 LD1	{V19.D[1]}, [X5]

      (159) 0x41b714 MOV	X5, V7.D[1]

      (159) 0x41b718 LDR	D7, [X13, X20,LSL #3]

      (159) 0x41b71c ADD	X5, X13, X5,LSL #3

      (159) 0x41b720 LD1	{V18.D[1]}, [X6]

      (159) 0x41b724 LD1	{V7.D[1]}, [X5]

      (159) 0x41b728 MADD	X5, X15, X30, XZR

      (159) 0x41b72c ORR	X15, XZR, X14

      (159) 0x41b730 ORR	X14, XZR, X12

      (159) 0x41b734 ORR	X12, XZR, X9

      (159) 0x41b738 ORR	W9, WZR, W22

      (159) 0x41b73c FMOV	X22, D17

      (159) 0x41b740 ADD	X20, X8, X5,LSL #3

      (159) 0x41b744 MOV	X5, V17.D[1]

      (159) 0x41b748 FMOV	X8, D21

      (159) 0x41b74c LDR	D20, [X20, X2,LSL #3]

      (159) 0x41b750 ADD	X23, X24, X5,LSL #3

      (159) 0x41b754 FDIV	V18.2D, V22.2D, V18.2D

      (159) 0x41b758 LD1	{V20.D[1]}, [X25]

      (159) 0x41b75c FMLA	V19.2D, V19.2D, V18.2D

      (159) 0x41b760 FSUB	V17.2D, V5.2D, V18.2D

      (159) 0x41b764 FSUB	V18.2D, V4.2D, V18.2D

      (159) 0x41b768 FNEG	V24.2D, V18.2D

      (159) 0x41b76c FDIV	V7.2D, V19.2D, V7.2D

      (159) 0x41b770 LDR	D19, [X20, X22,LSL #3]

      (159) 0x41b774 LD1	{V19.D[1]}, [X23]

      (159) 0x41b778 MOV	X23, V21.D[1]

      (159) 0x41b77c LDR	D21, [X20, X8,LSL #3]

      (159) 0x41b780 ADD	X24, X24, X23,LSL #3

      (159) 0x41b784 LD1	{V21.D[1]}, [X24]

      (159) 0x41b788 MADD	X24, X1, X30, XZR

      (159) 0x41b78c FSUB	V22.2D, V20.2D, V19.2D

      (159) 0x41b790 FABD	V19.2D, V20.2D, V19.2D

      (159) 0x41b794 ADD	X24, X0, X24,LSL #3

      (159) 0x41b798 FSUB	V23.2D, V21.2D, V20.2D

      (159) 0x41b79c FABD	V21.2D, V21.2D, V20.2D

      (159) 0x41b7a0 FMINNM	V25.2D, V19.2D, V21.2D

      (159) 0x41b7a4 FMUL	V19.2D, V19.2D, V7.2D

      (159) 0x41b7a8 FMUL	V22.2D, V23.2D, V22.2D

      (159) 0x41b7ac FCMGT	V23.2D, V23.2D, #0

      (159) 0x41b7b0 FMLA	V19.2D, V21.2D, V17.2D

      (159) 0x41b7b4 BIF	V18.16B, V24.16B, V23.16B

      (159) 0x41b7b8 FCMLE	V22.2D, V22.2D, #0

      (159) 0x41b7bc FMUL	V19.2D, V19.2D, V6.2D

      (159) 0x41b7c0 FMINNM	V19.2D, V25.2D, V19.2D

      (159) 0x41b7c4 FMUL	V18.2D, V19.2D, V18.2D

      (159) 0x41b7c8 BIC	V18.16B, V18.16B, V22.16B

      (159) 0x41b7cc FADD	V18.2D, V18.2D, V20.2D

      (159) 0x41b7d0 FMUL	V16.2D, V18.2D, V16.2D

      (159) 0x41b7d4 STR	D16, [X24, X26,SXTW #3]

      (159) 0x41b7d8 MADD	X24, X1, X27, XZR

      (159) 0x41b7dc LDR	X1, [SP, #64]

      (159) 0x41b7e0 FABS	V25.2D, V16.2D

      (159) 0x41b7e4 ADD	X24, X0, X24,LSL #3

      (159) 0x41b7e8 ADD	X24, X24, X28

      (159) 0x41b7ec ST1	{V16.D[1]}, [X24]

      (159) 0x41b7f0 MADD	X24, X3, X30, XZR

      (159) 0x41b7f4 LDR	D21, [X20, X2,LSL #3]

      (159) 0x41b7f8 LDR	D22, [X19, X2,LSL #3]

      (159) 0x41b7fc ADD	X24, X1, X24,LSL #3

      (159) 0x41b800 LDR	D20, [X24, X2,LSL #3]

      (159) 0x41b804 LDR	D18, [X24, X22,LSL #3]

      (159) 0x41b808 LDR	D19, [X24, X8,LSL #3]

      (159) 0x41b80c MADD	X8, X3, X27, XZR

      (159) 0x41b810 ORR	W22, WZR, W9

      (159) 0x41b814 ORR	X9, XZR, X12

      (159) 0x41b818 ORR	X12, XZR, X14

      (159) 0x41b81c ORR	X14, XZR, X15

      (159) 0x41b820 ORR	X15, XZR, X18

      (159) 0x41b824 LDUR	X18, [X29, #464]

      (159) 0x41b828 ADD	X8, X1, X8,LSL #3

      (159) 0x41b82c ADD	X10, X8, X10,LSL #3

      (159) 0x41b830 LD1	{V21.D[1]}, [X25]

      (159) 0x41b834 LD1	{V22.D[1]}, [X6]

      (159) 0x41b838 LD1	{V20.D[1]}, [X10]

      (159) 0x41b83c ADD	X10, X8, X5,LSL #3

      (159) 0x41b840 ADD	X8, X8, X23,LSL #3

      (159) 0x41b844 LD1	{V18.D[1]}, [X10]

      (159) 0x41b848 LD1	{V19.D[1]}, [X8]

      (159) 0x41b84c MADD	X8, X18, X30, XZR

      (159) 0x41b850 ORR	X30, XZR, X17

      (159) 0x41b854 ADD	X8, X17, X8,LSL #3

      (159) 0x41b858 FMUL	V21.2D, V22.2D, V21.2D

      (159) 0x41b85c FDIV	V21.2D, V25.2D, V21.2D

      (159) 0x41b860 FSUB	V23.2D, V20.2D, V18.2D

      (159) 0x41b864 FABD	V18.2D, V20.2D, V18.2D

      (159) 0x41b868 FSUB	V24.2D, V19.2D, V20.2D

      (159) 0x41b86c FABD	V19.2D, V19.2D, V20.2D

      (159) 0x41b870 FMUL	V7.2D, V18.2D, V7.2D

      (159) 0x41b874 FMUL	V23.2D, V24.2D, V23.2D

      (159) 0x41b878 FCMGT	V24.2D, V24.2D, #0

      (159) 0x41b87c FMLA	V7.2D, V19.2D, V17.2D

      (159) 0x41b880 FCMLE	V17.2D, V23.2D, #0

      (159) 0x41b884 FMUL	V7.2D, V7.2D, V6.2D

      (159) 0x41b888 FSUB	V21.2D, V4.2D, V21.2D

      (159) 0x41b88c FNEG	V22.2D, V21.2D

      (159) 0x41b890 BIF	V21.16B, V22.16B, V24.16B

      (159) 0x41b894 FMINNM	V22.2D, V18.2D, V19.2D

      (159) 0x41b898 FMINNM	V7.2D, V22.2D, V7.2D

      (159) 0x41b89c FMUL	V7.2D, V21.2D, V7.2D

      (159) 0x41b8a0 BIC	V7.16B, V7.16B, V17.16B

      (159) 0x41b8a4 FADD	V7.2D, V7.2D, V20.2D

      (159) 0x41b8a8 FMUL	V7.2D, V7.2D, V16.2D

      (159) 0x41b8ac STR	D7, [X8, X26,SXTW #3]

      (159) 0x41b8b0 MADD	X8, X18, X27, XZR

      (159) 0x41b8b4 ORR	X26, XZR, X11

      (159) 0x41b8b8 ADD	X8, X17, X8,LSL #3

      (159) 0x41b8bc ADD	X8, X8, X28

      (159) 0x41b8c0 ST1	{V7.D[1]}, [X8]

      (159) 0x41b8c4 LDUR	X8, [X29, #448]

      (159) 0x41b8c8 CMP	X8, X7

      (159) 0x41b8cc B.NE	41b600

    (160) 0x41b8d0 LDUR	X10, [X29, #448]

    (160) 0x41b8d4 LDR	X24, [SP, #32]

    (160) 0x41b8d8 ORR	X18, XZR, X0

    (160) 0x41b8dc LDP	W11, W27, [SP, #24]

    (160) 0x41b8e0 LDP	X28, X17, [SP, #48]

    (160) 0x41b8e4 LDP	X3, X1, [SP, #64]

    (160) 0x41b8e8 LDP	X8, X0, [SP, #8]

    (160) 0x41b8ec CMP	X8, X10

    (160) 0x41b8f0 B.EQ	41b508

  (162) 0x41b8f4 FMOV	D0, #2.0000000

  (162) 0x41b8f8 FMOV	D1, #1.0000000

  (162) 0x41b8fc ORR	X7, XZR, #3840

  (162) 0x41b900 SUB	W5, WZR, W26

  (162) 0x41b904 SUB	W6, W24, #1

  (162) 0x41b908 MOVK	X7, #16325

  (162) 0x41b90c B	41b944

0x41b910 HINT	#0

0x41b914 HINT	#0

0x41b918 HINT	#0

0x41b91c HINT	#0

  (162) 0x41b920 LDUR	X8, [X29, #464]

  (162) 0x41b924 FADD	D3, D5, D6

  (162) 0x41b928 ADD	X4, X4, #1

  (162) 0x41b92c FMUL	D2, D3, D2

  (162) 0x41b930 MADD	X8, X8, X21, XZR

  (162) 0x41b934 ADD	X8, X30, X8,LSL #3

  (162) 0x41b938 STR	D2, [X8, X20,LSL #3]

  (162) 0x41b93c CMP	X0, X4

  (162) 0x41b940 B.EQ	41b508

  (162) 0x41b944 SDIV	X10, X4, X26

  (162) 0x41b948 ADD	W2, W24, W4

  (162) 0x41b94c ADD	W8, W22, W10

  (162) 0x41b950 MADD	W2, W5, W10, W2

  (162) 0x41b954 SBFM	X21, X8, #0, #31

  (162) 0x41b958 MADD	X8, X12, X21, XZR

  (162) 0x41b95c ADD	W2, W2, #1

  (162) 0x41b960 SBFM	X20, X2, #0, #31

  (162) 0x41b964 ADD	X8, X9, X8,LSL #3

  (162) 0x41b968 LDR	D2, [X8, X2,SXTW #3]

  (162) 0x41b96c FCMP	D2, #0

  (162) 0x41b970 B.LE	41b9a0

  (162) 0x41b974 ADD	W8, W6, W4

  (162) 0x41b978 ADD	W2, W24, W4

  (162) 0x41b97c ORR	X19, XZR, X20

  (162) 0x41b980 MADD	W8, W5, W10, W8

  (162) 0x41b984 MADD	W10, W5, W10, W2

  (162) 0x41b988 SBFM	X25, X10, #0, #31

  (162) 0x41b98c SBFM	X2, X8, #0, #31

  (162) 0x41b990 ORR	X10, XZR, X25

  (162) 0x41b994 B	41b9c4

0x41b998 HINT	#0

0x41b99c HINT	#0

(161) 0x41b9a0 ADD	W8, W24, W4

(161) 0x41b9a4 MADD	W8, W5, W10, W8

(161) 0x41b9a8 ADD	W10, W8, #2

(161) 0x41b9ac SBFM	X19, X8, #0, #31

(161) 0x41b9b0 CMP	W11, W10

(161) 0x41b9b4 CSEL	W10, W11, W10, #11

(161) 0x41b9b8 SBFM	X2, X10, #0, #31

(161) 0x41b9bc ORR	X10, XZR, X20

(161) 0x41b9c0 ORR	X25, XZR, X2

  (162) 0x41b9c4 MADD	X8, X16, X21, XZR

  (162) 0x41b9c8 FABS	D3, D2

  (162) 0x41b9cc ADD	X23, X14, X8,LSL #3

  (162) 0x41b9d0 MADD	X8, X15, X21, XZR

  (162) 0x41b9d4 LDR	D4, [X23, X10,LSL #3]

  (162) 0x41b9d8 FDIV	D7, D3, D4

  (162) 0x41b9dc LDR	D3, [X13, X20,LSL #3]

  (162) 0x41b9e0 LDR	D4, [X13, X25,LSL #3]

  (162) 0x41b9e4 ADD	X25, X28, X8,LSL #3

  (162) 0x41b9e8 LDR	D6, [X25, X10,LSL #3]

  (162) 0x41b9ec LDR	D5, [X25, X2,LSL #3]

  (162) 0x41b9f0 FSUB	D16, D6, S5

  (162) 0x41b9f4 LDR	D5, [X25, X19,LSL #3]

  (162) 0x41b9f8 FSUB	D17, D5, S6

  (162) 0x41b9fc MOVI	D5, #0

  (162) 0x41ba00 FMADD	D3, D7, D3, D3

  (162) 0x41ba04 FMUL	D18, D17, D16

  (162) 0x41ba08 FCMP	D18, #0

  (162) 0x41ba0c MOVI	D18, #0

  (162) 0x41ba10 FDIV	D3, D3, D4

  (162) 0x41ba14 FSUB	D4, D0, S7

  (162) 0x41ba18 B.LE	41ba50

  (162) 0x41ba1c FSUB	D7, D1, S7

  (162) 0x41ba20 FCMP	D17, #0

  (162) 0x41ba24 FABS	D16, D16

  (162) 0x41ba28 FABS	D17, D17

  (162) 0x41ba2c FNEG	D18, D7

  (162) 0x41ba30 FCSEL	D7, D7, D18, #12

  (162) 0x41ba34 FMINNM	D18, D16, D17

  (162) 0x41ba38 FMUL	D16, D16, D3

  (162) 0x41ba3c FMADD	D16, D17, D4, D16

  (162) 0x41ba40 FMOV	D17, X7

  (162) 0x41ba44 FMUL	D16, D16, D17

  (162) 0x41ba48 FMINNM	D16, D18, D16

  (162) 0x41ba4c FMUL	D18, D16, D7

  (162) 0x41ba50 FADD	D6, D18, D6

  (162) 0x41ba54 MADD	X8, X1, X21, XZR

  (162) 0x41ba58 FMUL	D2, D6, D2

  (162) 0x41ba5c ADD	X8, X18, X8,LSL #3

  (162) 0x41ba60 STR	D2, [X8, X20,LSL #3]

  (162) 0x41ba64 MADD	X8, X17, X21, XZR

  (162) 0x41ba68 ADD	X8, X3, X8,LSL #3

  (162) 0x41ba6c LDR	D6, [X8, X10,LSL #3]

  (162) 0x41ba70 LDR	D7, [X8, X2,LSL #3]

  (162) 0x41ba74 LDR	D16, [X8, X19,LSL #3]

  (162) 0x41ba78 FSUB	D7, D6, S7

  (162) 0x41ba7c FSUB	D16, D16, S6

  (162) 0x41ba80 FMUL	D17, D16, D7

  (162) 0x41ba84 FCMP	D17, #0

  (162) 0x41ba88 B.LE	41b920

  (162) 0x41ba8c LDR	D17, [X25, X10,LSL #3]

  (162) 0x41ba90 LDR	D18, [X23, X10,LSL #3]

  (162) 0x41ba94 FABS	D5, D2

  (162) 0x41ba98 FABS	D7, D7

  (162) 0x41ba9c FCMP	D16, #0

  (162) 0x41baa0 FABS	D16, D16

  (162) 0x41baa4 FMUL	D3, D7, D3

  (162) 0x41baa8 FMADD	D3, D16, D4, D3

  (162) 0x41baac FMOV	D4, X7

  (162) 0x41bab0 FMUL	D17, D18, D17

  (162) 0x41bab4 FMUL	D3, D3, D4

  (162) 0x41bab8 FDIV	D5, D5, D17

  (162) 0x41babc FSUB	D5, D1, S5

  (162) 0x41bac0 FNEG	D17, D5

  (162) 0x41bac4 FCSEL	D5, D5, D17, #12

  (162) 0x41bac8 FMINNM	D17, D7, D16

  (162) 0x41bacc FMINNM	D3, D17, D3

  (162) 0x41bad0 FMUL	D5, D5, D3

  (162) 0x41bad4 B	41b920

0x41bad8 HINT	#0

0x41badc HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.83 to 4.61 cycles (1.27x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 0.50 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.58	4.58	4.50	4.50	4.42	4.42	0.00	0.00	0.00	0.00	5.83	5.50	5.67	5.50	5.50
cycles	1.50	1.50	4.58	4.58	4.50	4.50	4.42	4.42	0.00	0.00	0.00	0.00	5.83	5.50	5.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

6% of peak load performance is reached (6.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41b450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W19, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W9, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W19, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41b518 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W26, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c4b0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X23, W26, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X9, X23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CSEL X10, X9, X23, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41b538 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 0.50 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.58	4.58	4.50	4.50	4.42	4.42	0.00	0.00	0.00	0.00	5.83	5.50	5.67	5.50	5.50
cycles	1.50	1.50	4.58	4.58	4.50	4.50	4.42	4.42	0.00	0.00	0.00	0.00	5.83	5.50	5.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

6% of peak load performance is reached (6.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41b450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W19, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W9, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W19, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41b518 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W26, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c4b0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X23, W26, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X9, X23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CSEL X10, X9, X23, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41b538 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.26	2.62
▼Loop 161 - context.h:46-69 - exec–	0.00	0.00
▼Loop 162 - advec_cell.cpp:65-110 - exec–	0.00	0.00
▼Loop 160 - advec_cell.cpp:65-110 - exec–	0.00	0.00
○Loop 159 - advec_cell.cpp:66-110 - exec	3.26	2.60

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code