OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage (incl. loops): 6.35% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp: 40 - 53

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40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41a320 SUB	SP, SP, #352

0x41a324 STP	X29, X30, [SP, #256]

0x41a328 STP	X28, X27, [SP, #272]

0x41a32c STP	X26, X25, [SP, #288]

0x41a330 STP	X24, X23, [SP, #304]

0x41a334 STP	X22, X21, [SP, #320]

0x41a338 STP	X20, X19, [SP, #336]

0x41a33c ADD	X29, SP, #256

0x41a340 LDR	W22, [X2]

0x41a344 LDR	W8, [X3]

0x41a348 LDR	W24, [X4]

0x41a34c ADD	W23, W22, #1

0x41a350 LDR	W10, [X5]

0x41a354 ADD	W8, W8, #3

0x41a358 ADD	W9, W24, #1

0x41a35c ADD	W10, W10, #3

0x41a360 SUBS	W8, W8, W23

0x41a364 CCMP	W10, W9, #4, #12

0x41a368 B.LE	41aab0

0x41a36c LDR	W1, [X0]

0x41a370 SUB	W25, W10, W9

0x41a374 MOVN	X9, #0

0x41a378 ORR	X21, XZR, X7

0x41a37c ORR	X28, XZR, X6

0x41a380 ADRP	X0,

0x41a384 ADD	X0, X0, #2944

0x41a388 SUB	X3, X29, #36

0x41a38c SUB	X4, X29, #16

0x41a390 STUR	WZR, [X29, #476]

0x41a394 STR	W1, [SP, #36]

0x41a398 UMADDL	X19, W25, W8, X9

0x41a39c MOVZ	W8, #1

0x41a3a0 SUB	X5, X29, #24

0x41a3a4 SUB	X6, X29, #32

0x41a3a8 MOVZ	W2, #34

0x41a3ac MOVZ	W7, #1

0x41a3b0 STP	X19, XZR, [X29, #1000]

0x41a3b4 STUR	X8, [X29, #480]

0x41a3b8 STR	X8, [SP]

0x41a3bc BL	4034d0

0x41a3c0 LDP	X8, X9, [X29, #1000]

0x41a3c4 CMP	X8, X19

0x41a3c8 STR	X9, [SP, #128]

0x41a3cc CSEL	X8, X8, X19, #11

0x41a3d0 CMP	X9, X8

0x41a3d4 B.GT	41aaa0

0x41a3d8 LDP	X12, X9, [X29, #152]

0x41a3dc LDP	X18, X13, [X29, #136]

0x41a3e0 LDP	X15, X17, [X29, #120]

0x41a3e4 ADD	X20, X8, #1

0x41a3e8 LDP	X0, X14, [X29, #104]

0x41a3ec LDR	X11, [X29, #96]

0x41a3f0 LDR	X8, [SP, #128]

0x41a3f4 SUB	X8, X20, X8

0x41a3f8 LDR	X5, [X21, #16]

0x41a3fc LDR	X6, [X21]

0x41a400 LDR	X19, [X11, #16]

0x41a404 LDR	X11, [X11]

0x41a408 LDR	X30, [X14, #16]

0x41a40c LDR	X21, [X14]

0x41a410 LDR	X14, [X15, #16]

0x41a414 LDR	X15, [X15]

0x41a418 LDR	X16, [X17, #16]

0x41a41c LDR	X17, [X17]

0x41a420 LDR	X10, [X0, #16]

0x41a424 LDR	X0, [X0]

0x41a428 LDR	X1, [X13, #16]

0x41a42c LDR	X13, [X13]

0x41a430 LDR	X2, [X12, #16]

0x41a434 LDR	X12, [X12]

0x41a438 LDR	X3, [X18, #16]

0x41a43c LDR	X18, [X18]

0x41a440 LDR	X7, [X9, #16]

0x41a444 LDR	X26, [X9]

0x41a448 STP	X0, X10, [X29, #968]

0x41a44c STP	X13, X1, [X29, #952]

0x41a450 STP	X12, X2, [X29, #936]

0x41a454 STP	X18, X3, [X29, #920]

0x41a458 CMP	X8, #2

0x41a45c B.CS	41a468

0x41a460 LDR	X27, [SP, #128]

0x41a464 B	41a8a8

0x41a468 STP	X8, X20, [SP, #8]

0x41a46c AND	X9, X8, #8127

0x41a470 LDR	X8, [SP, #128]

0x41a474 FMOV	V0.2D, #0.2500000

0x41a478 ORR	X20, XZR, XZR

0x41a47c STR	X24, [SP, #24]

0x41a480 ADD	X27, X8, X9

0x41a484 STP	X9, X21, [SP, #112]

0x41a488 SUB	W9, WZR, W25

0x41a48c ADD	W8, W24, W8

0x41a490 STP	X30, X19, [SP, #96]

0x41a494 STR	X28, [SP, #88]

0x41a498 STP	W23, W22, [SP, #80]

0x41a49c STP	X5, X25, [SP, #64]

0x41a4a0 STR	X6, [SP, #56]

0x41a4a4 STR	W9, [SP, #52]

0x41a4a8 STR	X8, [SP, #40]

(152) 0x41a4ac LDR	X8, [SP, #128]

(152) 0x41a4b0 LDR	X10, [SP, #40]

(152) 0x41a4b4 LDR	D1, [X28]

(152) 0x41a4b8 ADD	X8, X8, X20

(152) 0x41a4bc ADD	W18, W10, W20

(152) 0x41a4c0 LDR	W10, [SP, #52]

(152) 0x41a4c4 ADD	X20, X20, #2

(152) 0x41a4c8 ADD	X9, X8, #1

(152) 0x41a4cc SDIV	X8, X8, X25

(152) 0x41a4d0 DUP	V1.2D, V1.D[0]

(152) 0x41a4d4 ADD	W12, W23, W8

(152) 0x41a4d8 SDIV	X9, X9, X25

(152) 0x41a4dc ADD	W13, W23, W9

(152) 0x41a4e0 SBFM	X25, X12, #0, #31

(152) 0x41a4e4 MADD	X12, X6, X25, XZR

(152) 0x41a4e8 ADD	X12, X5, X12,LSL #3

(152) 0x41a4ec MADD	W24, W10, W8, W18

(152) 0x41a4f0 ADD	W8, W22, W8

(152) 0x41a4f4 SBFM	X28, X8, #0, #31

(152) 0x41a4f8 MADD	X8, X6, X28, XZR

(152) 0x41a4fc ADD	X8, X5, X8,LSL #3

(152) 0x41a500 MADD	X1, X11, X28, XZR

(152) 0x41a504 ADD	W21, W24, #1

(152) 0x41a508 LDR	D2, [X8, X24,SXTW #3]

(152) 0x41a50c LDR	D4, [X12, X24,SXTW #3]

(152) 0x41a510 LDR	D5, [X12, X21,SXTW #3]

(152) 0x41a514 MADD	W18, W10, W9, W18

(152) 0x41a518 ADD	W9, W22, W9

(152) 0x41a51c SBFM	X10, X9, #0, #31

(152) 0x41a520 MADD	X9, X6, X10, XZR

(152) 0x41a524 ORR	X30, XZR, X10

(152) 0x41a528 MADD	X2, X11, X10, XZR

(152) 0x41a52c LDR	X10, [SP, #104]

(152) 0x41a530 ADD	W0, W18, #2

(152) 0x41a534 ADD	W18, W18, #1

(152) 0x41a538 ADD	X9, X5, X9,LSL #3

(152) 0x41a53c SBFM	X19, X18, #61, #31

(152) 0x41a540 SBFM	X22, X13, #0, #31

(152) 0x41a544 MADD	X13, X6, X22, XZR

(152) 0x41a548 ADD	X13, X5, X13,LSL #3

(152) 0x41a54c MADD	X3, X11, X22, XZR

(152) 0x41a550 SBFM	X23, X0, #61, #31

(152) 0x41a554 STP	X30, X28, [X29, #904]

(152) 0x41a558 ADD	X18, X9, X19

(152) 0x41a55c ADD	X9, X9, X23

(152) 0x41a560 ADD	X1, X10, X1,LSL #3

(152) 0x41a564 ADD	X3, X10, X3,LSL #3

(152) 0x41a568 LDR	D3, [X1, X24,SXTW #3]

(152) 0x41a56c ADD	X4, X3, X19

(152) 0x41a570 LDR	D6, [X1, X21,SXTW #3]

(152) 0x41a574 ADD	X12, X3, X23

(152) 0x41a578 LD1	{V2.D[1]}, [X18]

(152) 0x41a57c ADD	X18, X10, X2,LSL #3

(152) 0x41a580 ADD	X2, X18, X19

(152) 0x41a584 LD1	{V3.D[1]}, [X2]

(152) 0x41a588 ADD	X2, X13, X19

(152) 0x41a58c ADD	X13, X13, X23

(152) 0x41a590 LD1	{V4.D[1]}, [X2]

(152) 0x41a594 MADD	X2, X11, X25, XZR

(152) 0x41a598 LD1	{V5.D[1]}, [X13]

(152) 0x41a59c ADD	X2, X10, X2,LSL #3

(152) 0x41a5a0 LDR	X10, [SP, #96]

(152) 0x41a5a4 FMUL	V2.2D, V3.2D, V2.2D

(152) 0x41a5a8 LDR	D3, [X2, X24,SXTW #3]

(152) 0x41a5ac LD1	{V3.D[1]}, [X4]

(152) 0x41a5b0 FMLA	V2.2D, V3.2D, V4.2D

(152) 0x41a5b4 LDR	D3, [X2, X21,SXTW #3]

(152) 0x41a5b8 LDR	D4, [X8, X21,SXTW #3]

(152) 0x41a5bc ADD	X8, X18, X23

(152) 0x41a5c0 LD1	{V6.D[1]}, [X8]

(152) 0x41a5c4 LD1	{V3.D[1]}, [X12]

(152) 0x41a5c8 LD1	{V4.D[1]}, [X9]

(152) 0x41a5cc LDR	X9, [SP, #120]

(152) 0x41a5d0 MADD	X12, X15, X30, XZR

(152) 0x41a5d4 MADD	X8, X9, X25, XZR

(152) 0x41a5d8 MADD	X9, X9, X22, XZR

(152) 0x41a5dc ADD	X8, X10, X8,LSL #3

(152) 0x41a5e0 ADD	X9, X10, X9,LSL #3

(152) 0x41a5e4 LDUR	X10, [X29, #456]

(152) 0x41a5e8 ADD	X9, X9, X23

(152) 0x41a5ec FMLA	V2.2D, V3.2D, V5.2D

(152) 0x41a5f0 LDR	D3, [X8, X21,SXTW #3]

(152) 0x41a5f4 MADD	X8, X15, X25, XZR

(152) 0x41a5f8 ADD	X18, X14, X8,LSL #3

(152) 0x41a5fc FMLA	V2.2D, V6.2D, V4.2D

(152) 0x41a600 MADD	X13, X10, X22, XZR

(152) 0x41a604 LDR	D4, [X18, X21,SXTW #3]

(152) 0x41a608 FMUL	V2.2D, V2.2D, V0.2D

(152) 0x41a60c LD1	{V3.D[1]}, [X9]

(152) 0x41a610 MADD	X9, X15, X22, XZR

(152) 0x41a614 ADD	X8, X14, X9,LSL #3

(152) 0x41a618 MADD	X9, X17, X22, XZR

(152) 0x41a61c FDIV	V1.2D, V1.2D, V2.2D

(152) 0x41a620 ADD	X0, X8, X23

(152) 0x41a624 MADD	X8, X17, X25, XZR

(152) 0x41a628 LD1	{V4.D[1]}, [X0]

(152) 0x41a62c ADD	X3, X16, X8,LSL #3

(152) 0x41a630 ADD	X8, X16, X9,LSL #3

(152) 0x41a634 MADD	X9, X15, X28, XZR

(152) 0x41a638 LDR	D5, [X3, X21,SXTW #3]

(152) 0x41a63c LDR	D6, [X3, X24,SXTW #3]

(152) 0x41a640 ADD	X6, X8, X23

(152) 0x41a644 ADD	X8, X8, X19

(152) 0x41a648 ADD	X2, X14, X9,LSL #3

(152) 0x41a64c ADD	X9, X14, X12,LSL #3

(152) 0x41a650 MADD	X12, X17, X30, XZR

(152) 0x41a654 ORR	X30, XZR, X26

(152) 0x41a658 ORR	X26, XZR, X7

(152) 0x41a65c ORR	X7, XZR, X17

(152) 0x41a660 ADD	X1, X9, X23

(152) 0x41a664 MADD	X9, X17, X28, XZR

(152) 0x41a668 ORR	X17, XZR, X16

(152) 0x41a66c ADD	X12, X16, X12,LSL #3

(152) 0x41a670 ADD	X4, X16, X9,LSL #3

(152) 0x41a674 ADD	X9, X12, X23

(152) 0x41a678 ADD	X5, X12, X19

(152) 0x41a67c MADD	X12, X10, X25, XZR

(152) 0x41a680 LDUR	X10, [X29, #464]

(152) 0x41a684 ORR	X16, XZR, X15

(152) 0x41a688 ORR	X15, XZR, X14

(152) 0x41a68c ORR	X14, XZR, X11

(152) 0x41a690 LDP	X28, X11, [X29, #952]

(152) 0x41a694 LDR	D2, [X4, X21,SXTW #3]

(152) 0x41a698 LD1	{V5.D[1]}, [X6]

(152) 0x41a69c LD1	{V6.D[1]}, [X8]

(152) 0x41a6a0 ADD	X13, X10, X13,LSL #3

(152) 0x41a6a4 ADD	X12, X10, X12,LSL #3

(152) 0x41a6a8 MADD	X10, X28, X25, XZR

(152) 0x41a6ac ADD	X13, X13, X23

(152) 0x41a6b0 ADD	X10, X11, X10,LSL #3

(152) 0x41a6b4 LD1	{V2.D[1]}, [X9]

(152) 0x41a6b8 FSUB	V5.2D, V6.2D, V5.2D

(152) 0x41a6bc LDR	D6, [X4, X24,SXTW #3]

(152) 0x41a6c0 FMUL	V4.2D, V5.2D, V4.2D

(152) 0x41a6c4 LDR	D5, [X2, X21,SXTW #3]

(152) 0x41a6c8 LD1	{V6.D[1]}, [X5]

(152) 0x41a6cc LD1	{V5.D[1]}, [X1]

(152) 0x41a6d0 FSUB	V2.2D, V6.2D, V2.2D

(152) 0x41a6d4 FMLA	V4.2D, V2.2D, V5.2D

(152) 0x41a6d8 FMLA	V3.2D, V4.2D, V1.2D

(152) 0x41a6dc STR	D3, [X12, X21,SXTW #3]

(152) 0x41a6e0 ST1	{V3.D[1]}, [X13]

(152) 0x41a6e4 LDR	D3, [X3, X21,SXTW #3]

(152) 0x41a6e8 LDR	D5, [X4, X21,SXTW #3]

(152) 0x41a6ec LDR	D2, [X10, X21,SXTW #3]

(152) 0x41a6f0 MADD	X10, X28, X22, XZR

(152) 0x41a6f4 LDR	D4, [X3, X24,SXTW #3]

(152) 0x41a6f8 LDR	X28, [SP, #88]

(152) 0x41a6fc ADD	X10, X11, X10,LSL #3

(152) 0x41a700 ORR	X11, XZR, X14

(152) 0x41a704 ORR	X14, XZR, X15

(152) 0x41a708 ORR	X15, XZR, X16

(152) 0x41a70c ORR	X16, XZR, X17

(152) 0x41a710 ORR	X17, XZR, X7

(152) 0x41a714 ORR	X7, XZR, X26

(152) 0x41a718 ORR	X26, XZR, X30

(152) 0x41a71c ADD	X10, X10, X23

(152) 0x41a720 LD1	{V3.D[1]}, [X6]

(152) 0x41a724 LD1	{V5.D[1]}, [X9]

(152) 0x41a728 LDP	X6, X3, [X29, #936]

(152) 0x41a72c LD1	{V2.D[1]}, [X10]

(152) 0x41a730 LD1	{V4.D[1]}, [X8]

(152) 0x41a734 MADD	X10, X6, X25, XZR

(152) 0x41a738 MADD	X9, X6, X22, XZR

(152) 0x41a73c ADD	X6, X3, X10,LSL #3

(152) 0x41a740 ADD	X9, X3, X9,LSL #3

(152) 0x41a744 LDR	D6, [X6, X21,SXTW #3]

(152) 0x41a748 LDR	D7, [X6, X24,SXTW #3]

(152) 0x41a74c ADD	X8, X9, X23

(152) 0x41a750 ADD	X3, X9, X19

(152) 0x41a754 FSUB	V3.2D, V5.2D, V3.2D

(152) 0x41a758 LDR	D5, [X4, X24,SXTW #3]

(152) 0x41a75c LD1	{V6.D[1]}, [X8]

(152) 0x41a760 FMUL	V3.2D, V3.2D, V6.2D

(152) 0x41a764 LD1	{V5.D[1]}, [X5]

(152) 0x41a768 LD1	{V7.D[1]}, [X3]

(152) 0x41a76c LDP	X10, X5, [X29, #920]

(152) 0x41a770 MADD	X9, X10, X25, XZR

(152) 0x41a774 MADD	X10, X10, X22, XZR

(152) 0x41a778 ADD	X4, X5, X9,LSL #3

(152) 0x41a77c ADD	X9, X5, X10,LSL #3

(152) 0x41a780 ADD	X5, X9, X23

(152) 0x41a784 MADD	X9, X30, X25, XZR

(152) 0x41a788 MADD	X10, X30, X22, XZR

(152) 0x41a78c LDR	X25, [SP, #72]

(152) 0x41a790 FSUB	V4.2D, V5.2D, V4.2D

(152) 0x41a794 FMLA	V3.2D, V4.2D, V7.2D

(152) 0x41a798 FMLA	V2.2D, V3.2D, V1.2D

(152) 0x41a79c STR	D2, [X4, X21,SXTW #3]

(152) 0x41a7a0 ST1	{V2.D[1]}, [X5]

(152) 0x41a7a4 LDR	D2, [X18, X21,SXTW #3]

(152) 0x41a7a8 ADD	X18, X7, X9,LSL #3

(152) 0x41a7ac ADD	X9, X7, X10,LSL #3

(152) 0x41a7b0 LDR	D3, [X2, X21,SXTW #3]

(152) 0x41a7b4 LDR	D4, [X12, X21,SXTW #3]

(152) 0x41a7b8 LDR	D5, [X18, X21,SXTW #3]

(152) 0x41a7bc LDR	D6, [X18, X24,SXTW #3]

(152) 0x41a7c0 ADD	X10, X9, X23

(152) 0x41a7c4 LD1	{V2.D[1]}, [X0]

(152) 0x41a7c8 ADD	X0, X9, X19

(152) 0x41a7cc LDP	X9, X2, [X29, #904]

(152) 0x41a7d0 LD1	{V3.D[1]}, [X1]

(152) 0x41a7d4 LD1	{V4.D[1]}, [X13]

(152) 0x41a7d8 LD1	{V5.D[1]}, [X10]

(152) 0x41a7dc LD1	{V6.D[1]}, [X0]

(152) 0x41a7e0 MADD	X2, X30, X2, XZR

(152) 0x41a7e4 MADD	X9, X30, X9, XZR

(152) 0x41a7e8 ADD	X2, X7, X2,LSL #3

(152) 0x41a7ec ADD	X9, X7, X9,LSL #3

(152) 0x41a7f0 ADD	X1, X9, X23

(152) 0x41a7f4 ADD	X9, X9, X19

(152) 0x41a7f8 LDP	W23, W22, [SP, #80]

(152) 0x41a7fc FSUB	V5.2D, V6.2D, V5.2D

(152) 0x41a800 LDR	D6, [X2, X24,SXTW #3]

(152) 0x41a804 FMUL	V2.2D, V5.2D, V2.2D

(152) 0x41a808 LDR	D5, [X2, X21,SXTW #3]

(152) 0x41a80c LD1	{V6.D[1]}, [X9]

(152) 0x41a810 LD1	{V5.D[1]}, [X1]

(152) 0x41a814 FSUB	V5.2D, V6.2D, V5.2D

(152) 0x41a818 FMLA	V2.2D, V5.2D, V3.2D

(152) 0x41a81c FMLA	V4.2D, V2.2D, V1.2D

(152) 0x41a820 STR	D4, [X12, X21,SXTW #3]

(152) 0x41a824 ST1	{V4.D[1]}, [X13]

(152) 0x41a828 LDR	D4, [X18, X21,SXTW #3]

(152) 0x41a82c LDR	D7, [X2, X21,SXTW #3]

(152) 0x41a830 LDR	D2, [X6, X21,SXTW #3]

(152) 0x41a834 LDR	D5, [X18, X24,SXTW #3]

(152) 0x41a838 LDR	D6, [X2, X24,SXTW #3]

(152) 0x41a83c LDR	D3, [X6, X24,SXTW #3]

(152) 0x41a840 LD1	{V4.D[1]}, [X10]

(152) 0x41a844 LD1	{V7.D[1]}, [X1]

(152) 0x41a848 LD1	{V2.D[1]}, [X8]

(152) 0x41a84c LD1	{V5.D[1]}, [X0]

(152) 0x41a850 LD1	{V6.D[1]}, [X9]

(152) 0x41a854 LD1	{V3.D[1]}, [X3]

(152) 0x41a858 LDR	X8, [SP, #112]

(152) 0x41a85c FSUB	V4.2D, V7.2D, V4.2D

(152) 0x41a860 FSUB	V5.2D, V6.2D, V5.2D

(152) 0x41a864 FMUL	V2.2D, V4.2D, V2.2D

(152) 0x41a868 LDR	D4, [X4, X21,SXTW #3]

(152) 0x41a86c FMLA	V2.2D, V5.2D, V3.2D

(152) 0x41a870 LD1	{V4.D[1]}, [X5]

(152) 0x41a874 FMLA	V4.2D, V2.2D, V1.2D

(152) 0x41a878 STR	D4, [X4, X21,SXTW #3]

(152) 0x41a87c ST1	{V4.D[1]}, [X5]

(152) 0x41a880 LDP	X6, X5, [SP, #56]

(152) 0x41a884 CMP	X8, X20

(152) 0x41a888 B.NE	41a4ac

0x41a88c LDP	X8, X20, [SP, #8]

0x41a890 LDP	X19, X9, [SP, #104]

0x41a894 LDR	X24, [SP, #24]

0x41a898 LDR	X30, [SP, #96]

0x41a89c LDR	X21, [SP, #120]

0x41a8a0 CMP	X8, X9

0x41a8a4 B.EQ	41aaa0

0x41a8a8 FMOV	D0, #0.2500000

0x41a8ac SUB	W8, WZR, W25

0x41a8b0 STUR	W8, [X29, #400]

0x41a8b4 HINT	#0

0x41a8b8 HINT	#0

0x41a8bc HINT	#0

(153) 0x41a8c0 SDIV	X8, X27, X25

(153) 0x41a8c4 LDUR	W12, [X29, #400]

(153) 0x41a8c8 ADD	W10, W24, W27

(153) 0x41a8cc LDR	D1, [X28]

(153) 0x41a8d0 LDP	X3, X4, [X29, #968]

(153) 0x41a8d4 ADD	X27, X27, #1

(153) 0x41a8d8 ADD	W9, W23, W8

(153) 0x41a8dc MADD	W18, W12, W8, W10

(153) 0x41a8e0 ADD	W8, W22, W8

(153) 0x41a8e4 ORR	X12, XZR, X20

(153) 0x41a8e8 ORR	X20, XZR, X21

(153) 0x41a8ec SBFM	X8, X8, #0, #31

(153) 0x41a8f0 MADD	X10, X6, X8, XZR

(153) 0x41a8f4 MADD	X0, X11, X8, XZR

(153) 0x41a8f8 ADD	W13, W18, #1

(153) 0x41a8fc ADD	X10, X5, X10,LSL #3

(153) 0x41a900 ADD	X1, X19, X0,LSL #3

(153) 0x41a904 SBFM	X0, X9, #0, #31

(153) 0x41a908 LDR	D2, [X10, X18,SXTW #3]

(153) 0x41a90c LDR	D3, [X1, X18,SXTW #3]

(153) 0x41a910 MADD	X9, X6, X0, XZR

(153) 0x41a914 MADD	X2, X11, X0, XZR

(153) 0x41a918 MADD	X3, X3, X0, XZR

(153) 0x41a91c ADD	X9, X5, X9,LSL #3

(153) 0x41a920 ADD	X2, X19, X2,LSL #3

(153) 0x41a924 ADD	X3, X4, X3,LSL #3

(153) 0x41a928 LDUR	X4, [X29, #440]

(153) 0x41a92c LDR	D4, [X2, X18,SXTW #3]

(153) 0x41a930 FMUL	D2, D3, D2

(153) 0x41a934 LDR	D3, [X9, X18,SXTW #3]

(153) 0x41a938 MADD	X4, X4, X0, XZR

(153) 0x41a93c FMADD	D2, D4, D3, D2

(153) 0x41a940 LDR	D3, [X9, X13,SXTW #3]

(153) 0x41a944 LDR	D4, [X2, X13,SXTW #3]

(153) 0x41a948 MADD	X9, X21, X0, XZR

(153) 0x41a94c MADD	X2, X17, X8, XZR

(153) 0x41a950 ORR	X21, XZR, X24

(153) 0x41a954 LDUR	X24, [X29, #448]

(153) 0x41a958 ADD	X9, X30, X9,LSL #3

(153) 0x41a95c ADD	X2, X16, X2,LSL #3

(153) 0x41a960 LDR	D6, [X2, X18,SXTW #3]

(153) 0x41a964 ADD	X4, X24, X4,LSL #3

(153) 0x41a968 ORR	X24, XZR, X21

(153) 0x41a96c ORR	X21, XZR, X20

(153) 0x41a970 ORR	X20, XZR, X12

(153) 0x41a974 FMADD	D2, D4, D3, D2

(153) 0x41a978 LDR	D3, [X10, X13,SXTW #3]

(153) 0x41a97c LDR	D4, [X1, X13,SXTW #3]

(153) 0x41a980 MADD	X10, X17, X0, XZR

(153) 0x41a984 MADD	X1, X15, X8, XZR

(153) 0x41a988 MADD	X8, X26, X8, XZR

(153) 0x41a98c ADD	X10, X16, X10,LSL #3

(153) 0x41a990 ADD	X1, X14, X1,LSL #3

(153) 0x41a994 ADD	X8, X7, X8,LSL #3

(153) 0x41a998 LDR	D5, [X10, X18,SXTW #3]

(153) 0x41a99c FMADD	D2, D4, D3, D2

(153) 0x41a9a0 LDR	D4, [X10, X13,SXTW #3]

(153) 0x41a9a4 FMUL	D2, D2, D0

(153) 0x41a9a8 FSUB	D4, D5, S4

(153) 0x41a9ac LDR	D5, [X1, X13,SXTW #3]

(153) 0x41a9b0 FDIV	D1, D1, D2

(153) 0x41a9b4 LDR	D2, [X9, X13,SXTW #3]

(153) 0x41a9b8 MADD	X9, X15, X0, XZR

(153) 0x41a9bc ADD	X9, X14, X9,LSL #3

(153) 0x41a9c0 LDR	D3, [X9, X13,SXTW #3]

(153) 0x41a9c4 FMUL	D3, D4, D3

(153) 0x41a9c8 LDR	D4, [X2, X13,SXTW #3]

(153) 0x41a9cc FSUB	D4, D6, S4

(153) 0x41a9d0 FMADD	D3, D4, D5, D3

(153) 0x41a9d4 FMADD	D2, D3, D1, D2

(153) 0x41a9d8 STR	D2, [X3, X13,SXTW #3]

(153) 0x41a9dc LDR	D2, [X4, X13,SXTW #3]

(153) 0x41a9e0 LDR	D3, [X10, X13,SXTW #3]

(153) 0x41a9e4 LDR	D4, [X10, X18,SXTW #3]

(153) 0x41a9e8 LDP	X10, X4, [X29, #936]

(153) 0x41a9ec LDR	D6, [X2, X13,SXTW #3]

(153) 0x41a9f0 MADD	X10, X10, X0, XZR

(153) 0x41a9f4 ADD	X10, X4, X10,LSL #3

(153) 0x41a9f8 FSUB	D3, D6, S3

(153) 0x41a9fc LDR	D6, [X2, X18,SXTW #3]

(153) 0x41aa00 LDP	X2, X4, [X29, #920]

(153) 0x41aa04 LDR	D5, [X10, X13,SXTW #3]

(153) 0x41aa08 MADD	X2, X2, X0, XZR

(153) 0x41aa0c FSUB	D4, D6, S4

(153) 0x41aa10 ADD	X2, X4, X2,LSL #3

(153) 0x41aa14 FMUL	D3, D3, D5

(153) 0x41aa18 LDR	D5, [X10, X18,SXTW #3]

(153) 0x41aa1c FMADD	D3, D4, D5, D3

(153) 0x41aa20 FMADD	D2, D3, D1, D2

(153) 0x41aa24 STR	D2, [X2, X13,SXTW #3]

(153) 0x41aa28 LDR	D2, [X9, X13,SXTW #3]

(153) 0x41aa2c MADD	X9, X26, X0, XZR

(153) 0x41aa30 LDR	D3, [X1, X13,SXTW #3]

(153) 0x41aa34 LDR	D4, [X3, X13,SXTW #3]

(153) 0x41aa38 ADD	X9, X7, X9,LSL #3

(153) 0x41aa3c LDR	D5, [X9, X13,SXTW #3]

(153) 0x41aa40 LDR	D6, [X9, X18,SXTW #3]

(153) 0x41aa44 FSUB	D5, D6, S5

(153) 0x41aa48 LDR	D6, [X8, X18,SXTW #3]

(153) 0x41aa4c FMUL	D2, D5, D2

(153) 0x41aa50 LDR	D5, [X8, X13,SXTW #3]

(153) 0x41aa54 FSUB	D5, D6, S5

(153) 0x41aa58 FMADD	D2, D5, D3, D2

(153) 0x41aa5c FMADD	D2, D2, D1, D4

(153) 0x41aa60 STR	D2, [X3, X13,SXTW #3]

(153) 0x41aa64 LDR	D4, [X9, X13,SXTW #3]

(153) 0x41aa68 LDR	D7, [X8, X13,SXTW #3]

(153) 0x41aa6c LDR	D2, [X10, X13,SXTW #3]

(153) 0x41aa70 LDR	D5, [X9, X18,SXTW #3]

(153) 0x41aa74 LDR	D6, [X8, X18,SXTW #3]

(153) 0x41aa78 LDR	D3, [X10, X18,SXTW #3]

(153) 0x41aa7c FSUB	D4, D7, S4

(153) 0x41aa80 FSUB	D5, D6, S5

(153) 0x41aa84 FMUL	D2, D4, D2

(153) 0x41aa88 LDR	D4, [X2, X13,SXTW #3]

(153) 0x41aa8c FMADD	D2, D5, D3, D2

(153) 0x41aa90 FMADD	D1, D2, D1, D4

(153) 0x41aa94 STR	D1, [X2, X13,SXTW #3]

(153) 0x41aa98 CMP	X12, X27

(153) 0x41aa9c B.NE	41a8c0

0x41aaa0 LDR	W1, [SP, #36]

0x41aaa4 ADRP	X0,

0x41aaa8 ADD	X0, X0, #2968

0x41aaac BL	403400

0x41aab0 LDP	X20, X19, [SP, #336]

0x41aab4 LDP	X22, X21, [SP, #320]

0x41aab8 LDP	X24, X23, [SP, #304]

0x41aabc LDP	X26, X25, [SP, #288]

0x41aac0 LDP	X28, X27, [SP, #272]

0x41aac4 LDP	X29, X30, [SP, #256]

0x41aac8 ADD	SP, SP, #352

0x41aacc RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.50 to 0.38 cycles (65.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 24.50 to 18.33 cycles (1.34x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.50 to 1.00 cycles (24.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 448 bytes. The binary function is storing 320 bytes.

General properties

nb instructions	124
loop length	496
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	6.75	6.75	6.67	6.67	6.58	6.58	0.50	0.50	0.50	0.50	24.50	24.17	24.33	13.50	13.50
cycles	4.00	4.00	6.75	6.75	6.67	6.67	6.58	6.58	0.50	0.50	0.50	0.50	24.50	24.17	24.33	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.13
Overall L1	24.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.50 cycles. At this rate:

19% of peak load performance is reached (18.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41a320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W10, W10, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41aab0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W25, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c380>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2944	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMADDL X19, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X19, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41aaa0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X18, X13, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X15, X17, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X20, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X0, X14, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X8, X20, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X26, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X0, X10, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X13, X1, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X2, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X3, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 41a468 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 41a8a8 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X8, X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X9, X8, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMOV V0.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X24, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X27, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X9, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W9, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W24, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X30, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP W23, W22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X5, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X6, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W9, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X24, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41aaa0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W8, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <46caa4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2968	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.50 to 1.00 cycles (24.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 448 bytes. The binary function is storing 320 bytes.

General properties

nb instructions	124
loop length	496
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	6.75	6.75	6.67	6.67	6.58	6.58	0.50	0.50	0.50	0.50	24.50	24.17	24.33	13.50	13.50
cycles	4.00	4.00	6.75	6.75	6.67	6.67	6.58	6.58	0.50	0.50	0.50	0.50	24.50	24.17	24.33	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.13
Overall L1	24.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.50 cycles. At this rate:

19% of peak load performance is reached (18.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41a320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W10, W10, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41aab0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W25, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c380>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2944	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMADDL X19, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X19, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41aaa0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X18, X13, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X15, X17, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X20, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X0, X14, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X8, X20, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X26, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X0, X10, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X13, X1, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X2, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X3, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 41a468 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 41a8a8 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X8, X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X9, X8, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMOV V0.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X24, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X27, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X9, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W9, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W24, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X30, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP W23, W22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X5, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X6, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W9, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X24, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41aaa0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W8, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <46caa4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2968	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.35	5.11
○Loop 152 - accelerate.cpp:41-53 - exec	6.35	5.08
○Loop 153 - accelerate.cpp:41-53 - exec	0.00	0.00

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code