OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage (incl. loops): 7.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 69 - 83

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69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x429a40 SUB	SP, SP, #368

0x429a44 STP	X29, X30, [SP, #272]

0x429a48 STP	X28, X27, [SP, #288]

0x429a4c STP	X26, X25, [SP, #304]

0x429a50 STP	X24, X23, [SP, #320]

0x429a54 STP	X22, X21, [SP, #336]

0x429a58 STP	X20, X19, [SP, #352]

0x429a5c ADD	X29, SP, #272

0x429a60 LDR	W8, [X2]

0x429a64 LDR	W24, [X4]

0x429a68 LDR	W10, [X5]

0x429a6c ADD	W22, W8, #1

0x429a70 LDR	W8, [X3]

0x429a74 ADD	W9, W24, #1

0x429a78 ADD	W10, W10, #2

0x429a7c ADD	W8, W8, #2

0x429a80 SUBS	W8, W8, W22

0x429a84 CCMP	W10, W9, #4, #12

0x429a88 B.LE	42a1d8

0x429a8c LDR	W1, [X0]

0x429a90 SUB	W25, W10, W9

0x429a94 MOVN	X9, #0

0x429a98 ORR	X20, XZR, X7

0x429a9c ORR	X21, XZR, X6

0x429aa0 ADRP	X0,

0x429aa4 ADD	X0, X0, #2440

0x429aa8 SUB	X3, X29, #36

0x429aac SUB	X4, X29, #16

0x429ab0 STUR	WZR, [X29, #476]

0x429ab4 STR	W1, [SP, #44]

0x429ab8 UMADDL	X19, W25, W8, X9

0x429abc MOVZ	W8, #1

0x429ac0 SUB	X5, X29, #24

0x429ac4 SUB	X6, X29, #32

0x429ac8 MOVZ	W2, #34

0x429acc MOVZ	W7, #1

0x429ad0 STP	X19, XZR, [X29, #1000]

0x429ad4 STUR	X8, [X29, #480]

0x429ad8 STR	X8, [SP]

0x429adc BL	4034d0

0x429ae0 LDP	X8, X9, [X29, #1000]

0x429ae4 CMP	X8, X19

0x429ae8 STUR	X9, [X29, #400]

0x429aec CSEL	X8, X8, X19, #11

0x429af0 CMP	X9, X8

0x429af4 B.GT	42a1c8

0x429af8 LDP	X3, X2, [X29, #160]

0x429afc LDP	X10, X9, [X29, #176]

0x429b00 LDP	X5, X4, [X29, #144]

0x429b04 ADD	X8, X8, #1

0x429b08 LDP	X1, X6, [X29, #128]

0x429b0c LDP	X16, X18, [X29, #112]

0x429b10 LDP	X14, X11, [X29, #96]

0x429b14 LDR	X13, [X21, #16]

0x429b18 LDR	X12, [X21]

0x429b1c LDUR	X23, [X29, #400]

0x429b20 SUB	X23, X8, X23

0x429b24 LDR	X19, [X3, #16]

0x429b28 LDR	X3, [X3]

0x429b2c STP	X12, X13, [X29, #920]

0x429b30 LDR	X27, [X20, #16]

0x429b34 LDR	X12, [X20]

0x429b38 LDR	X13, [X14, #16]

0x429b3c LDR	X14, [X14]

0x429b40 LDR	X15, [X16, #16]

0x429b44 LDR	X16, [X16]

0x429b48 LDR	X17, [X18, #16]

0x429b4c LDR	X18, [X18]

0x429b50 LDR	X0, [X1, #16]

0x429b54 LDR	X1, [X1]

0x429b58 LDR	X7, [X6, #16]

0x429b5c LDR	X6, [X6]

0x429b60 LDR	X20, [X5, #16]

0x429b64 LDR	X5, [X5]

0x429b68 LDR	X21, [X4, #16]

0x429b6c LDR	X28, [X4]

0x429b70 LDR	X4, [X2, #16]

0x429b74 LDR	X2, [X2]

0x429b78 STR	X8, [SP, #32]

0x429b7c STP	X19, X3, [X29, #968]

0x429b80 LDR	X3, [X10, #16]

0x429b84 LDR	X10, [X10]

0x429b88 STP	X2, X4, [X29, #944]

0x429b8c STUR	X3, [X29, #448]

0x429b90 LDR	X3, [X9, #16]

0x429b94 LDR	X9, [X9]

0x429b98 STUR	X10, [X29, #424]

0x429b9c CMP	X23, #2

0x429ba0 B.CS	429bb8

0x429ba4 LDUR	X23, [X29, #400]

0x429ba8 LDR	X30, [SP, #32]

0x429bac ORR	X26, XZR, X3

0x429bb0 ORR	X2, XZR, X9

0x429bb4 B	429fe4

0x429bb8 ORR	X10, XZR, X24

0x429bbc LDUR	X24, [X29, #400]

0x429bc0 STP	X23, X10, [SP, #16]

0x429bc4 AND	X23, X23, #8127

0x429bc8 FMOV	D0, #0.2500000

0x429bcc SUB	W26, WZR, W25

0x429bd0 ORR	X8, XZR, XZR

0x429bd4 STUR	X27, [X29, #384]

0x429bd8 STUR	W22, [X29, #380]

0x429bdc STP	X7, X11, [SP, #120]

0x429be0 STUR	X23, [X29, #392]

0x429be4 ADD	X23, X24, X23

0x429be8 ADD	W24, W10, W24

0x429bec STR	W26, [SP, #68]

0x429bf0 STP	X20, X6, [SP, #104]

0x429bf4 STP	X21, X5, [SP, #88]

0x429bf8 STP	X9, X3, [SP, #72]

0x429bfc STP	X28, X24, [SP, #48]

(308) 0x429c00 LDUR	X9, [X29, #400]

(308) 0x429c04 LDR	X11, [SP, #56]

(308) 0x429c08 ORR	X28, XZR, X1

(308) 0x429c0c ORR	X1, XZR, X0

(308) 0x429c10 ORR	X0, XZR, X18

(308) 0x429c14 ORR	X18, XZR, X17

(308) 0x429c18 ORR	X17, XZR, X16

(308) 0x429c1c ORR	X16, XZR, X15

(308) 0x429c20 ORR	X15, XZR, X14

(308) 0x429c24 ORR	X14, XZR, X13

(308) 0x429c28 ORR	X13, XZR, X12

(308) 0x429c2c ORR	X30, XZR, X25

(308) 0x429c30 ADD	X9, X9, X8

(308) 0x429c34 ADD	W5, W11, W8

(308) 0x429c38 LDR	W11, [SP, #68]

(308) 0x429c3c ADD	X8, X8, #2

(308) 0x429c40 ADD	X10, X9, #1

(308) 0x429c44 SDIV	X9, X9, X25

(308) 0x429c48 ADD	W3, W22, W9

(308) 0x429c4c SDIV	X10, X10, X25

(308) 0x429c50 ADD	W4, W22, W10

(308) 0x429c54 SBFM	X22, X4, #0, #31

(308) 0x429c58 MADD	X26, X12, X22, XZR

(308) 0x429c5c MADD	W2, W11, W9, W5

(308) 0x429c60 SBFM	X9, X3, #0, #31

(308) 0x429c64 ADD	W24, W2, #1

(308) 0x429c68 MADD	X20, X12, X9, XZR

(308) 0x429c6c LDUR	X12, [X29, #384]

(308) 0x429c70 ADD	W2, W2, #2

(308) 0x429c74 ADD	W3, W3, #1

(308) 0x429c78 ADD	X21, X12, X20,LSL #3

(308) 0x429c7c ADD	X20, X12, X26,LSL #3

(308) 0x429c80 LDR	D2, [X21, X24,SXTW #3]

(308) 0x429c84 LDR	D5, [X21, X2,SXTW #3]

(308) 0x429c88 MADD	W6, W11, W10, W5

(308) 0x429c8c LDUR	X11, [X29, #408]

(308) 0x429c90 MADD	X5, X11, X9, XZR

(308) 0x429c94 MADD	X7, X11, X22, XZR

(308) 0x429c98 LDUR	X11, [X29, #416]

(308) 0x429c9c ADD	W10, W6, #2

(308) 0x429ca0 SBFM	X10, X10, #61, #31

(308) 0x429ca4 ADD	X26, X20, X10

(308) 0x429ca8 ADD	X5, X11, X5,LSL #3

(308) 0x429cac ADD	X7, X11, X7,LSL #3

(308) 0x429cb0 LDR	D1, [X5, X24,SXTW #3]

(308) 0x429cb4 ADD	X25, X7, X10

(308) 0x429cb8 LDR	D3, [X5, X2,SXTW #3]

(308) 0x429cbc LD1	{V2.D[1]}, [X26]

(308) 0x429cc0 MADD	X26, X15, X22, XZR

(308) 0x429cc4 LD1	{V1.D[1]}, [X25]

(308) 0x429cc8 MADD	X25, X15, X9, XZR

(308) 0x429ccc ADD	X27, X14, X25,LSL #3

(308) 0x429cd0 ADD	X25, X14, X26,LSL #3

(308) 0x429cd4 LDR	D4, [X27, X24,SXTW #3]

(308) 0x429cd8 ADD	X5, X25, X10

(308) 0x429cdc LDR	D16, [X27, X2,SXTW #3]

(308) 0x429ce0 LD1	{V4.D[1]}, [X5]

(308) 0x429ce4 ADD	W5, W4, #1

(308) 0x429ce8 SBFM	X4, X3, #0, #31

(308) 0x429cec ADD	W3, W6, #3

(308) 0x429cf0 SBFM	X3, X3, #61, #31

(308) 0x429cf4 SBFM	X5, X5, #0, #31

(308) 0x429cf8 ADD	X6, X7, X3

(308) 0x429cfc MADD	X7, X13, X5, XZR

(308) 0x429d00 ADD	X25, X25, X3

(308) 0x429d04 ADD	X20, X20, X3

(308) 0x429d08 LD1	{V3.D[1]}, [X6]

(308) 0x429d0c MADD	X6, X13, X4, XZR

(308) 0x429d10 LD1	{V16.D[1]}, [X25]

(308) 0x429d14 LD1	{V5.D[1]}, [X20]

(308) 0x429d18 ADD	X7, X12, X7,LSL #3

(308) 0x429d1c ADD	X6, X12, X6,LSL #3

(308) 0x429d20 ORR	X12, XZR, X13

(308) 0x429d24 ORR	X13, XZR, X14

(308) 0x429d28 ORR	X14, XZR, X15

(308) 0x429d2c ORR	X15, XZR, X16

(308) 0x429d30 ORR	X16, XZR, X17

(308) 0x429d34 MADD	X25, X17, X22, XZR

(308) 0x429d38 ORR	X17, XZR, X18

(308) 0x429d3c ORR	X18, XZR, X0

(308) 0x429d40 ORR	X0, XZR, X1

(308) 0x429d44 ORR	X1, XZR, X28

(308) 0x429d48 MADD	X21, X14, X5, XZR

(308) 0x429d4c ADD	X20, X7, X10

(308) 0x429d50 ADD	X7, X7, X3

(308) 0x429d54 LDR	X28, [SP, #48]

(308) 0x429d58 LDR	D7, [X6, X24,SXTW #3]

(308) 0x429d5c LDR	D6, [X6, X2,SXTW #3]

(308) 0x429d60 MADD	X6, X14, X4, XZR

(308) 0x429d64 ADD	X25, X15, X25,LSL #3

(308) 0x429d68 ADD	X21, X13, X21,LSL #3

(308) 0x429d6c ADD	X6, X13, X6,LSL #3

(308) 0x429d70 FADD	V2.2D, V2.2D, V4.2D

(308) 0x429d74 LDR	D17, [X6, X24,SXTW #3]

(308) 0x429d78 LDR	D19, [X6, X2,SXTW #3]

(308) 0x429d7c MADD	X6, X16, X9, XZR

(308) 0x429d80 ADD	X6, X15, X6,LSL #3

(308) 0x429d84 LDR	D18, [X6, X24,SXTW #3]

(308) 0x429d88 ADD	X6, X25, X10

(308) 0x429d8c LD1	{V7.D[1]}, [X20]

(308) 0x429d90 ADD	X20, X21, X10

(308) 0x429d94 LD1	{V6.D[1]}, [X7]

(308) 0x429d98 MADD	X7, X1, X22, XZR

(308) 0x429d9c ADD	X7, X0, X7,LSL #3

(308) 0x429da0 LD1	{V17.D[1]}, [X20]

(308) 0x429da4 MADD	X20, X18, X22, XZR

(308) 0x429da8 ADD	X20, X17, X20,LSL #3

(308) 0x429dac ADD	X25, X20, X10

(308) 0x429db0 LD1	{V18.D[1]}, [X6]

(308) 0x429db4 MADD	X6, X18, X9, XZR

(308) 0x429db8 ADD	X20, X20, X3

(308) 0x429dbc ADD	X6, X17, X6,LSL #3

(308) 0x429dc0 LDR	D20, [X6, X24,SXTW #3]

(308) 0x429dc4 LDR	D21, [X6, X2,SXTW #3]

(308) 0x429dc8 MADD	X6, X1, X9, XZR

(308) 0x429dcc ADD	X6, X0, X6,LSL #3

(308) 0x429dd0 FADD	V4.2D, V7.2D, V17.2D

(308) 0x429dd4 LDR	D22, [X6, X24,SXTW #3]

(308) 0x429dd8 LDR	D23, [X6, X2,SXTW #3]

(308) 0x429ddc MADD	X6, X16, X4, XZR

(308) 0x429de0 FADD	V2.2D, V4.2D, V2.2D

(308) 0x429de4 FADD	V4.2D, V5.2D, V16.2D

(308) 0x429de8 ADD	X6, X15, X6,LSL #3

(308) 0x429dec LDR	D24, [X6, X24,SXTW #3]

(308) 0x429df0 MADD	X6, X18, X4, XZR

(308) 0x429df4 MADD	X4, X1, X4, XZR

(308) 0x429df8 FMUL	V2.2D, V2.2D, V1.2D

(308) 0x429dfc LD1	{V21.D[1]}, [X20]

(308) 0x429e00 ADD	X20, X7, X10

(308) 0x429e04 ADD	X7, X7, X3

(308) 0x429e08 LD1	{V20.D[1]}, [X25]

(308) 0x429e0c ORR	X25, XZR, X30

(308) 0x429e10 LDP	X26, X30, [X29, #968]

(308) 0x429e14 ADD	X6, X17, X6,LSL #3

(308) 0x429e18 ADD	X4, X0, X4,LSL #3

(308) 0x429e1c LDR	D26, [X6, X2,SXTW #3]

(308) 0x429e20 LDR	D25, [X6, X24,SXTW #3]

(308) 0x429e24 LDR	D27, [X4, X24,SXTW #3]

(308) 0x429e28 LD1	{V22.D[1]}, [X20]

(308) 0x429e2c ADD	X20, X21, X3

(308) 0x429e30 LD1	{V23.D[1]}, [X7]

(308) 0x429e34 MADD	X7, X16, X5, XZR

(308) 0x429e38 LD1	{V19.D[1]}, [X20]

(308) 0x429e3c ADD	X7, X15, X7,LSL #3

(308) 0x429e40 ADD	X7, X7, X10

(308) 0x429e44 LD1	{V24.D[1]}, [X7]

(308) 0x429e48 MADD	X7, X18, X5, XZR

(308) 0x429e4c MADD	X5, X1, X5, XZR

(308) 0x429e50 ADD	X7, X17, X7,LSL #3

(308) 0x429e54 ADD	X5, X0, X5,LSL #3

(308) 0x429e58 ADD	X20, X7, X10

(308) 0x429e5c ADD	X6, X7, X3

(308) 0x429e60 LDP	X7, X11, [SP, #120]

(308) 0x429e64 ADD	X3, X5, X3

(308) 0x429e68 LD1	{V26.D[1]}, [X6]

(308) 0x429e6c ADD	X6, X5, X10

(308) 0x429e70 LD1	{V25.D[1]}, [X20]

(308) 0x429e74 LDP	X21, X5, [SP, #88]

(308) 0x429e78 FADD	V5.2D, V6.2D, V19.2D

(308) 0x429e7c FADD	V6.2D, V22.2D, V23.2D

(308) 0x429e80 LD1	{V27.D[1]}, [X6]

(308) 0x429e84 LDP	X20, X6, [SP, #104]

(308) 0x429e88 FADD	V4.2D, V5.2D, V4.2D

(308) 0x429e8c FADD	V5.2D, V21.2D, V20.2D

(308) 0x429e90 LDR	D1, [X11]

(308) 0x429e94 FMUL	V3.2D, V4.2D, V3.2D

(308) 0x429e98 FADD	V4.2D, V5.2D, V6.2D

(308) 0x429e9c LDR	D6, [X4, X2,SXTW #3]

(308) 0x429ea0 MADD	X2, X6, X9, XZR

(308) 0x429ea4 MADD	X4, X30, X9, XZR

(308) 0x429ea8 ADD	X2, X7, X2,LSL #3

(308) 0x429eac FMLA	V2.2D, V4.2D, V18.2D

(308) 0x429eb0 ADD	X4, X26, X4,LSL #3

(308) 0x429eb4 FADD	V5.2D, V26.2D, V25.2D

(308) 0x429eb8 FMUL	D4, D1, D0

(308) 0x429ebc LDR	D1, [X2, X24,SXTW #3]

(308) 0x429ec0 MADD	X2, X5, X9, XZR

(308) 0x429ec4 ADD	X2, X20, X2,LSL #3

(308) 0x429ec8 LD1	{V6.D[1]}, [X3]

(308) 0x429ecc MADD	X3, X6, X22, XZR

(308) 0x429ed0 ADD	X3, X7, X3,LSL #3

(308) 0x429ed4 ADD	X3, X3, X10

(308) 0x429ed8 LD1	{V1.D[1]}, [X3]

(308) 0x429edc MADD	X3, X5, X22, XZR

(308) 0x429ee0 ADD	X3, X20, X3,LSL #3

(308) 0x429ee4 ADD	X3, X3, X10

(308) 0x429ee8 FADD	V6.2D, V27.2D, V6.2D

(308) 0x429eec FADD	V5.2D, V5.2D, V6.2D

(308) 0x429ef0 LDR	D6, [X4, X24,SXTW #3]

(308) 0x429ef4 MADD	X4, X30, X22, XZR

(308) 0x429ef8 LDUR	X30, [X29, #424]

(308) 0x429efc FMLA	V3.2D, V5.2D, V24.2D

(308) 0x429f00 ADD	X4, X26, X4,LSL #3

(308) 0x429f04 LDR	D5, [X2, X24,SXTW #3]

(308) 0x429f08 MADD	X2, X28, X9, XZR

(308) 0x429f0c LDUR	X26, [X29, #448]

(308) 0x429f10 ADD	X4, X4, X10

(308) 0x429f14 ADD	X2, X21, X2,LSL #3

(308) 0x429f18 FSUB	V2.2D, V3.2D, V2.2D

(308) 0x429f1c LDR	D3, [X2, X24,SXTW #3]

(308) 0x429f20 LD1	{V6.D[1]}, [X4]

(308) 0x429f24 MADD	X4, X30, X9, XZR

(308) 0x429f28 FMUL	V2.2D, V2.2D, V4.D[0]

(308) 0x429f2c LD1	{V5.D[1]}, [X3]

(308) 0x429f30 MADD	X3, X28, X22, XZR

(308) 0x429f34 ADD	X4, X26, X4,LSL #3

(308) 0x429f38 ADD	X3, X21, X3,LSL #3

(308) 0x429f3c ADD	X3, X3, X10

(308) 0x429f40 LD1	{V3.D[1]}, [X3]

(308) 0x429f44 FADD	V4.2D, V6.2D, V5.2D

(308) 0x429f48 FMUL	V4.2D, V4.2D, V2.2D

(308) 0x429f4c FADD	V2.2D, V2.2D, V1.2D

(308) 0x429f50 FMUL	V3.2D, V3.2D, V1.2D

(308) 0x429f54 FDIV	V3.2D, V4.2D, V3.2D

(308) 0x429f58 LDR	D4, [X4, X24,SXTW #3]

(308) 0x429f5c MADD	X4, X30, X22, XZR

(308) 0x429f60 ADD	X4, X26, X4,LSL #3

(308) 0x429f64 LDP	X30, X26, [X29, #944]

(308) 0x429f68 ADD	X4, X4, X10

(308) 0x429f6c LD1	{V4.D[1]}, [X4]

(308) 0x429f70 MADD	X4, X30, X9, XZR

(308) 0x429f74 ADD	X4, X26, X4,LSL #3

(308) 0x429f78 FSUB	V3.2D, V4.2D, V3.2D

(308) 0x429f7c STR	D3, [X4, X24,SXTW #3]

(308) 0x429f80 MADD	X4, X30, X22, XZR

(308) 0x429f84 ADD	X4, X26, X4,LSL #3

(308) 0x429f88 ADD	X4, X4, X10

(308) 0x429f8c ST1	{V3.D[1]}, [X4]

(308) 0x429f90 LDR	D3, [X2, X24,SXTW #3]

(308) 0x429f94 LDP	X2, X26, [SP, #72]

(308) 0x429f98 MADD	X9, X2, X9, XZR

(308) 0x429f9c ADD	X9, X26, X9,LSL #3

(308) 0x429fa0 LD1	{V3.D[1]}, [X3]

(308) 0x429fa4 FMUL	V1.2D, V3.2D, V1.2D

(308) 0x429fa8 FDIV	V1.2D, V1.2D, V2.2D

(308) 0x429fac STR	D1, [X9, X24,SXTW #3]

(308) 0x429fb0 MADD	X9, X2, X22, XZR

(308) 0x429fb4 LDUR	W22, [X29, #380]

(308) 0x429fb8 ADD	X9, X26, X9,LSL #3

(308) 0x429fbc ADD	X9, X9, X10

(308) 0x429fc0 ST1	{V1.D[1]}, [X9]

(308) 0x429fc4 LDUR	X9, [X29, #392]

(308) 0x429fc8 CMP	X9, X8

(308) 0x429fcc B.NE	429c00

0x429fd0 LDP	X8, X24, [SP, #16]

0x429fd4 LDP	X27, X9, [X29, #896]

0x429fd8 LDR	X30, [SP, #32]

0x429fdc CMP	X8, X9

0x429fe0 B.EQ	42a1c8

0x429fe4 LDUR	X19, [X29, #416]

0x429fe8 FMOV	D0, #0.2500000

0x429fec SUB	W8, WZR, W25

0x429ff0 STUR	W8, [X29, #400]

0x429ff4 HINT	#0

0x429ff8 HINT	#0

0x429ffc HINT	#0

(309) 0x42a000 SDIV	X9, X23, X25

(309) 0x42a004 ADD	W10, W24, W23

(309) 0x42a008 ORR	X8, XZR, X24

(309) 0x42a00c ORR	X24, XZR, X2

(309) 0x42a010 LDUR	W2, [X29, #400]

(309) 0x42a014 LDUR	X4, [X29, #408]

(309) 0x42a018 ADD	X23, X23, #1

(309) 0x42a01c ADD	W3, W22, W9

(309) 0x42a020 MADD	W2, W2, W9, W10

(309) 0x42a024 SBFM	X10, X3, #0, #31

(309) 0x42a028 ADD	W3, W3, #1

(309) 0x42a02c MADD	X4, X4, X10, XZR

(309) 0x42a030 ADD	W9, W2, #1

(309) 0x42a034 ADD	W2, W2, #2

(309) 0x42a038 SBFM	X3, X3, #0, #31

(309) 0x42a03c ADD	X4, X19, X4,LSL #3

(309) 0x42a040 LDR	D1, [X4, X9,SXTW #3]

(309) 0x42a044 LDR	D2, [X4, X2,SXTW #3]

(309) 0x42a048 MADD	X4, X12, X10, XZR

(309) 0x42a04c ADD	X4, X27, X4,LSL #3

(309) 0x42a050 LDR	D3, [X4, X9,SXTW #3]

(309) 0x42a054 LDR	D4, [X4, X2,SXTW #3]

(309) 0x42a058 MADD	X4, X14, X10, XZR

(309) 0x42a05c ADD	X4, X13, X4,LSL #3

(309) 0x42a060 LDR	D5, [X4, X9,SXTW #3]

(309) 0x42a064 LDR	D6, [X4, X2,SXTW #3]

(309) 0x42a068 MADD	X4, X12, X3, XZR

(309) 0x42a06c ADD	X4, X27, X4,LSL #3

(309) 0x42a070 LDR	D7, [X4, X9,SXTW #3]

(309) 0x42a074 LDR	D16, [X4, X2,SXTW #3]

(309) 0x42a078 MADD	X4, X14, X3, XZR

(309) 0x42a07c ADD	X4, X13, X4,LSL #3

(309) 0x42a080 LDR	D17, [X4, X9,SXTW #3]

(309) 0x42a084 LDR	D18, [X4, X2,SXTW #3]

(309) 0x42a088 MADD	X4, X16, X10, XZR

(309) 0x42a08c FADD	D3, D3, D5

(309) 0x42a090 FADD	D4, D4, D6

(309) 0x42a094 ADD	X4, X15, X4,LSL #3

(309) 0x42a098 LDR	D19, [X4, X9,SXTW #3]

(309) 0x42a09c MADD	X4, X18, X10, XZR

(309) 0x42a0a0 ADD	X4, X17, X4,LSL #3

(309) 0x42a0a4 LDR	D20, [X4, X9,SXTW #3]

(309) 0x42a0a8 LDR	D21, [X4, X2,SXTW #3]

(309) 0x42a0ac MADD	X4, X1, X10, XZR

(309) 0x42a0b0 FADD	D5, D7, D17

(309) 0x42a0b4 LDR	D7, [X11]

(309) 0x42a0b8 ADD	X4, X0, X4,LSL #3

(309) 0x42a0bc FADD	D3, D5, D3

(309) 0x42a0c0 FADD	D5, D16, D18

(309) 0x42a0c4 LDR	D22, [X4, X9,SXTW #3]

(309) 0x42a0c8 LDR	D23, [X4, X2,SXTW #3]

(309) 0x42a0cc MADD	X4, X16, X3, XZR

(309) 0x42a0d0 FADD	D4, D5, D4

(309) 0x42a0d4 FMUL	D1, D3, D1

(309) 0x42a0d8 ADD	X4, X15, X4,LSL #3

(309) 0x42a0dc LDR	D24, [X4, X9,SXTW #3]

(309) 0x42a0e0 MADD	X4, X18, X3, XZR

(309) 0x42a0e4 MADD	X3, X1, X3, XZR

(309) 0x42a0e8 FADD	D5, D21, D20

(309) 0x42a0ec FMUL	D2, D4, D2

(309) 0x42a0f0 ADD	X4, X17, X4,LSL #3

(309) 0x42a0f4 ADD	X3, X0, X3,LSL #3

(309) 0x42a0f8 FADD	D6, D22, D23

(309) 0x42a0fc LDR	D25, [X4, X9,SXTW #3]

(309) 0x42a100 LDR	D26, [X4, X2,SXTW #3]

(309) 0x42a104 LDR	D16, [X3, X2,SXTW #3]

(309) 0x42a108 MADD	X2, X6, X10, XZR

(309) 0x42a10c FADD	D4, D5, D6

(309) 0x42a110 LDR	D6, [X3, X9,SXTW #3]

(309) 0x42a114 LDP	X4, X3, [X29, #968]

(309) 0x42a118 ADD	X2, X7, X2,LSL #3

(309) 0x42a11c FMADD	D1, D4, D19, D1

(309) 0x42a120 FADD	D5, D26, D25

(309) 0x42a124 MADD	X3, X3, X10, XZR

(309) 0x42a128 FADD	D6, D6, D16

(309) 0x42a12c ADD	X3, X4, X3,LSL #3

(309) 0x42a130 LDUR	X4, [X29, #448]

(309) 0x42a134 FADD	D5, D5, D6

(309) 0x42a138 FMADD	D2, D5, D24, D2

(309) 0x42a13c LDR	D5, [X3, X9,SXTW #3]

(309) 0x42a140 LDUR	X3, [X29, #424]

(309) 0x42a144 FSUB	D1, D2, S1

(309) 0x42a148 FMUL	D2, D7, D0

(309) 0x42a14c MADD	X3, X3, X10, XZR

(309) 0x42a150 ADD	X3, X4, X3,LSL #3

(309) 0x42a154 FMUL	D1, D2, D1

(309) 0x42a158 LDR	D2, [X2, X9,SXTW #3]

(309) 0x42a15c MADD	X2, X5, X10, XZR

(309) 0x42a160 ADD	X2, X20, X2,LSL #3

(309) 0x42a164 LDR	D3, [X2, X9,SXTW #3]

(309) 0x42a168 MADD	X2, X28, X10, XZR

(309) 0x42a16c ADD	X2, X21, X2,LSL #3

(309) 0x42a170 LDR	D4, [X2, X9,SXTW #3]

(309) 0x42a174 FADD	D3, D5, D3

(309) 0x42a178 FMUL	D3, D3, D1

(309) 0x42a17c FADD	D1, D1, D2

(309) 0x42a180 FMUL	D4, D4, D2

(309) 0x42a184 FDIV	D3, D3, D4

(309) 0x42a188 LDR	D4, [X3, X9,SXTW #3]

(309) 0x42a18c LDP	X3, X4, [X29, #944]

(309) 0x42a190 MADD	X3, X3, X10, XZR

(309) 0x42a194 ADD	X3, X4, X3,LSL #3

(309) 0x42a198 FSUB	D3, D4, S3

(309) 0x42a19c STR	D3, [X3, X9,SXTW #3]

(309) 0x42a1a0 LDR	D3, [X2, X9,SXTW #3]

(309) 0x42a1a4 ORR	X2, XZR, X24

(309) 0x42a1a8 MADD	X10, X24, X10, XZR

(309) 0x42a1ac ORR	X24, XZR, X8

(309) 0x42a1b0 ADD	X10, X26, X10,LSL #3

(309) 0x42a1b4 FMUL	D2, D3, D2

(309) 0x42a1b8 FDIV	D1, D2, D1

(309) 0x42a1bc STR	D1, [X10, X9,SXTW #3]

(309) 0x42a1c0 CMP	X30, X23

(309) 0x42a1c4 B.NE	42a000

0x42a1c8 LDR	W1, [SP, #44]

0x42a1cc ADRP	X0,

0x42a1d0 ADD	X0, X0, #2464

0x42a1d4 BL	403400

0x42a1d8 LDP	X20, X19, [SP, #352]

0x42a1dc LDP	X22, X21, [SP, #336]

0x42a1e0 LDP	X24, X23, [SP, #320]

0x42a1e4 LDP	X26, X25, [SP, #304]

0x42a1e8 LDP	X28, X27, [SP, #288]

0x42a1ec LDP	X29, X30, [SP, #272]

0x42a1f0 ADD	SP, SP, #368

0x42a1f4 RET

0x42a1f8 HINT	#0

0x42a1fc HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 27.50 to 21.42 cycles (1.28x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.50 to 1.00 cycles (27.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 520 bytes. The binary function is storing 340 bytes.

General properties

nb instructions	138
loop length	552
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	7.25	7.25	7.17	7.17	7.08	7.08	0.50	0.50	0.50	0.50	27.50	27.17	27.33	14.50	14.50
cycles	4.00	4.00	7.25	7.25	7.17	7.17	7.08	7.08	0.50	0.50	0.50	0.50	27.50	27.17	27.33	14.50	14.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.63
Overall L1	27.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.50 cycles. At this rate:

19% of peak load performance is reached (18.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #368	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W10, W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 42a1d8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46daa0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMADDL X19, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X19, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STUR X9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 42a1c8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X2, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X5, X4, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X1, X6, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X16, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X14, X11, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X13, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X23, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X23, X8, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X19, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X13, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X27, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X19, X3, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X3, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X2, X4, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X3, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X23, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 429bb8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X23, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X26, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 429fe4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x5a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X23, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X23, X23, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W26, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X27, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR W22, [X29, #380]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X7, X11, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X23, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X23, X24, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W24, W10, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W26, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X20, X6, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X5, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X3, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X24, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X9, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42a1c8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X19, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W8, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <46d1cc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2464	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #368	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.50 to 1.00 cycles (27.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 520 bytes. The binary function is storing 340 bytes.

General properties

nb instructions	138
loop length	552
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	7.25	7.25	7.17	7.17	7.08	7.08	0.50	0.50	0.50	0.50	27.50	27.17	27.33	14.50	14.50
cycles	4.00	4.00	7.25	7.25	7.17	7.17	7.08	7.08	0.50	0.50	0.50	0.50	27.50	27.17	27.33	14.50	14.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.63
Overall L1	27.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.50 cycles. At this rate:

19% of peak load performance is reached (18.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #368	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W10, W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 42a1d8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46daa0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMADDL X19, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X19, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STUR X9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 42a1c8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X2, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X5, X4, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X1, X6, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X16, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X14, X11, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X13, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X23, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X23, X8, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X19, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X13, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X27, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X19, X3, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X3, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X2, X4, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X3, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X23, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 429bb8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X23, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X26, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 429fe4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x5a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X23, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X23, X23, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W26, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X27, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR W22, [X29, #380]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X7, X11, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X23, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X23, X24, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W24, W10, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W26, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X20, X6, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X5, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X3, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X24, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X9, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42a1c8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X19, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W8, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <46d1cc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2464	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #368	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	7.02	5.65
○Loop 308 - PdV.cpp:70-83 - exec	7.02	5.62
○Loop 309 - PdV.cpp:70-83 - exec	0.00	0.00

Report Configuration

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code