OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage (incl. loops): 5.38% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 48 - 63

--------------------------------------------------------------------------------

48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4293f0 SUB	SP, SP, #304

0x4293f4 STP	X29, X30, [SP, #208]

0x4293f8 STP	X28, X27, [SP, #224]

0x4293fc STP	X26, X25, [SP, #240]

0x429400 STP	X24, X23, [SP, #256]

0x429404 STP	X22, X21, [SP, #272]

0x429408 STP	X20, X19, [SP, #288]

0x42940c ADD	X29, SP, #208

0x429410 LDR	W8, [X2]

0x429414 LDR	W25, [X4]

0x429418 LDR	W10, [X5]

0x42941c ADD	W22, W8, #1

0x429420 LDR	W8, [X3]

0x429424 ADD	W9, W25, #1

0x429428 ADD	W10, W10, #2

0x42942c ADD	W8, W8, #2

0x429430 SUBS	W8, W8, W22

0x429434 CCMP	W10, W9, #4, #12

0x429438 B.LE	429a1c

0x42943c LDR	W1, [X0]

0x429440 SUB	W24, W10, W9

0x429444 MOVN	X9, #0

0x429448 ORR	X20, XZR, X7

0x42944c ORR	X21, XZR, X6

0x429450 ADRP	X0,

0x429454 ADD	X0, X0, #2368

0x429458 SUB	X3, X29, #36

0x42945c SUB	X4, X29, #16

0x429460 STUR	WZR, [X29, #476]

0x429464 STR	W1, [SP, #36]

0x429468 UMADDL	X19, W24, W8, X9

0x42946c MOVZ	W8, #1

0x429470 SUB	X5, X29, #24

0x429474 SUB	X6, X29, #32

0x429478 MOVZ	W2, #34

0x42947c MOVZ	W7, #1

0x429480 STP	X19, XZR, [X29, #1000]

0x429484 STUR	X8, [X29, #480]

0x429488 STR	X8, [SP]

0x42948c BL	4034d0

0x429490 LDP	X8, X9, [X29, #1000]

0x429494 CMP	X8, X19

0x429498 STUR	X9, [X29, #432]

0x42949c CSEL	X8, X8, X19, #11

0x4294a0 CMP	X9, X8

0x4294a4 B.GT	429a0c

0x4294a8 LDP	X10, X9, [X29, #160]

0x4294ac LDP	X5, X19, [X29, #144]

0x4294b0 LDP	X1, X3, [X29, #128]

0x4294b4 ADD	X26, X8, #1

0x4294b8 LDP	X16, X18, [X29, #112]

0x4294bc LDP	X0, X14, [X29, #96]

0x4294c0 LDUR	X8, [X29, #432]

0x4294c4 LDR	X2, [X21, #16]

0x4294c8 LDR	X6, [X21]

0x4294cc LDR	X23, [X20, #16]

0x4294d0 LDR	X12, [X20]

0x4294d4 LDR	X27, [X10, #16]

0x4294d8 LDR	X30, [X10]

0x4294dc LDR	X10, [X19, #16]

0x4294e0 LDR	X17, [X9, #16]

0x4294e4 LDR	X13, [X14, #16]

0x4294e8 LDR	X14, [X14]

0x4294ec LDR	X15, [X16, #16]

0x4294f0 LDR	X16, [X16]

0x4294f4 LDR	X4, [X18, #16]

0x4294f8 LDR	X7, [X18]

0x4294fc LDR	X11, [X1, #16]

0x429500 LDR	X1, [X1]

0x429504 LDR	X21, [X3, #16]

0x429508 LDR	X3, [X3]

0x42950c LDR	X20, [X5, #16]

0x429510 LDR	X5, [X5]

0x429514 STP	X17, X10, [X29, #968]

0x429518 LDR	X10, [X19]

0x42951c SUB	X17, X26, X8

0x429520 LDR	X8, [X9]

0x429524 STP	X10, X8, [X29, #952]

0x429528 CMP	X17, #2

0x42952c B.CS	429538

0x429530 LDUR	X28, [X29, #432]

0x429534 B	4298ac

0x429538 LDUR	X8, [X29, #432]

0x42953c AND	X9, X17, #8127

0x429540 FMOV	D0, #0.2500000

0x429544 ORR	X18, XZR, X25

0x429548 STP	X17, X26, [SP, #8]

0x42954c ORR	X25, XZR, XZR

0x429550 STR	X18, [SP, #24]

0x429554 ORR	X19, XZR, X12

0x429558 ADD	X28, X8, X9

0x42955c STP	X23, X9, [X29, #928]

0x429560 SUB	W9, WZR, W24

0x429564 ADD	W8, W18, W8

0x429568 STP	X30, X12, [SP, #96]

0x42956c STP	X4, X11, [SP, #80]

0x429570 STR	X24, [SP, #72]

0x429574 STP	X3, X20, [SP, #40]

0x429578 STR	W9, [SP, #68]

0x42957c STR	X8, [SP, #56]

(306) 0x429580 LDUR	X8, [X29, #432]

(306) 0x429584 LDR	X11, [SP, #56]

(306) 0x429588 ORR	W3, WZR, W22

(306) 0x42958c ORR	X4, XZR, X27

(306) 0x429590 ORR	X27, XZR, X1

(306) 0x429594 ORR	X20, XZR, X5

(306) 0x429598 ORR	X5, XZR, X0

(306) 0x42959c ORR	X12, XZR, X21

(306) 0x4295a0 ORR	X21, XZR, X7

(306) 0x4295a4 ORR	X7, XZR, X6

(306) 0x4295a8 ADD	X8, X8, X25

(306) 0x4295ac ADD	W23, W11, W25

(306) 0x4295b0 LDR	W11, [SP, #68]

(306) 0x4295b4 ADD	X25, X25, #2

(306) 0x4295b8 ADD	X9, X8, #1

(306) 0x4295bc SDIV	X8, X8, X24

(306) 0x4295c0 ADD	W10, W22, W8

(306) 0x4295c4 SDIV	X9, X9, X24

(306) 0x4295c8 SBFM	X26, X10, #0, #31

(306) 0x4295cc ADD	W22, W22, W9

(306) 0x4295d0 MADD	X1, X19, X26, XZR

(306) 0x4295d4 SBFM	X30, X22, #0, #31

(306) 0x4295d8 MADD	X18, X6, X30, XZR

(306) 0x4295dc ADD	X18, X2, X18,LSL #3

(306) 0x4295e0 MADD	W24, W11, W8, W23

(306) 0x4295e4 MADD	W17, W11, W9, W23

(306) 0x4295e8 ORR	X11, XZR, X16

(306) 0x4295ec ORR	X16, XZR, X15

(306) 0x4295f0 ORR	X15, XZR, X14

(306) 0x4295f4 ORR	X14, XZR, X13

(306) 0x4295f8 LDUR	X13, [X29, #416]

(306) 0x4295fc MADD	X9, X6, X26, XZR

(306) 0x429600 ADD	W23, W24, #1

(306) 0x429604 ADD	X0, X2, X9,LSL #3

(306) 0x429608 LDR	D1, [X0, X23,SXTW #3]

(306) 0x42960c ADD	X1, X13, X1,LSL #3

(306) 0x429610 ADD	W8, W17, #2

(306) 0x429614 ORR	X6, XZR, X2

(306) 0x429618 MADD	X2, X19, X30, XZR

(306) 0x42961c ADD	W24, W24, #2

(306) 0x429620 SBFM	X8, X8, #61, #31

(306) 0x429624 LDR	D3, [X0, X24,SXTW #3]

(306) 0x429628 LDR	D2, [X1, X23,SXTW #3]

(306) 0x42962c ADD	X9, X18, X8

(306) 0x429630 ADD	X2, X13, X2,LSL #3

(306) 0x429634 LDR	D4, [X1, X24,SXTW #3]

(306) 0x429638 LD1	{V1.D[1]}, [X9]

(306) 0x42963c ADD	X9, X2, X8

(306) 0x429640 LD1	{V2.D[1]}, [X9]

(306) 0x429644 ADD	W9, W10, #1

(306) 0x429648 ADD	W10, W22, #1

(306) 0x42964c SBFM	X22, X9, #0, #31

(306) 0x429650 SBFM	X9, X10, #0, #31

(306) 0x429654 ADD	W10, W17, #3

(306) 0x429658 MADD	X0, X19, X22, XZR

(306) 0x42965c SBFM	X10, X10, #61, #31

(306) 0x429660 ADD	X17, X18, X10

(306) 0x429664 ADD	X1, X2, X10

(306) 0x429668 ORR	X2, XZR, X6

(306) 0x42966c ORR	X6, XZR, X7

(306) 0x429670 ORR	X7, XZR, X21

(306) 0x429674 ORR	X21, XZR, X12

(306) 0x429678 LDUR	X12, [X29, #464]

(306) 0x42967c LD1	{V3.D[1]}, [X17]

(306) 0x429680 MADD	X17, X19, X9, XZR

(306) 0x429684 ADD	X18, X13, X0,LSL #3

(306) 0x429688 LD1	{V4.D[1]}, [X1]

(306) 0x42968c LDR	D5, [X18, X23,SXTW #3]

(306) 0x429690 LDR	D6, [X18, X24,SXTW #3]

(306) 0x429694 ADD	X17, X13, X17,LSL #3

(306) 0x429698 ORR	X13, XZR, X14

(306) 0x42969c ORR	X14, XZR, X15

(306) 0x4296a0 MADD	X18, X15, X26, XZR

(306) 0x4296a4 ORR	X15, XZR, X16

(306) 0x4296a8 ORR	X16, XZR, X11

(306) 0x4296ac ADD	X0, X17, X8

(306) 0x4296b0 ADD	X17, X17, X10

(306) 0x4296b4 ADD	X18, X13, X18,LSL #3

(306) 0x4296b8 LDR	D7, [X18, X23,SXTW #3]

(306) 0x4296bc MADD	X18, X11, X26, XZR

(306) 0x4296c0 ADD	X18, X15, X18,LSL #3

(306) 0x4296c4 LD1	{V5.D[1]}, [X0]

(306) 0x4296c8 MADD	X0, X14, X30, XZR

(306) 0x4296cc ADD	X0, X13, X0,LSL #3

(306) 0x4296d0 LDR	D17, [X18, X24,SXTW #3]

(306) 0x4296d4 LDR	D16, [X18, X23,SXTW #3]

(306) 0x4296d8 LD1	{V6.D[1]}, [X17]

(306) 0x4296dc MADD	X17, X14, X9, XZR

(306) 0x4296e0 ADD	X17, X13, X17,LSL #3

(306) 0x4296e4 MADD	X9, X11, X9, XZR

(306) 0x4296e8 ADD	X9, X15, X9,LSL #3

(306) 0x4296ec ADD	X0, X0, X8

(306) 0x4296f0 ADD	X17, X17, X8

(306) 0x4296f4 LD1	{V7.D[1]}, [X0]

(306) 0x4296f8 MADD	X0, X11, X30, XZR

(306) 0x4296fc ADD	X0, X15, X0,LSL #3

(306) 0x429700 ADD	X18, X0, X10

(306) 0x429704 ADD	X1, X0, X8

(306) 0x429708 ORR	X0, XZR, X5

(306) 0x42970c ORR	X5, XZR, X20

(306) 0x429710 LD1	{V17.D[1]}, [X18]

(306) 0x429714 MADD	X18, X14, X22, XZR

(306) 0x429718 LD1	{V16.D[1]}, [X1]

(306) 0x42971c FADD	V4.2D, V6.2D, V4.2D

(306) 0x429720 FADD	V2.2D, V5.2D, V2.2D

(306) 0x429724 ORR	X1, XZR, X27

(306) 0x429728 ORR	X27, XZR, X4

(306) 0x42972c ADD	X18, X13, X18,LSL #3

(306) 0x429730 FMUL	V3.2D, V4.2D, V3.2D

(306) 0x429734 FADD	V4.2D, V17.2D, V16.2D

(306) 0x429738 LDR	D18, [X18, X23,SXTW #3]

(306) 0x42973c ADD	X18, X9, X8

(306) 0x429740 ADD	X9, X9, X10

(306) 0x429744 MADD	X10, X7, X30, XZR

(306) 0x429748 LD1	{V18.D[1]}, [X17]

(306) 0x42974c MADD	X17, X11, X22, XZR

(306) 0x429750 FMUL	V4.2D, V4.2D, V7.2D

(306) 0x429754 LDR	X11, [SP, #88]

(306) 0x429758 ORR	W22, WZR, W3

(306) 0x42975c LDP	X3, X20, [SP, #40]

(306) 0x429760 FMLA	V4.2D, V2.2D, V1.2D

(306) 0x429764 LDR	D1, [X0]

(306) 0x429768 ADD	X17, X15, X17,LSL #3

(306) 0x42976c LDR	D5, [X17, X24,SXTW #3]

(306) 0x429770 LDR	D19, [X17, X23,SXTW #3]

(306) 0x429774 LDP	X24, X4, [SP, #72]

(306) 0x429778 MADD	X17, X5, X26, XZR

(306) 0x42977c FSUB	V3.2D, V3.2D, V4.2D

(306) 0x429780 ADD	X17, X20, X17,LSL #3

(306) 0x429784 LDR	D6, [X17, X23,SXTW #3]

(306) 0x429788 MADD	X17, X5, X30, XZR

(306) 0x42978c FMUL	D2, D1, D0

(306) 0x429790 ADD	X10, X4, X10,LSL #3

(306) 0x429794 ADD	X10, X10, X8

(306) 0x429798 ADD	X17, X20, X17,LSL #3

(306) 0x42979c ADD	X17, X17, X8

(306) 0x4297a0 LD1	{V5.D[1]}, [X9]

(306) 0x4297a4 MADD	X9, X7, X26, XZR

(306) 0x4297a8 LD1	{V19.D[1]}, [X18]

(306) 0x4297ac LDR	X18, [SP, #96]

(306) 0x4297b0 ADD	X9, X4, X9,LSL #3

(306) 0x4297b4 LDR	D1, [X9, X23,SXTW #3]

(306) 0x4297b8 MADD	X9, X1, X26, XZR

(306) 0x4297bc LD1	{V6.D[1]}, [X17]

(306) 0x4297c0 MADD	X17, X18, X26, XZR

(306) 0x4297c4 ADD	X9, X11, X9,LSL #3

(306) 0x4297c8 ADD	X17, X27, X17,LSL #3

(306) 0x4297cc LDR	D4, [X9, X23,SXTW #3]

(306) 0x4297d0 MADD	X9, X3, X26, XZR

(306) 0x4297d4 FADD	V5.2D, V5.2D, V19.2D

(306) 0x4297d8 ADD	X9, X21, X9,LSL #3

(306) 0x4297dc LD1	{V1.D[1]}, [X10]

(306) 0x4297e0 MADD	X10, X1, X30, XZR

(306) 0x4297e4 FMLA	V3.2D, V5.2D, V18.2D

(306) 0x4297e8 LDR	D5, [X9, X23,SXTW #3]

(306) 0x4297ec ADD	X10, X11, X10,LSL #3

(306) 0x4297f0 ADD	X10, X10, X8

(306) 0x4297f4 LD1	{V4.D[1]}, [X10]

(306) 0x4297f8 MADD	X10, X3, X30, XZR

(306) 0x4297fc FMUL	V2.2D, V3.2D, V2.D[0]

(306) 0x429800 ADD	X10, X21, X10,LSL #3

(306) 0x429804 ADD	X10, X10, X8

(306) 0x429808 LD1	{V5.D[1]}, [X10]

(306) 0x42980c FADD	V3.2D, V6.2D, V4.2D

(306) 0x429810 FMUL	V3.2D, V3.2D, V2.2D

(306) 0x429814 FADD	V2.2D, V2.2D, V1.2D

(306) 0x429818 FMUL	V4.2D, V5.2D, V1.2D

(306) 0x42981c FDIV	V3.2D, V3.2D, V4.2D

(306) 0x429820 LDR	D4, [X17, X23,SXTW #3]

(306) 0x429824 MADD	X17, X18, X30, XZR

(306) 0x429828 LDUR	X18, [X29, #440]

(306) 0x42982c ADD	X17, X27, X17,LSL #3

(306) 0x429830 ADD	X17, X17, X8

(306) 0x429834 LD1	{V4.D[1]}, [X17]

(306) 0x429838 MADD	X17, X18, X26, XZR

(306) 0x42983c ADD	X17, X12, X17,LSL #3

(306) 0x429840 FSUB	V3.2D, V4.2D, V3.2D

(306) 0x429844 STR	D3, [X17, X23,SXTW #3]

(306) 0x429848 MADD	X17, X18, X30, XZR

(306) 0x42984c ADD	X17, X12, X17,LSL #3

(306) 0x429850 ADD	X17, X17, X8

(306) 0x429854 ST1	{V3.D[1]}, [X17]

(306) 0x429858 LDP	X17, X12, [X29, #960]

(306) 0x42985c LDR	D3, [X9, X23,SXTW #3]

(306) 0x429860 MADD	X9, X17, X26, XZR

(306) 0x429864 ADD	X9, X12, X9,LSL #3

(306) 0x429868 LD1	{V3.D[1]}, [X10]

(306) 0x42986c FMUL	V1.2D, V3.2D, V1.2D

(306) 0x429870 FDIV	V1.2D, V1.2D, V2.2D

(306) 0x429874 STR	D1, [X9, X23,SXTW #3]

(306) 0x429878 MADD	X9, X17, X30, XZR

(306) 0x42987c ADD	X9, X12, X9,LSL #3

(306) 0x429880 ADD	X8, X9, X8

(306) 0x429884 ST1	{V1.D[1]}, [X8]

(306) 0x429888 LDUR	X8, [X29, #424]

(306) 0x42988c CMP	X8, X25

(306) 0x429890 B.NE	429580

0x429894 LDP	X8, X26, [SP, #8]

0x429898 LDP	X23, X9, [X29, #928]

0x42989c LDR	X25, [SP, #24]

0x4298a0 LDP	X30, X12, [SP, #96]

0x4298a4 CMP	X8, X9

0x4298a8 B.EQ	429a0c

0x4298ac FMOV	D0, #0.2500000

0x4298b0 SUB	W8, WZR, W24

0x4298b4 HINT	#0

0x4298b8 HINT	#0

0x4298bc HINT	#0

(307) 0x4298c0 SDIV	X9, X28, X24

(307) 0x4298c4 ADD	W17, W25, W28

(307) 0x4298c8 ADD	X28, X28, #1

(307) 0x4298cc ADD	W10, W22, W9

(307) 0x4298d0 MADD	W17, W8, W9, W17

(307) 0x4298d4 SBFM	X9, X10, #0, #31

(307) 0x4298d8 ADD	W10, W10, #1

(307) 0x4298dc MADD	X18, X6, X9, XZR

(307) 0x4298e0 ADD	W19, W17, #1

(307) 0x4298e4 ADD	W17, W17, #2

(307) 0x4298e8 SBFM	X10, X10, #0, #31

(307) 0x4298ec ADD	X18, X2, X18,LSL #3

(307) 0x4298f0 LDR	D1, [X18, X19,SXTW #3]

(307) 0x4298f4 LDR	D2, [X18, X17,SXTW #3]

(307) 0x4298f8 MADD	X18, X12, X9, XZR

(307) 0x4298fc ADD	X18, X23, X18,LSL #3

(307) 0x429900 LDR	D3, [X18, X19,SXTW #3]

(307) 0x429904 LDR	D4, [X18, X17,SXTW #3]

(307) 0x429908 MADD	X18, X12, X10, XZR

(307) 0x42990c ADD	X18, X23, X18,LSL #3

(307) 0x429910 LDR	D5, [X18, X19,SXTW #3]

(307) 0x429914 LDR	D6, [X18, X17,SXTW #3]

(307) 0x429918 MADD	X18, X14, X9, XZR

(307) 0x42991c ADD	X18, X13, X18,LSL #3

(307) 0x429920 LDR	D7, [X18, X19,SXTW #3]

(307) 0x429924 MADD	X18, X16, X9, XZR

(307) 0x429928 ADD	X18, X15, X18,LSL #3

(307) 0x42992c LDR	D16, [X18, X19,SXTW #3]

(307) 0x429930 LDR	D17, [X18, X17,SXTW #3]

(307) 0x429934 MADD	X18, X14, X10, XZR

(307) 0x429938 MADD	X10, X16, X10, XZR

(307) 0x42993c FADD	D4, D6, D4

(307) 0x429940 FADD	D3, D5, D3

(307) 0x429944 LDR	D5, [X0]

(307) 0x429948 ADD	X10, X15, X10,LSL #3

(307) 0x42994c ADD	X18, X13, X18,LSL #3

(307) 0x429950 LDR	D18, [X18, X19,SXTW #3]

(307) 0x429954 LDUR	X18, [X29, #464]

(307) 0x429958 FADD	D6, D17, D16

(307) 0x42995c LDR	D16, [X10, X19,SXTW #3]

(307) 0x429960 LDR	D17, [X10, X17,SXTW #3]

(307) 0x429964 MADD	X10, X7, X9, XZR

(307) 0x429968 MADD	X17, X5, X9, XZR

(307) 0x42996c FMUL	D6, D6, D7

(307) 0x429970 ADD	X10, X4, X10,LSL #3

(307) 0x429974 ADD	X17, X20, X17,LSL #3

(307) 0x429978 FMADD	D1, D3, D1, D6

(307) 0x42997c FNMSUB	D1, D4, D2, D1

(307) 0x429980 FMUL	D2, D5, D0

(307) 0x429984 LDR	D5, [X17, X19,SXTW #3]

(307) 0x429988 MADD	X17, X30, X9, XZR

(307) 0x42998c FADD	D16, D17, D16

(307) 0x429990 ADD	X17, X27, X17,LSL #3

(307) 0x429994 FMADD	D1, D16, D18, D1

(307) 0x429998 FMUL	D1, D2, D1

(307) 0x42999c LDR	D2, [X10, X19,SXTW #3]

(307) 0x4299a0 MADD	X10, X1, X9, XZR

(307) 0x4299a4 ADD	X10, X11, X10,LSL #3

(307) 0x4299a8 LDR	D3, [X10, X19,SXTW #3]

(307) 0x4299ac MADD	X10, X3, X9, XZR

(307) 0x4299b0 ADD	X10, X21, X10,LSL #3

(307) 0x4299b4 LDR	D4, [X10, X19,SXTW #3]

(307) 0x4299b8 FADD	D3, D5, D3

(307) 0x4299bc FMUL	D3, D3, D1

(307) 0x4299c0 FADD	D1, D1, D2

(307) 0x4299c4 FMUL	D4, D4, D2

(307) 0x4299c8 FDIV	D3, D3, D4

(307) 0x4299cc LDR	D4, [X17, X19,SXTW #3]

(307) 0x4299d0 LDUR	X17, [X29, #440]

(307) 0x4299d4 MADD	X17, X17, X9, XZR

(307) 0x4299d8 ADD	X17, X18, X17,LSL #3

(307) 0x4299dc FSUB	D3, D4, S3

(307) 0x4299e0 STR	D3, [X17, X19,SXTW #3]

(307) 0x4299e4 LDR	D3, [X10, X19,SXTW #3]

(307) 0x4299e8 LDUR	X10, [X29, #448]

(307) 0x4299ec MADD	X9, X10, X9, XZR

(307) 0x4299f0 LDUR	X10, [X29, #456]

(307) 0x4299f4 FMUL	D2, D3, D2

(307) 0x4299f8 ADD	X9, X10, X9,LSL #3

(307) 0x4299fc FDIV	D1, D2, D1

(307) 0x429a00 STR	D1, [X9, X19,SXTW #3]

(307) 0x429a04 CMP	X26, X28

(307) 0x429a08 B.NE	4298c0

0x429a0c LDR	W1, [SP, #36]

0x429a10 ADRP	X0,

0x429a14 ADD	X0, X0, #2392

0x429a18 BL	403400

0x429a1c LDP	X20, X19, [SP, #288]

0x429a20 LDP	X22, X21, [SP, #272]

0x429a24 LDP	X24, X23, [SP, #256]

0x429a28 LDP	X26, X25, [SP, #240]

0x429a2c LDP	X28, X27, [SP, #224]

0x429a30 LDP	X29, X30, [SP, #208]

0x429a34 ADD	SP, SP, #304

0x429a38 RET

0x429a3c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 23.50 to 18.37 cycles (1.28x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.50 to 1.00 cycles (23.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 472 bytes. The binary function is storing 284 bytes.

General properties

nb instructions	124
loop length	496
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	7.08	7.08	7.00	7.00	6.92	6.92	0.50	0.50	0.50	0.50	23.50	23.17	23.33	11.50	11.50
cycles	4.00	4.00	7.08	7.08	7.00	7.00	6.92	6.92	0.50	0.50	0.50	0.50	23.50	23.17	23.33	11.50	11.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.00
Overall L1	23.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

20% of peak load performance is reached (20.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4293f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W25, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W10, W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 429a1c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W24, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46d450>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2368	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMADDL X19, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X19, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 429a0c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X5, X19, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X1, X3, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X26, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X16, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X0, X14, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X23, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X27, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X17, X10, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X17, X26, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X10, X8, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X17, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 429538 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X28, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4298ac <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X9, X17, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X18, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X17, X26, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X25, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X18, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W9, WZR, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W18, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X30, X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X24, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X20, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR W9, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X25, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X30, X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 429a0c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W8, WZR, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <46da10>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2392	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.50 to 1.00 cycles (23.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 472 bytes. The binary function is storing 284 bytes.

General properties

nb instructions	124
loop length	496
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	7.08	7.08	7.00	7.00	6.92	6.92	0.50	0.50	0.50	0.50	23.50	23.17	23.33	11.50	11.50
cycles	4.00	4.00	7.08	7.08	7.00	7.00	6.92	6.92	0.50	0.50	0.50	0.50	23.50	23.17	23.33	11.50	11.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.00
Overall L1	23.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

20% of peak load performance is reached (20.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4293f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W25, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W10, W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 429a1c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W24, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46d450>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2368	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMADDL X19, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X19, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 429a0c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X5, X19, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X1, X3, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X26, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X16, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X0, X14, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X23, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X27, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X17, X10, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X17, X26, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X10, X8, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X17, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 429538 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X28, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4298ac <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X9, X17, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X18, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X17, X26, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X25, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X18, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W9, WZR, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W18, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X30, X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X24, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X20, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR W9, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X25, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X30, X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 429a0c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W8, WZR, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <46da10>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2392	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.38	4.33
○Loop 306 - PdV.cpp:49-63 - exec	5.38	4.30
○Loop 307 - PdV.cpp:49-63 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code