OV - exec - Function generate_chunk(int, global_variables&) [clone .omp

	Function: generate_chunk(int, global_variables&) [clone .omp_outlined.2]	Module: exec	Source: generate_chunk.cpp:85-123 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 85 - 123

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

[...]

105:               std::sqrt((field.cellx[i] - x_cent) * (field.cellx[i] - x_cent) + (field.celly[j] - y_cent) * (field.celly[j] - y_cent));

106:           if (radius <= state_radius[state]) {

107:             field.energy0(i, j) = state_energy[state];

108:             field.density0(i, j) = state_density[state];

109:             for (int kt = j; kt <= j + 1; ++kt) {

110:               for (int jt = i; jt <= i + 1; ++jt) {

111:                 field.xvel0(jt, kt) = state_xvel[state];

112:                 field.yvel0(jt, kt) = state_yvel[state];

113:               }

114:             }

115:           }

116:         } else if (state_geometry[state] == g_point) {

117:           if (field.vertexx[i] == x_cent && field.vertexy[j] == y_cent) {

118:             field.energy0(i, j) = state_energy[state];

119:             field.density0(i, j) = state_density[state];

120:             for (int kt = j; kt <= j + 1; ++kt) {

121:               for (int jt = i; jt <= i + 1; ++jt) {

122:                 field.xvel0(jt, kt) = state_xvel[state];

123:                 field.yvel0(jt, kt) = state_yvel[state];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x424180 LDR	W8, [X2]

0x424184 LDR	W9, [X3]

0x424188 CMP	W8, #1

0x42418c CCMP	W9, #1, #8, #10

0x424190 B.LT	424250

0x424194 SUB	SP, SP, #256

0x424198 STP	X29, X30, [SP, #160]

0x42419c STP	X28, X27, [SP, #176]

0x4241a0 STP	X26, X25, [SP, #192]

0x4241a4 STP	X24, X23, [SP, #208]

0x4241a8 STP	X22, X21, [SP, #224]

0x4241ac STP	X20, X19, [SP, #240]

0x4241b0 ADD	X29, SP, #160

0x4241b4 LDR	W25, [X0]

0x4241b8 SBFM	X24, X9, #0, #31

0x4241bc MOVN	X9, #0

0x4241c0 ORR	X20, XZR, X7

0x4241c4 ORR	X21, XZR, X6

0x4241c8 ORR	X23, XZR, X5

0x4241cc ORR	X22, XZR, X4

0x4241d0 ADRP	X0,

0x4241d4 ADD	X0, X0, #1272

0x4241d8 SUB	X3, X29, #36

0x4241dc SUB	X4, X29, #16

0x4241e0 STUR	WZR, [X29, #476]

0x4241e4 ORR	W1, WZR, W25

0x4241e8 MADD	X19, X24, X8, X9

0x4241ec MOVZ	W8, #1

0x4241f0 SUB	X5, X29, #24

0x4241f4 SUB	X6, X29, #32

0x4241f8 MOVZ	W2, #34

0x4241fc MOVZ	W7, #1

0x424200 STP	X19, XZR, [X29, #1000]

0x424204 STUR	X8, [X29, #480]

0x424208 STR	X8, [SP]

0x42420c BL	4034d0

0x424210 LDP	X8, X4, [X29, #1000]

0x424214 CMP	X8, X19

0x424218 CSEL	X11, X8, X19, #11

0x42421c CMP	X4, X11

0x424220 B.LE	424254

  (247) 0x424224 ADRP	X0,

  (247) 0x424228 ADD	X0, X0, #1296

  (247) 0x42422c ORR	W1, WZR, W25

  (247) 0x424230 BL	403400

  (247) 0x424234 LDP	X20, X19, [SP, #240]

  (247) 0x424238 LDP	X22, X21, [SP, #224]

  (247) 0x42423c LDP	X24, X23, [SP, #208]

  (247) 0x424240 LDP	X26, X25, [SP, #192]

  (247) 0x424244 LDP	X28, X27, [SP, #176]

  (247) 0x424248 LDP	X29, X30, [SP, #160]

  (247) 0x42424c ADD	SP, SP, #256

  (247) 0x424250 RET

  (247) 0x424254 LDP	X15, X14, [X29, #120]

  (247) 0x424258 LDR	X9, [X29, #96]

  (247) 0x42425c LDR	X10, [X21, #8]

  (247) 0x424260 LDP	X13, X12, [X29, #136]

  (247) 0x424264 LDRSW	X8, [X23]

  (247) 0x424268 LDR	X22, [X22, #8]

  (247) 0x42426c LDR	X15, [X15, #8]

  (247) 0x424270 STP	X15, X10, [X29, #968]

  (247) 0x424274 LDR	X10, [X20, #8]

  (247) 0x424278 LDR	X5, [X9, #600]

  (247) 0x42427c LDR	X6, [X9, #632]

  (247) 0x424280 LDR	X17, [X13, #8]

  (247) 0x424284 LDR	X18, [X9, #184]

  (247) 0x424288 LDR	X0, [X9, #168]

  (247) 0x42428c LDR	X1, [X12, #8]

  (247) 0x424290 LDR	X2, [X9, #232]

  (247) 0x424294 LDR	X3, [X9, #216]

  (247) 0x424298 LDR	X12, [X9, #64]

  (247) 0x42429c LDR	W10, [X10, X8,LSL #2]

  (247) 0x4242a0 LDR	X15, [X9, #48]

  (247) 0x4242a4 STP	X15, X12, [X29, #952]

  (247) 0x4242a8 LDR	X15, [X14, #8]

  (247) 0x4242ac LDR	X14, [X9, #16]

  (247) 0x4242b0 STP	X14, X15, [SP, #72]

  (247) 0x4242b4 LDR	X14, [X9]

  (247) 0x4242b8 STR	X14, [SP, #64]

  (247) 0x4242bc CMP	W10, #1

  (247) 0x4242c0 B.EQ	424624

  (247) 0x4242c4 CMP	W10, #2

  (247) 0x4242c8 B.EQ	4245fc

  (247) 0x4242cc CMP	W10, #3

  (247) 0x4242d0 B.NE	424224

  (247) 0x4242d4 ADD	X7, X11, #1

  (247) 0x4242d8 SUB	X9, X7, X4

  (247) 0x4242dc CMP	X9, #1

  (247) 0x4242e0 B.LS	424fb4

  (247) 0x4242e4 STP	X9, X22, [SP, #48]

  (247) 0x4242e8 AND	X9, X9, #8127

  (247) 0x4242ec DUP	V0.2S, W24

  (247) 0x4242f0 SUB	X26, XZR, X24,LSL #32

  (247) 0x4242f4 STR	W25, [SP, #36]

  (247) 0x4242f8 SUB	X25, XZR, X24

  (247) 0x4242fc UBFM	X27, X4, #32, #31

  (247) 0x424300 ORR	X22, XZR, XZR

  (247) 0x424304 ORR	X16, XZR, X9

  (247) 0x424308 ADD	X9, X4, X9

  (247) 0x42430c STR	X9, [SP, #40]

  (247) 0x424310 MOVZ	W9, #1

  (247) 0x424314 DUP	V1.2D, X9

  (247) 0x424318 B	424334

0x42431c HINT	#0

    (252) 0x424320 MOVZ	X9, #2

    (252) 0x424324 ADD	X22, X22, #2

    (252) 0x424328 ADD	X27, X27, X9

    (252) 0x42432c CMP	X16, X22

    (252) 0x424330 B.EQ	424fa0

    (252) 0x424334 ADD	X19, X4, X22

    (252) 0x424338 LDR	X9, [SP, #56]

    (252) 0x42433c MOVZ	X10, #1

    (252) 0x424340 ADD	X23, X19, #1

    (252) 0x424344 SDIV	X20, X19, X24

    (252) 0x424348 ADD	X9, X9, X8,LSL #3

    (252) 0x42434c LD1R	{V2.2D}, [X9]

    (252) 0x424350 MADD	X12, X26, X20, X27

    (252) 0x424354 SDIV	X28, X23, X24

    (252) 0x424358 MADD	X9, X26, X28, X27

    (252) 0x42435c ADD	X11, X9, X10

    (252) 0x424360 SBFM	X9, X12, #29, #63

    (252) 0x424364 LDR	D3, [X5, X9]

    (252) 0x424368 ADD	X10, X5, X11,ASR #29

    (252) 0x42436c LD1	{V3.D[1]}, [X10]

    (252) 0x424370 FCMEQ	V2.2D, V3.2D, V2.2D

    (252) 0x424374 XTN	V4.2S, V2.2D

    (252) 0x424378 FMOV	W9, S4

    (252) 0x42437c TBZ	W9, #0, 424400

    (252) 0x424380 LDUR	X9, [X29, #464]

    (252) 0x424384 LDR	D3, [X9, X8,LSL #3]

    (252) 0x424388 MOV	W9, V4.S[1]

    (252) 0x42438c TBNZ	W9, #0, 424408

    (252) 0x424390 FMOV	W9, S4

    (252) 0x424394 SBFM	X21, X20, #0, #31

    (252) 0x424398 TBZ	W9, #0, 424420

    (252) 0x42439c LDR	D5, [X6, X21,LSL #3]

    (252) 0x4243a0 MOV	W9, V4.S[1]

    (252) 0x4243a4 SBFM	X30, X28, #0, #31

    (252) 0x4243a8 TBNZ	W9, #0, 42442c

    (252) 0x4243ac FCMEQ	V3.2D, V5.2D, V3.2D

    (252) 0x4243b0 AND	V2.16B, V2.16B, V3.16B

    (252) 0x4243b4 XTN	V2.2S, V2.2D

    (252) 0x4243b8 FMOV	W9, S2

    (252) 0x4243bc TBZ	W9, #0, 424448

    (252) 0x4243c0 SBFM	X9, X12, #32, #63

    (252) 0x4243c4 LDP	X12, X10, [X29, #960]

    (252) 0x4243c8 LDR	D3, [X10, X8,LSL #3]

    (252) 0x4243cc LDUR	X10, [X29, #440]

    (252) 0x4243d0 MADD	X10, X10, X21, XZR

    (252) 0x4243d4 ADD	X10, X12, X10,LSL #3

    (252) 0x4243d8 STR	D3, [X10, X9,LSL #3]

    (252) 0x4243dc LDP	X12, X10, [SP, #72]

    (252) 0x4243e0 LDR	D3, [X10, X8,LSL #3]

    (252) 0x4243e4 LDR	X10, [SP, #64]

    (252) 0x4243e8 MADD	X10, X10, X21, XZR

    (252) 0x4243ec ADD	X10, X12, X10,LSL #3

    (252) 0x4243f0 STR	D3, [X10, X9,LSL #3]

    (252) 0x4243f4 MOV	W9, V2.S[1]

    (252) 0x4243f8 TBNZ	W9, #0, 424450

    (252) 0x4243fc B	424484

    (252) 0x424400 MOV	W9, V4.S[1]

    (252) 0x424404 TBZ	W9, #0, 424390

    (252) 0x424408 LDUR	X9, [X29, #464]

    (252) 0x42440c ADD	X9, X9, X8,LSL #3

    (252) 0x424410 LD1	{V3.D[1]}, [X9]

    (252) 0x424414 FMOV	W9, S4

    (252) 0x424418 SBFM	X21, X20, #0, #31

    (252) 0x42441c TBNZ	W9, #0, 42439c

    (252) 0x424420 MOV	W9, V4.S[1]

    (252) 0x424424 SBFM	X30, X28, #0, #31

    (252) 0x424428 TBZ	W9, #0, 4243ac

    (252) 0x42442c ADD	X9, X6, X30,LSL #3

    (252) 0x424430 LD1	{V5.D[1]}, [X9]

    (252) 0x424434 FCMEQ	V3.2D, V5.2D, V3.2D

    (252) 0x424438 AND	V2.16B, V2.16B, V3.16B

    (252) 0x42443c XTN	V2.2S, V2.2D

    (252) 0x424440 FMOV	W9, S2

    (252) 0x424444 TBNZ	W9, #0, 4243c0

    (252) 0x424448 MOV	W9, V2.S[1]

    (252) 0x42444c TBZ	W9, #0, 424484

    (252) 0x424450 SBFM	X9, X11, #32, #63

    (252) 0x424454 LDP	X11, X10, [X29, #960]

    (252) 0x424458 LDR	D3, [X10, X8,LSL #3]

    (252) 0x42445c LDUR	X10, [X29, #440]

    (252) 0x424460 MADD	X10, X10, X30, XZR

    (252) 0x424464 ADD	X10, X11, X10,LSL #3

    (252) 0x424468 STR	D3, [X10, X9,LSL #3]

    (252) 0x42446c LDP	X11, X10, [SP, #72]

    (252) 0x424470 LDR	D3, [X10, X8,LSL #3]

    (252) 0x424474 LDR	X10, [SP, #64]

    (252) 0x424478 MADD	X10, X10, X30, XZR

    (252) 0x42447c ADD	X10, X11, X10,LSL #3

    (252) 0x424480 STR	D3, [X10, X9,LSL #3]

    (252) 0x424484 FMOV	S3, W21

    (252) 0x424488 MADD	X9, X0, X21, XZR

    (252) 0x42448c ADD	X12, X18, X9,LSL #3

    (252) 0x424490 FMOV	S4, W19

    (252) 0x424494 MADD	X9, X3, X21, XZR

    (252) 0x424498 MOV	V3.S[1], W28

    (252) 0x42449c MOV	V4.S[1], W23

    (252) 0x4244a0 ADD	X13, X2, X9,LSL #3

    (252) 0x4244a4 FMOV	W9, S2

    (252) 0x4244a8 MLS	V4.2S, V0.2S, V3.2S

    (252) 0x4244ac SSHLL	V3.2D, V4.2S, #32

    (252) 0x4244b0 TBZ	W9, #0, 4244c8

    (252) 0x4244b4 LDR	D4, [X17, X8,LSL #3]

    (252) 0x4244b8 FMOV	X9, D3

    (252) 0x4244bc STR	D4, [X12, X9,LSL #3]

    (252) 0x4244c0 LDR	D4, [X1, X8,LSL #3]

    (252) 0x4244c4 STR	D4, [X13, X9,LSL #3]

    (252) 0x4244c8 MADD	X9, X0, X30, XZR

    (252) 0x4244cc MADD	X10, X3, X30, XZR

    (252) 0x4244d0 MOV	W14, V2.S[1]

    (252) 0x4244d4 MOV	X11, V3.D[1]

    (252) 0x4244d8 ADD	X9, X18, X9,LSL #3

    (252) 0x4244dc ADD	X10, X2, X10,LSL #3

    (252) 0x4244e0 TBZ	W14, #0, 4244f4

    (252) 0x4244e4 LDR	D4, [X17, X8,LSL #3]

    (252) 0x4244e8 STR	D4, [X9, X11,LSL #3]

    (252) 0x4244ec LDR	D4, [X1, X8,LSL #3]

    (252) 0x4244f0 STR	D4, [X10, X11,LSL #3]

    (252) 0x4244f4 MADD	X14, X25, X20, X19

    (252) 0x4244f8 ADD	V5.2D, V3.2D, V1.2D

    (252) 0x4244fc MADD	X15, X25, X28, X23

    (252) 0x424500 FMOV	D4, X14

    (252) 0x424504 MOV	V4.D[1], X15

    (252) 0x424508 SHL	V4.2D, V4.2D, #32

    (252) 0x42450c SSHR	V4.2D, V4.2D, #32

    (252) 0x424510 CMGE	V4.2D, V4.2D, V3.2D

    (252) 0x424514 XTN	V4.2S, V4.2D

    (252) 0x424518 AND	V4.8B, V2.8B, V4.8B

    (252) 0x42451c FMOV	W14, S4

    (252) 0x424520 TBZ	W14, #0, 424538

    (252) 0x424524 LDR	D6, [X17, X8,LSL #3]

    (252) 0x424528 FMOV	X14, D5

    (252) 0x42452c STR	D6, [X12, X14,LSL #3]

    (252) 0x424530 LDR	D6, [X1, X8,LSL #3]

    (252) 0x424534 STR	D6, [X13, X14,LSL #3]

    (252) 0x424538 MOV	W13, V4.S[1]

    (252) 0x42453c MOV	X12, V5.D[1]

    (252) 0x424540 TBZ	W13, #0, 424554

    (252) 0x424544 LDR	D6, [X17, X8,LSL #3]

    (252) 0x424548 STR	D6, [X9, X12,LSL #3]

    (252) 0x42454c LDR	D6, [X1, X8,LSL #3]

    (252) 0x424550 STR	D6, [X10, X12,LSL #3]

    (252) 0x424554 ADD	X10, X21, #1

    (252) 0x424558 FMOV	W13, S2

    (252) 0x42455c MADD	X9, X0, X10, XZR

    (252) 0x424560 MADD	X10, X3, X10, XZR

    (252) 0x424564 ADD	X9, X18, X9,LSL #3

    (252) 0x424568 ADD	X10, X2, X10,LSL #3

    (252) 0x42456c TBZ	W13, #0, 424584

    (252) 0x424570 LDR	D6, [X17, X8,LSL #3]

    (252) 0x424574 FMOV	X13, D3

    (252) 0x424578 STR	D6, [X9, X13,LSL #3]

    (252) 0x42457c LDR	D3, [X1, X8,LSL #3]

    (252) 0x424580 STR	D3, [X10, X13,LSL #3]

    (252) 0x424584 ADD	X14, X30, #1

    (252) 0x424588 MOV	W15, V2.S[1]

    (252) 0x42458c MADD	X13, X0, X14, XZR

    (252) 0x424590 MADD	X14, X3, X14, XZR

    (252) 0x424594 ADD	X13, X18, X13,LSL #3

    (252) 0x424598 ADD	X14, X2, X14,LSL #3

    (252) 0x42459c TBZ	W15, #0, 4245c4

    (252) 0x4245a0 LDR	D2, [X17, X8,LSL #3]

    (252) 0x4245a4 STR	D2, [X13, X11,LSL #3]

    (252) 0x4245a8 LDR	D2, [X1, X8,LSL #3]

    (252) 0x4245ac STR	D2, [X14, X11,LSL #3]

    (252) 0x4245b0 FMOV	W11, S4

    (252) 0x4245b4 TBNZ	W11, #0, 4245cc

    (252) 0x4245b8 MOV	W9, V4.S[1]

    (252) 0x4245bc TBZ	W9, #0, 424320

    (252) 0x4245c0 B	4245e8

    (252) 0x4245c4 FMOV	W11, S4

    (252) 0x4245c8 TBZ	W11, #0, 4245b8

    (252) 0x4245cc LDR	D2, [X17, X8,LSL #3]

    (252) 0x4245d0 FMOV	X11, D5

    (252) 0x4245d4 STR	D2, [X9, X11,LSL #3]

    (252) 0x4245d8 LDR	D2, [X1, X8,LSL #3]

    (252) 0x4245dc STR	D2, [X10, X11,LSL #3]

    (252) 0x4245e0 MOV	W9, V4.S[1]

    (252) 0x4245e4 TBZ	W9, #0, 424320

    (252) 0x4245e8 LDR	D2, [X17, X8,LSL #3]

    (252) 0x4245ec STR	D2, [X13, X12,LSL #3]

    (252) 0x4245f0 LDR	D2, [X1, X8,LSL #3]

    (252) 0x4245f4 STR	D2, [X14, X12,LSL #3]

    (252) 0x4245f8 B	424320

  (247) 0x4245fc LDR	X10, [X29, #152]

  (247) 0x424600 LDR	X5, [X9, #536]

  (247) 0x424604 LDR	X6, [X9, #568]

  (247) 0x424608 ADD	X23, X11, #1

  (247) 0x42460c SUB	X9, X23, X4

  (247) 0x424610 LDR	X27, [X10, #8]

  (247) 0x424614 CMP	X9, #1

  (247) 0x424618 B.HI	424a1c

  (247) 0x42461c ORR	X21, XZR, X4

  (247) 0x424620 B	424d0c

  (247) 0x424624 LDP	X10, X9, [X29, #104]

  (247) 0x424628 ADD	X23, X11, #1

  (247) 0x42462c LDR	X9, [X9, #8]

  (247) 0x424630 LDR	X7, [X10, #8]

  (247) 0x424634 STR	X9, [SP, #48]

  (247) 0x424638 SUB	X9, X23, X4

  (247) 0x42463c CMP	X9, #2

  (247) 0x424640 B.CC	424e48

  (247) 0x424644 STP	X9, X23, [SP, #16]

  (247) 0x424648 AND	X9, X9, #8127

  (247) 0x42464c DUP	V0.2S, W24

  (247) 0x424650 SUB	X28, XZR, X24,LSL #32

  (247) 0x424654 SUB	X27, XZR, X24

  (247) 0x424658 UBFM	X30, X4, #32, #31

  (247) 0x42465c MOVZ	X13, #1

  (247) 0x424660 MOVZ	X14, #2

  (247) 0x424664 STR	X22, [SP, #56]

  (247) 0x424668 STR	W25, [SP, #36]

  (247) 0x42466c ORR	X25, XZR, XZR

  (247) 0x424670 STR	X9, [SP, #40]

  (247) 0x424674 ADD	X9, X4, X9

  (247) 0x424678 STR	X9, [SP, #8]

  (247) 0x42467c MOVZ	W9, #1

  (247) 0x424680 DUP	V1.2D, X9

  (247) 0x424684 B	4246a0

    (248) 0x424688 LDR	X9, [SP, #40]

    (248) 0x42468c ADD	X25, X25, #2

    (248) 0x424690 ADD	X30, X30, X14

    (248) 0x424694 MOVZ	X13, #1

    (248) 0x424698 CMP	X9, X25

    (248) 0x42469c B.EQ	424e2c

    (248) 0x4246a0 ADD	X19, X4, X25

    (248) 0x4246a4 LDR	X9, [SP, #56]

    (248) 0x4246a8 SDIV	X26, X19, X24

    (248) 0x4246ac ADD	X20, X19, #1

    (248) 0x4246b0 ADD	X9, X9, X8,LSL #3

    (248) 0x4246b4 LD1R	{V2.2D}, [X9]

    (248) 0x4246b8 ADD	X9, X30, X13

    (248) 0x4246bc MADD	X11, X28, X26, X9

    (248) 0x4246c0 SDIV	X22, X20, X24

    (248) 0x4246c4 SBFM	X11, X11, #29, #63

    (248) 0x4246c8 LDR	D3, [X5, X11]

    (248) 0x4246cc MADD	X12, X28, X22, X30

    (248) 0x4246d0 ADD	X12, X12, X14

    (248) 0x4246d4 ADD	X12, X5, X12,ASR #29

    (248) 0x4246d8 MADD	X10, X28, X26, X30

    (248) 0x4246dc SBFM	X23, X10, #32, #63

    (248) 0x4246e0 LD1	{V3.D[1]}, [X12]

    (248) 0x4246e4 FCMGE	V2.2D, V3.2D, V2.2D

    (248) 0x4246e8 XTN	V5.2S, V2.2D

    (248) 0x4246ec FMOV	W10, S5

    (248) 0x4246f0 TBZ	W10, #0, 424720

    (248) 0x4246f4 LDR	D3, [X5, X23,LSL #3]

    (248) 0x4246f8 LDR	D4, [X7, X8,LSL #3]

    (248) 0x4246fc MADD	X9, X28, X22, X9

    (248) 0x424700 SBFM	X21, X9, #32, #63

    (248) 0x424704 MOV	W9, V5.S[1]

    (248) 0x424708 TBZ	W9, #0, 424740

    (248) 0x42470c B	424730

0x424710 HINT	#0

0x424714 HINT	#0

0x424718 HINT	#0

0x42471c HINT	#0

    (248) 0x424720 MADD	X9, X28, X22, X9

    (248) 0x424724 SBFM	X21, X9, #32, #63

    (248) 0x424728 MOV	W9, V5.S[1]

    (248) 0x42472c TBZ	W9, #0, 424740

    (248) 0x424730 ADD	X9, X5, X21,LSL #3

    (248) 0x424734 LD1	{V3.D[1]}, [X9]

    (248) 0x424738 ADD	X9, X7, X8,LSL #3

    (248) 0x42473c LD1	{V4.D[1]}, [X9]

    (248) 0x424740 FCMGT	V3.2D, V4.2D, V3.2D

    (248) 0x424744 UBFM	X10, X26, #32, #31

    (248) 0x424748 AND	V2.16B, V2.16B, V3.16B

    (248) 0x42474c XTN	V2.2S, V2.2D

    (248) 0x424750 FMOV	W9, S2

    (248) 0x424754 TBZ	W9, #0, 424780

    (248) 0x424758 ADD	X9, X10, X13

    (248) 0x42475c SBFM	X9, X9, #29, #63

    (248) 0x424760 LDR	D3, [X6, X9]

    (248) 0x424764 MOV	W11, V2.S[1]

    (248) 0x424768 UBFM	X9, X22, #32, #31

    (248) 0x42476c TBNZ	W11, #0, 42478c

    (248) 0x424770 B	424798

0x424774 HINT	#0

0x424778 HINT	#0

0x42477c HINT	#0

    (248) 0x424780 MOV	W11, V2.S[1]

    (248) 0x424784 UBFM	X9, X22, #32, #31

    (248) 0x424788 TBZ	W11, #0, 424798

    (248) 0x42478c ADD	X11, X9, X13

    (248) 0x424790 ADD	X11, X6, X11,ASR #29

    (248) 0x424794 LD1	{V3.D[1]}, [X11]

    (248) 0x424798 LDUR	X11, [X29, #464]

    (248) 0x42479c ADD	X11, X11, X8,LSL #3

    (248) 0x4247a0 LD1R	{V4.2D}, [X11]

    (248) 0x4247a4 SBFM	X11, X10, #32, #63

    (248) 0x4247a8 FCMGE	V3.2D, V3.2D, V4.2D

    (248) 0x4247ac XTN	V3.2S, V3.2D

    (248) 0x4247b0 AND	V2.8B, V2.8B, V3.8B

    (248) 0x4247b4 FMOV	W10, S2

    (248) 0x4247b8 TBZ	W10, #0, 424824

    (248) 0x4247bc LDR	X10, [SP, #48]

    (248) 0x4247c0 LDR	D3, [X6, X11,LSL #3]

    (248) 0x4247c4 LDR	D4, [X10, X8,LSL #3]

    (248) 0x4247c8 SBFM	X12, X9, #32, #63

    (248) 0x4247cc MOV	W9, V2.S[1]

    (248) 0x4247d0 TBNZ	W9, #0, 424830

    (248) 0x4247d4 FCMGT	V3.2D, V4.2D, V3.2D

    (248) 0x4247d8 XTN	V3.2S, V3.2D

    (248) 0x4247dc AND	V2.8B, V2.8B, V3.8B

    (248) 0x4247e0 FMOV	W9, S2

    (248) 0x4247e4 TBZ	W9, #0, 424858

    (248) 0x4247e8 LDP	X10, X9, [X29, #960]

    (248) 0x4247ec LDR	D3, [X9, X8,LSL #3]

    (248) 0x4247f0 LDUR	X9, [X29, #440]

    (248) 0x4247f4 MADD	X9, X9, X11, XZR

    (248) 0x4247f8 ADD	X9, X10, X9,LSL #3

    (248) 0x4247fc STR	D3, [X9, X23,LSL #3]

    (248) 0x424800 LDP	X10, X9, [SP, #72]

    (248) 0x424804 LDR	D3, [X9, X8,LSL #3]

    (248) 0x424808 LDR	X9, [SP, #64]

    (248) 0x42480c MADD	X9, X9, X11, XZR

    (248) 0x424810 ADD	X9, X10, X9,LSL #3

    (248) 0x424814 STR	D3, [X9, X23,LSL #3]

    (248) 0x424818 MOV	W9, V2.S[1]

    (248) 0x42481c TBNZ	W9, #0, 424860

    (248) 0x424820 B	424890

    (248) 0x424824 SBFM	X12, X9, #32, #63

    (248) 0x424828 MOV	W9, V2.S[1]

    (248) 0x42482c TBZ	W9, #0, 4247d4

    (248) 0x424830 ADD	X9, X6, X12,LSL #3

    (248) 0x424834 LD1	{V3.D[1]}, [X9]

    (248) 0x424838 LDR	X9, [SP, #48]

    (248) 0x42483c ADD	X9, X9, X8,LSL #3

    (248) 0x424840 LD1	{V4.D[1]}, [X9]

    (248) 0x424844 FCMGT	V3.2D, V4.2D, V3.2D

    (248) 0x424848 XTN	V3.2S, V3.2D

    (248) 0x42484c AND	V2.8B, V2.8B, V3.8B

    (248) 0x424850 FMOV	W9, S2

    (248) 0x424854 TBNZ	W9, #0, 4247e8

    (248) 0x424858 MOV	W9, V2.S[1]

    (248) 0x42485c TBZ	W9, #0, 424890

    (248) 0x424860 LDP	X10, X9, [X29, #960]

    (248) 0x424864 LDR	D3, [X9, X8,LSL #3]

    (248) 0x424868 LDUR	X9, [X29, #440]

    (248) 0x42486c MADD	X9, X9, X12, XZR

    (248) 0x424870 ADD	X9, X10, X9,LSL #3

    (248) 0x424874 STR	D3, [X9, X21,LSL #3]

    (248) 0x424878 LDP	X10, X9, [SP, #72]

    (248) 0x42487c LDR	D3, [X9, X8,LSL #3]

    (248) 0x424880 LDR	X9, [SP, #64]

    (248) 0x424884 MADD	X9, X9, X12, XZR

    (248) 0x424888 ADD	X9, X10, X9,LSL #3

    (248) 0x42488c STR	D3, [X9, X21,LSL #3]

    (248) 0x424890 FMOV	S3, W26

    (248) 0x424894 SBFM	X11, X26, #0, #31

    (248) 0x424898 MADD	X9, X0, X11, XZR

    (248) 0x42489c FMOV	S4, W19

    (248) 0x4248a0 ADD	X13, X18, X9,LSL #3

    (248) 0x4248a4 MOV	V3.S[1], W22

    (248) 0x4248a8 MOV	V4.S[1], W20

    (248) 0x4248ac MADD	X9, X3, X11, XZR

    (248) 0x4248b0 ADD	X14, X2, X9,LSL #3

    (248) 0x4248b4 FMOV	W9, S2

    (248) 0x4248b8 MLS	V4.2S, V0.2S, V3.2S

    (248) 0x4248bc SSHLL	V3.2D, V4.2S, #32

    (248) 0x4248c0 TBZ	W9, #0, 4248d8

    (248) 0x4248c4 LDR	D4, [X17, X8,LSL #3]

    (248) 0x4248c8 FMOV	X9, D3

    (248) 0x4248cc STR	D4, [X13, X9,LSL #3]

    (248) 0x4248d0 LDR	D4, [X1, X8,LSL #3]

    (248) 0x4248d4 STR	D4, [X14, X9,LSL #3]

    (248) 0x4248d8 SBFM	X12, X22, #0, #31

    (248) 0x4248dc MOV	W15, V2.S[1]

    (248) 0x4248e0 MADD	X9, X0, X12, XZR

    (248) 0x4248e4 MADD	X10, X3, X12, XZR

    (248) 0x4248e8 ADD	X9, X18, X9,LSL #3

    (248) 0x4248ec ADD	X10, X2, X10,LSL #3

    (248) 0x4248f0 TBZ	W15, #0, 424908

    (248) 0x4248f4 LDR	D4, [X17, X8,LSL #3]

    (248) 0x4248f8 MOV	X15, V3.D[1]

    (248) 0x4248fc STR	D4, [X9, X15,LSL #3]

    (248) 0x424900 LDR	D4, [X1, X8,LSL #3]

    (248) 0x424904 STR	D4, [X10, X15,LSL #3]

    (248) 0x424908 MADD	X15, X27, X26, X19

    (248) 0x42490c MADD	X16, X27, X22, X20

    (248) 0x424910 FMOV	D4, X15

    (248) 0x424914 MOV	V4.D[1], X16

    (248) 0x424918 SHL	V4.2D, V4.2D, #32

    (248) 0x42491c SSHR	V5.2D, V4.2D, #32

    (248) 0x424920 ADD	V4.2D, V3.2D, V1.2D

    (248) 0x424924 CMGE	V5.2D, V5.2D, V3.2D

    (248) 0x424928 XTN	V5.2S, V5.2D

    (248) 0x42492c AND	V5.8B, V2.8B, V5.8B

    (248) 0x424930 FMOV	W15, S5

    (248) 0x424934 TBZ	W15, #0, 42494c

    (248) 0x424938 LDR	D6, [X17, X8,LSL #3]

    (248) 0x42493c FMOV	X15, D4

    (248) 0x424940 STR	D6, [X13, X15,LSL #3]

    (248) 0x424944 LDR	D6, [X1, X8,LSL #3]

    (248) 0x424948 STR	D6, [X14, X15,LSL #3]

    (248) 0x42494c MOV	W13, V5.S[1]

    (248) 0x424950 TBZ	W13, #0, 424968

    (248) 0x424954 LDR	D6, [X17, X8,LSL #3]

    (248) 0x424958 MOV	X13, V4.D[1]

    (248) 0x42495c STR	D6, [X9, X13,LSL #3]

    (248) 0x424960 LDR	D6, [X1, X8,LSL #3]

    (248) 0x424964 STR	D6, [X10, X13,LSL #3]

    (248) 0x424968 ADD	X10, X11, #1

    (248) 0x42496c FMOV	W11, S2

    (248) 0x424970 MOVZ	X14, #2

    (248) 0x424974 MADD	X9, X0, X10, XZR

    (248) 0x424978 MADD	X10, X3, X10, XZR

    (248) 0x42497c ADD	X9, X18, X9,LSL #3

    (248) 0x424980 ADD	X10, X2, X10,LSL #3

    (248) 0x424984 TBZ	W11, #0, 42499c

    (248) 0x424988 LDR	D6, [X17, X8,LSL #3]

    (248) 0x42498c FMOV	X11, D3

    (248) 0x424990 STR	D6, [X9, X11,LSL #3]

    (248) 0x424994 LDR	D6, [X1, X8,LSL #3]

    (248) 0x424998 STR	D6, [X10, X11,LSL #3]

    (248) 0x42499c ADD	X12, X12, #1

    (248) 0x4249a0 MOV	W13, V2.S[1]

    (248) 0x4249a4 MADD	X11, X0, X12, XZR

    (248) 0x4249a8 MADD	X12, X3, X12, XZR

    (248) 0x4249ac ADD	X11, X18, X11,LSL #3

    (248) 0x4249b0 ADD	X12, X2, X12,LSL #3

    (248) 0x4249b4 TBZ	W13, #0, 4249e0

    (248) 0x4249b8 LDR	D2, [X17, X8,LSL #3]

    (248) 0x4249bc MOV	X13, V3.D[1]

    (248) 0x4249c0 STR	D2, [X11, X13,LSL #3]

    (248) 0x4249c4 LDR	D2, [X1, X8,LSL #3]

    (248) 0x4249c8 STR	D2, [X12, X13,LSL #3]

    (248) 0x4249cc FMOV	W13, S5

    (248) 0x4249d0 TBNZ	W13, #0, 4249e8

    (248) 0x4249d4 MOV	W9, V5.S[1]

    (248) 0x4249d8 TBZ	W9, #0, 424688

    (248) 0x4249dc B	424a04

    (248) 0x4249e0 FMOV	W13, S5

    (248) 0x4249e4 TBZ	W13, #0, 4249d4

    (248) 0x4249e8 LDR	D2, [X17, X8,LSL #3]

    (248) 0x4249ec FMOV	X13, D4

    (248) 0x4249f0 STR	D2, [X9, X13,LSL #3]

    (248) 0x4249f4 LDR	D2, [X1, X8,LSL #3]

    (248) 0x4249f8 STR	D2, [X10, X13,LSL #3]

    (248) 0x4249fc MOV	W9, V5.S[1]

    (248) 0x424a00 TBZ	W9, #0, 424688

    (248) 0x424a04 LDR	D2, [X17, X8,LSL #3]

    (248) 0x424a08 MOV	X9, V4.D[1]

    (248) 0x424a0c STR	D2, [X11, X9,LSL #3]

    (248) 0x424a10 LDR	D2, [X1, X8,LSL #3]

    (248) 0x424a14 STR	D2, [X12, X9,LSL #3]

    (248) 0x424a18 B	424688

  (247) 0x424a1c STP	X9, X23, [SP, #16]

  (247) 0x424a20 AND	X10, X9, #8127

  (247) 0x424a24 SUB	W7, WZR, W24

  (247) 0x424a28 UBFM	X30, X4, #32, #31

  (247) 0x424a2c STR	W25, [SP, #36]

  (247) 0x424a30 ORR	X23, XZR, XZR

  (247) 0x424a34 ADD	X21, X4, X10

  (247) 0x424a38 SUB	X9, XZR, X24

  (247) 0x424a3c STP	X9, X10, [SP, #48]

  (247) 0x424a40 SUB	X9, XZR, X24,LSL #32

  (247) 0x424a44 STR	X9, [SP, #40]

  (247) 0x424a48 MOVZ	W9, #1

  (247) 0x424a4c DUP	V0.2D, X9

  (247) 0x424a50 B	424a78

0x424a54 HINT	#0

0x424a58 HINT	#0

0x424a5c HINT	#0

    (250) 0x424a60 MOVZ	X9, #2

    (250) 0x424a64 ADD	X23, X23, #2

    (250) 0x424a68 ADD	X30, X30, X9

    (250) 0x424a6c LDR	X9, [SP, #56]

    (250) 0x424a70 CMP	X9, X23

    (250) 0x424a74 B.EQ	424cf8

    (250) 0x424a78 ADD	X11, X4, X23

    (250) 0x424a7c ADD	X9, X22, X8,LSL #3

    (250) 0x424a80 MOVZ	X15, #1

    (250) 0x424a84 ORR	X26, XZR, X22

    (250) 0x424a88 ADD	X12, X11, #1

    (250) 0x424a8c SDIV	X13, X11, X24

    (250) 0x424a90 LD1R	{V1.2D}, [X9]

    (250) 0x424a94 LDUR	X9, [X29, #464]

    (250) 0x424a98 ADD	X9, X9, X8,LSL #3

    (250) 0x424a9c LD1R	{V2.2D}, [X9]

    (250) 0x424aa0 LDR	X9, [SP, #40]

    (250) 0x424aa4 SBFM	X22, X13, #0, #31

    (250) 0x424aa8 SDIV	X14, X12, X24

    (250) 0x424aac MADD	X10, X9, X13, X30

    (250) 0x424ab0 MADD	X9, X9, X14, X30

    (250) 0x424ab4 ADD	X9, X9, X15

    (250) 0x424ab8 SBFM	X15, X10, #29, #63

    (250) 0x424abc LDR	D3, [X5, X15]

    (250) 0x424ac0 ADD	X16, X5, X9,ASR #29

    (250) 0x424ac4 ADD	X15, X6, W14,SXTW #3

    (250) 0x424ac8 LD1	{V3.D[1]}, [X16]

    (250) 0x424acc FSUB	V1.2D, V3.2D, V1.2D

    (250) 0x424ad0 LDR	D3, [X6, X13,SXTW #3]

    (250) 0x424ad4 FMUL	V1.2D, V1.2D, V1.2D

    (250) 0x424ad8 LD1	{V3.D[1]}, [X15]

    (250) 0x424adc ADD	X15, X27, X8,LSL #3

    (250) 0x424ae0 FSUB	V2.2D, V3.2D, V2.2D

    (250) 0x424ae4 FMLA	V1.2D, V2.2D, V2.2D

    (250) 0x424ae8 LD1R	{V2.2D}, [X15]

    (250) 0x424aec FSQRT	V1.2D, V1.2D

    (250) 0x424af0 FCMGE	V2.2D, V2.2D, V1.2D

    (250) 0x424af4 XTN	V1.2S, V2.2D

    (250) 0x424af8 FMOV	W15, S1

    (250) 0x424afc TBZ	W15, #0, 424b34

    (250) 0x424b00 LDP	X16, X15, [X29, #960]

    (250) 0x424b04 SBFM	X10, X10, #32, #63

    (250) 0x424b08 LDR	D3, [X15, X8,LSL #3]

    (250) 0x424b0c LDUR	X15, [X29, #440]

    (250) 0x424b10 MADD	X15, X15, X22, XZR

    (250) 0x424b14 ADD	X15, X16, X15,LSL #3

    (250) 0x424b18 STR	D3, [X15, X10,LSL #3]

    (250) 0x424b1c LDP	X16, X15, [SP, #72]

    (250) 0x424b20 LDR	D3, [X15, X8,LSL #3]

    (250) 0x424b24 LDR	X15, [SP, #64]

    (250) 0x424b28 MADD	X15, X15, X22, XZR

    (250) 0x424b2c ADD	X15, X16, X15,LSL #3

    (250) 0x424b30 STR	D3, [X15, X10,LSL #3]

    (250) 0x424b34 MOV	W10, V1.S[1]

    (250) 0x424b38 SBFM	X19, X14, #0, #31

    (250) 0x424b3c TBZ	W10, #0, 424b74

    (250) 0x424b40 LDP	X15, X10, [X29, #960]

    (250) 0x424b44 SBFM	X9, X9, #32, #63

    (250) 0x424b48 LDR	D3, [X10, X8,LSL #3]

    (250) 0x424b4c LDUR	X10, [X29, #440]

    (250) 0x424b50 MADD	X10, X10, X19, XZR

    (250) 0x424b54 ADD	X10, X15, X10,LSL #3

    (250) 0x424b58 STR	D3, [X10, X9,LSL #3]

    (250) 0x424b5c LDP	X15, X10, [SP, #72]

    (250) 0x424b60 LDR	D3, [X10, X8,LSL #3]

    (250) 0x424b64 LDR	X10, [SP, #64]

    (250) 0x424b68 MADD	X10, X10, X19, XZR

    (250) 0x424b6c ADD	X10, X15, X10,LSL #3

    (250) 0x424b70 STR	D3, [X10, X9,LSL #3]

    (250) 0x424b74 ADD	W9, W4, W23

    (250) 0x424b78 MADD	W10, W7, W13, W9

    (250) 0x424b7c SBFM	X15, X10, #0, #31

    (250) 0x424b80 MADD	X10, X0, X22, XZR

    (250) 0x424b84 ADD	X25, X18, X10,LSL #3

    (250) 0x424b88 MADD	X10, X3, X22, XZR

    (250) 0x424b8c ADD	X20, X2, X10,LSL #3

    (250) 0x424b90 FMOV	W10, S1

    (250) 0x424b94 TBZ	W10, #0, 424ba8

    (250) 0x424b98 LDR	D3, [X17, X8,LSL #3]

    (250) 0x424b9c STR	D3, [X25, X15,LSL #3]

    (250) 0x424ba0 LDR	D3, [X1, X8,LSL #3]

    (250) 0x424ba4 STR	D3, [X20, X15,LSL #3]

    (250) 0x424ba8 MADD	W9, W7, W14, W9

    (250) 0x424bac ORR	W28, WZR, W7

    (250) 0x424bb0 MOV	W7, V1.S[1]

    (250) 0x424bb4 ADD	W9, W9, #1

    (250) 0x424bb8 SBFM	X16, X9, #0, #31

    (250) 0x424bbc MADD	X9, X0, X19, XZR

    (250) 0x424bc0 ADD	X10, X18, X9,LSL #3

    (250) 0x424bc4 MADD	X9, X3, X19, XZR

    (250) 0x424bc8 ADD	X9, X2, X9,LSL #3

    (250) 0x424bcc TBZ	W7, #0, 424be0

    (250) 0x424bd0 LDR	D3, [X17, X8,LSL #3]

    (250) 0x424bd4 STR	D3, [X10, X16,LSL #3]

    (250) 0x424bd8 LDR	D3, [X1, X8,LSL #3]

    (250) 0x424bdc STR	D3, [X9, X16,LSL #3]

    (250) 0x424be0 LDR	X7, [SP, #48]

    (250) 0x424be4 FMOV	D4, X15

    (250) 0x424be8 MOV	V4.D[1], X16

    (250) 0x424bec MADD	X11, X7, X13, X11

    (250) 0x424bf0 MADD	X12, X7, X14, X12

    (250) 0x424bf4 FMOV	D3, X11

    (250) 0x424bf8 MOV	V3.D[1], X12

    (250) 0x424bfc SHL	V3.2D, V3.2D, #32

    (250) 0x424c00 SSHR	V5.2D, V3.2D, #32

    (250) 0x424c04 ADD	V3.2D, V4.2D, V0.2D

    (250) 0x424c08 CMGE	V4.2D, V5.2D, V4.2D

    (250) 0x424c0c AND	V2.16B, V2.16B, V4.16B

    (250) 0x424c10 XTN	V2.2S, V2.2D

    (250) 0x424c14 FMOV	W11, S2

    (250) 0x424c18 TBZ	W11, #0, 424c30

    (250) 0x424c1c LDR	D4, [X17, X8,LSL #3]

    (250) 0x424c20 FMOV	X11, D3

    (250) 0x424c24 STR	D4, [X25, X11,LSL #3]

    (250) 0x424c28 LDR	D4, [X1, X8,LSL #3]

    (250) 0x424c2c STR	D4, [X20, X11,LSL #3]

    (250) 0x424c30 MOV	W12, V2.S[1]

    (250) 0x424c34 ORR	W7, WZR, W28

    (250) 0x424c38 MOV	X11, V3.D[1]

    (250) 0x424c3c TBZ	W12, #0, 424c50

    (250) 0x424c40 LDR	D4, [X17, X8,LSL #3]

    (250) 0x424c44 STR	D4, [X10, X11,LSL #3]

    (250) 0x424c48 LDR	D4, [X1, X8,LSL #3]

    (250) 0x424c4c STR	D4, [X9, X11,LSL #3]

    (250) 0x424c50 ADD	X10, X22, #1

    (250) 0x424c54 FMOV	W12, S1

    (250) 0x424c58 MADD	X9, X0, X10, XZR

    (250) 0x424c5c MADD	X10, X3, X10, XZR

    (250) 0x424c60 ADD	X9, X18, X9,LSL #3

    (250) 0x424c64 ADD	X10, X2, X10,LSL #3

    (250) 0x424c68 TBZ	W12, #0, 424c7c

    (250) 0x424c6c LDR	D4, [X17, X8,LSL #3]

    (250) 0x424c70 STR	D4, [X9, X15,LSL #3]

    (250) 0x424c74 LDR	D4, [X1, X8,LSL #3]

    (250) 0x424c78 STR	D4, [X10, X15,LSL #3]

    (250) 0x424c7c ADD	X13, X19, #1

    (250) 0x424c80 MOV	W14, V1.S[1]

    (250) 0x424c84 ORR	X22, XZR, X26

    (250) 0x424c88 MADD	X12, X0, X13, XZR

    (250) 0x424c8c MADD	X13, X3, X13, XZR

    (250) 0x424c90 ADD	X12, X18, X12,LSL #3

    (250) 0x424c94 ADD	X13, X2, X13,LSL #3

    (250) 0x424c98 TBZ	W14, #0, 424cc0

    (250) 0x424c9c LDR	D1, [X17, X8,LSL #3]

    (250) 0x424ca0 STR	D1, [X12, X16,LSL #3]

    (250) 0x424ca4 LDR	D1, [X1, X8,LSL #3]

    (250) 0x424ca8 STR	D1, [X13, X16,LSL #3]

    (250) 0x424cac FMOV	W14, S2

    (250) 0x424cb0 TBNZ	W14, #0, 424cc8

    (250) 0x424cb4 MOV	W9, V2.S[1]

    (250) 0x424cb8 TBZ	W9, #0, 424a60

    (250) 0x424cbc B	424ce4

    (250) 0x424cc0 FMOV	W14, S2

    (250) 0x424cc4 TBZ	W14, #0, 424cb4

    (250) 0x424cc8 LDR	D1, [X17, X8,LSL #3]

    (250) 0x424ccc FMOV	X14, D3

    (250) 0x424cd0 STR	D1, [X9, X14,LSL #3]

    (250) 0x424cd4 LDR	D1, [X1, X8,LSL #3]

    (250) 0x424cd8 STR	D1, [X10, X14,LSL #3]

    (250) 0x424cdc MOV	W9, V2.S[1]

    (250) 0x424ce0 TBZ	W9, #0, 424a60

    (250) 0x424ce4 LDR	D1, [X17, X8,LSL #3]

    (250) 0x424ce8 STR	D1, [X12, X11,LSL #3]

    (250) 0x424cec LDR	D1, [X1, X8,LSL #3]

    (250) 0x424cf0 STR	D1, [X13, X11,LSL #3]

    (250) 0x424cf4 B	424a60

  (247) 0x424cf8 LDP	X9, X23, [SP, #16]

  (247) 0x424cfc LDR	X10, [SP, #56]

  (247) 0x424d00 LDR	W25, [SP, #36]

  (247) 0x424d04 CMP	X9, X10

  (247) 0x424d08 B.EQ	424224

  (247) 0x424d0c SUB	X12, XZR, X24,LSL #32

  (247) 0x424d10 SUB	W11, WZR, W24

  (247) 0x424d14 UBFM	X13, X21, #32, #31

  (247) 0x424d18 MOVZ	X14, #1

  (247) 0x424d1c B	424d30

    (249) 0x424d20 ADD	X21, X21, #1

    (249) 0x424d24 ADD	X13, X13, X14

    (249) 0x424d28 CMP	X23, X21

    (249) 0x424d2c B.EQ	424224

    (249) 0x424d30 SDIV	X15, X21, X24

    (249) 0x424d34 LDUR	X9, [X29, #464]

    (249) 0x424d38 LDR	D0, [X22, X8,LSL #3]

    (249) 0x424d3c LDR	D1, [X9, X8,LSL #3]

    (249) 0x424d40 MADD	X9, X12, X15, X13

    (249) 0x424d44 SBFM	X10, X9, #29, #63

    (249) 0x424d48 LDR	D2, [X5, X10]

    (249) 0x424d4c FSUB	D0, D2, S0

    (249) 0x424d50 LDR	D2, [X6, X15,SXTW #3]

    (249) 0x424d54 FMUL	D0, D0, D0

    (249) 0x424d58 FSUB	D1, D2, S1

    (249) 0x424d5c FMADD	D0, D1, D1, D0

    (249) 0x424d60 LDR	D1, [X27, X8,LSL #3]

    (249) 0x424d64 FSQRT	D0, D0

    (249) 0x424d68 FCMP	D0, D1

    (249) 0x424d6c B.GT	424d20

    (249) 0x424d70 LDP	X4, X16, [X29, #960]

    (249) 0x424d74 SBFM	X10, X9, #32, #63

    (249) 0x424d78 SBFM	X9, X15, #0, #31

    (249) 0x424d7c MADD	X7, X3, X9, XZR

    (249) 0x424d80 ADD	X19, X2, X7,LSL #3

    (249) 0x424d84 LDR	D0, [X16, X8,LSL #3]

    (249) 0x424d88 LDUR	X16, [X29, #440]

    (249) 0x424d8c MADD	X16, X16, X9, XZR

    (249) 0x424d90 ADD	X16, X4, X16,LSL #3

    (249) 0x424d94 STR	D0, [X16, X10,LSL #3]

    (249) 0x424d98 LDP	X4, X16, [SP, #72]

    (249) 0x424d9c LDR	D0, [X16, X8,LSL #3]

    (249) 0x424da0 LDR	X16, [SP, #64]

    (249) 0x424da4 MADD	X16, X16, X9, XZR

    (249) 0x424da8 ADD	X16, X4, X16,LSL #3

    (249) 0x424dac MADD	X4, X0, X9, XZR

    (249) 0x424db0 STR	D0, [X16, X10,LSL #3]

    (249) 0x424db4 MADD	W16, W11, W15, W21

    (249) 0x424db8 LDR	D0, [X17, X8,LSL #3]

    (249) 0x424dbc ADD	X4, X18, X4,LSL #3

    (249) 0x424dc0 SBFM	X15, X16, #0, #31

    (249) 0x424dc4 STR	D0, [X4, X16,SXTW #3]

    (249) 0x424dc8 LDR	D0, [X1, X8,LSL #3]

    (249) 0x424dcc STR	D0, [X19, X16,SXTW #3]

    (249) 0x424dd0 ADD	X16, X15, #1

    (249) 0x424dd4 CMP	X10, X15

    (249) 0x424dd8 B.LT	424dec

    (249) 0x424ddc LDR	D0, [X17, X8,LSL #3]

    (249) 0x424de0 STR	D0, [X4, X16,LSL #3]

    (249) 0x424de4 LDR	D0, [X1, X8,LSL #3]

    (249) 0x424de8 STR	D0, [X19, X16,LSL #3]

    (249) 0x424dec LDR	D0, [X17, X8,LSL #3]

    (249) 0x424df0 ADD	X4, X9, #1

    (249) 0x424df4 MADD	X9, X0, X4, XZR

    (249) 0x424df8 MADD	X4, X3, X4, XZR

    (249) 0x424dfc ADD	X9, X18, X9,LSL #3

    (249) 0x424e00 ADD	X4, X2, X4,LSL #3

    (249) 0x424e04 STR	D0, [X9, X15,LSL #3]

    (249) 0x424e08 LDR	D0, [X1, X8,LSL #3]

    (249) 0x424e0c STR	D0, [X4, X15,LSL #3]

    (249) 0x424e10 CMP	X10, X15

    (249) 0x424e14 B.LT	424d20

    (249) 0x424e18 LDR	D0, [X17, X8,LSL #3]

    (249) 0x424e1c STR	D0, [X9, X16,LSL #3]

    (249) 0x424e20 LDR	D0, [X1, X8,LSL #3]

    (249) 0x424e24 STR	D0, [X4, X16,LSL #3]

    (249) 0x424e28 B	424d20

  (247) 0x424e2c LDP	X4, X9, [SP, #8]

  (247) 0x424e30 LDR	X10, [SP, #40]

  (247) 0x424e34 LDR	W25, [SP, #36]

  (247) 0x424e38 LDR	X22, [SP, #56]

  (247) 0x424e3c LDR	X23, [SP, #24]

  (247) 0x424e40 CMP	X9, X10

  (247) 0x424e44 B.EQ	424224

(246) 0x424e48 SUB	X11, XZR, X24,LSL #32

(246) 0x424e4c SUB	W19, WZR, W24

(246) 0x424e50 UBFM	X12, X4, #32, #31

(246) 0x424e54 MOVZ	X13, #1

(246) 0x424e58 B	424e70

0x424e5c HINT	#0

(246) 0x424e60 ADD	X4, X4, #1

(246) 0x424e64 ADD	X12, X12, X13

(246) 0x424e68 CMP	X23, X4

(246) 0x424e6c B.EQ	424224

(246) 0x424e70 SDIV	X14, X4, X24

(246) 0x424e74 LDR	D0, [X22, X8,LSL #3]

(246) 0x424e78 MADD	X9, X11, X14, X12

(246) 0x424e7c ADD	X10, X9, X13

(246) 0x424e80 SBFM	X10, X10, #29, #63

(246) 0x424e84 LDR	D1, [X5, X10]

(246) 0x424e88 FCMP	D1, D0

(246) 0x424e8c B.LT	424e60

(246) 0x424e90 SBFM	X10, X9, #29, #63

(246) 0x424e94 LDR	D1, [X7, X8,LSL #3]

(246) 0x424e98 LDR	D0, [X5, X10]

(246) 0x424e9c FCMP	D0, D1

(246) 0x424ea0 B.GE	424e60

(246) 0x424ea4 LDUR	X10, [X29, #464]

(246) 0x424ea8 UBFM	X15, X14, #32, #31

(246) 0x424eac LDR	D0, [X10, X8,LSL #3]

(246) 0x424eb0 ADD	X10, X15, X13

(246) 0x424eb4 SBFM	X10, X10, #29, #63

(246) 0x424eb8 LDR	D1, [X6, X10]

(246) 0x424ebc FCMP	D1, D0

(246) 0x424ec0 B.LT	424e60

(246) 0x424ec4 SBFM	X10, X15, #29, #63

(246) 0x424ec8 LDR	D0, [X6, X10]

(246) 0x424ecc LDR	X10, [SP, #48]

(246) 0x424ed0 LDR	D1, [X10, X8,LSL #3]

(246) 0x424ed4 FCMP	D0, D1

(246) 0x424ed8 B.GE	424e60

(246) 0x424edc SBFM	X10, X9, #32, #63

(246) 0x424ee0 SBFM	X9, X15, #32, #63

(246) 0x424ee4 LDP	X16, X15, [X29, #960]

(246) 0x424ee8 MADD	W21, W19, W14, W4

(246) 0x424eec LDR	D0, [X15, X8,LSL #3]

(246) 0x424ef0 LDUR	X15, [X29, #440]

(246) 0x424ef4 MADD	X15, X15, X9, XZR

(246) 0x424ef8 ADD	X15, X16, X15,LSL #3

(246) 0x424efc STR	D0, [X15, X10,LSL #3]

(246) 0x424f00 LDR	X15, [SP, #80]

(246) 0x424f04 LDR	D0, [X15, X8,LSL #3]

(246) 0x424f08 LDR	X15, [SP, #64]

(246) 0x424f0c MADD	X9, X15, X9, XZR

(246) 0x424f10 LDR	X15, [SP, #72]

(246) 0x424f14 ADD	X9, X15, X9,LSL #3

(246) 0x424f18 SBFM	X15, X14, #0, #31

(246) 0x424f1c STR	D0, [X9, X10,LSL #3]

(246) 0x424f20 MADD	X14, X0, X15, XZR

(246) 0x424f24 SBFM	X9, X21, #0, #31

(246) 0x424f28 LDR	D0, [X17, X8,LSL #3]

(246) 0x424f2c ADD	X16, X18, X14,LSL #3

(246) 0x424f30 MADD	X14, X3, X15, XZR

(246) 0x424f34 ADD	X20, X2, X14,LSL #3

(246) 0x424f38 ADD	X14, X9, #1

(246) 0x424f3c STR	D0, [X16, X21,SXTW #3]

(246) 0x424f40 LDR	D0, [X1, X8,LSL #3]

(246) 0x424f44 STR	D0, [X20, X21,SXTW #3]

(246) 0x424f48 CMP	X10, X9

(246) 0x424f4c B.LT	424f60

(246) 0x424f50 LDR	D0, [X17, X8,LSL #3]

(246) 0x424f54 STR	D0, [X16, X14,LSL #3]

(246) 0x424f58 LDR	D0, [X1, X8,LSL #3]

(246) 0x424f5c STR	D0, [X20, X14,LSL #3]

(246) 0x424f60 LDR	D0, [X17, X8,LSL #3]

(246) 0x424f64 ADD	X16, X15, #1

(246) 0x424f68 MADD	X15, X0, X16, XZR

(246) 0x424f6c MADD	X16, X3, X16, XZR

(246) 0x424f70 ADD	X15, X18, X15,LSL #3

(246) 0x424f74 ADD	X16, X2, X16,LSL #3

(246) 0x424f78 STR	D0, [X15, X9,LSL #3]

(246) 0x424f7c LDR	D0, [X1, X8,LSL #3]

(246) 0x424f80 STR	D0, [X16, X9,LSL #3]

(246) 0x424f84 CMP	X10, X9

(246) 0x424f88 B.LT	424e60

(246) 0x424f8c LDR	D0, [X17, X8,LSL #3]

(246) 0x424f90 STR	D0, [X15, X14,LSL #3]

(246) 0x424f94 LDR	D0, [X1, X8,LSL #3]

(246) 0x424f98 STR	D0, [X16, X14,LSL #3]

(246) 0x424f9c B	424e60

  (247) 0x424fa0 LDP	X4, X9, [SP, #40]

  (247) 0x424fa4 LDR	W25, [SP, #36]

  (247) 0x424fa8 LDR	X22, [SP, #56]

  (247) 0x424fac CMP	X9, X16

  (247) 0x424fb0 B.EQ	424224

  (247) 0x424fb4 SUB	X12, XZR, X24,LSL #32

  (247) 0x424fb8 SUB	W11, WZR, W24

  (247) 0x424fbc UBFM	X13, X4, #32, #31

  (247) 0x424fc0 MOVZ	X14, #1

  (247) 0x424fc4 B	424fd8

    (251) 0x424fc8 ADD	X4, X4, #1

    (251) 0x424fcc ADD	X13, X13, X14

    (251) 0x424fd0 CMP	X7, X4

    (251) 0x424fd4 B.EQ	424224

    (251) 0x424fd8 SDIV	X15, X4, X24

    (251) 0x424fdc LDR	D0, [X22, X8,LSL #3]

    (251) 0x424fe0 MADD	X9, X12, X15, X13

    (251) 0x424fe4 SBFM	X10, X9, #29, #63

    (251) 0x424fe8 LDR	D1, [X5, X10]

    (251) 0x424fec FCMP	D1, D0

    (251) 0x424ff0 B.NE	424fc8

    (251) 0x424ff4 LDUR	X10, [X29, #464]

    (251) 0x424ff8 LDR	D1, [X6, X15,SXTW #3]

    (251) 0x424ffc LDR	D0, [X10, X8,LSL #3]

    (251) 0x425000 FCMP	D1, D0

    (251) 0x425004 B.NE	424fc8

    (251) 0x425008 LDP	X19, X16, [X29, #960]

    (251) 0x42500c SBFM	X10, X15, #0, #31

    (251) 0x425010 SBFM	X9, X9, #32, #63

    (251) 0x425014 MADD	X20, X3, X10, XZR

    (251) 0x425018 ADD	X20, X2, X20,LSL #3

    (251) 0x42501c LDR	D0, [X16, X8,LSL #3]

    (251) 0x425020 LDUR	X16, [X29, #440]

    (251) 0x425024 MADD	X16, X16, X10, XZR

    (251) 0x425028 ADD	X16, X19, X16,LSL #3

    (251) 0x42502c STR	D0, [X16, X9,LSL #3]

    (251) 0x425030 LDP	X19, X16, [SP, #72]

    (251) 0x425034 LDR	D0, [X16, X8,LSL #3]

    (251) 0x425038 LDR	X16, [SP, #64]

    (251) 0x42503c MADD	X16, X16, X10, XZR

    (251) 0x425040 ADD	X16, X19, X16,LSL #3

    (251) 0x425044 MADD	X19, X0, X10, XZR

    (251) 0x425048 STR	D0, [X16, X9,LSL #3]

    (251) 0x42504c MADD	W16, W11, W15, W4

    (251) 0x425050 LDR	D0, [X17, X8,LSL #3]

    (251) 0x425054 ADD	X19, X18, X19,LSL #3

    (251) 0x425058 SBFM	X15, X16, #0, #31

    (251) 0x42505c STR	D0, [X19, X16,SXTW #3]

    (251) 0x425060 LDR	D0, [X1, X8,LSL #3]

    (251) 0x425064 STR	D0, [X20, X16,SXTW #3]

    (251) 0x425068 ADD	X16, X15, #1

    (251) 0x42506c CMP	X9, X15

    (251) 0x425070 B.LT	425084

    (251) 0x425074 LDR	D0, [X17, X8,LSL #3]

    (251) 0x425078 STR	D0, [X19, X16,LSL #3]

    (251) 0x42507c LDR	D0, [X1, X8,LSL #3]

    (251) 0x425080 STR	D0, [X20, X16,LSL #3]

    (251) 0x425084 LDR	D0, [X17, X8,LSL #3]

    (251) 0x425088 ADD	X19, X10, #1

    (251) 0x42508c MADD	X10, X0, X19, XZR

    (251) 0x425090 MADD	X19, X3, X19, XZR

    (251) 0x425094 ADD	X10, X18, X10,LSL #3

    (251) 0x425098 ADD	X19, X2, X19,LSL #3

    (251) 0x42509c STR	D0, [X10, X15,LSL #3]

    (251) 0x4250a0 LDR	D0, [X1, X8,LSL #3]

    (251) 0x4250a4 STR	D0, [X19, X15,LSL #3]

    (251) 0x4250a8 CMP	X9, X15

    (251) 0x4250ac B.LT	424fc8

    (251) 0x4250b0 LDR	D0, [X17, X8,LSL #3]

    (251) 0x4250b4 STR	D0, [X10, X16,LSL #3]

    (251) 0x4250b8 LDR	D0, [X1, X8,LSL #3]

    (251) 0x4250bc STR	D0, [X19, X16,LSL #3]

    (251) 0x4250c0 B	424fc8

0x4250c4 HINT	#0

0x4250c8 HINT	#0

0x4250cc HINT	#0

0x4250d0 HINT	#0

0x4250d4 HINT	#0

0x4250d8 HINT	#0

0x4250dc HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-123
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 56% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.13 to 4.25 cycles (1.21x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.13 to 0.50 cycles (10.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.25	4.25	4.17	4.17	4.08	4.08	0.00	0.00	0.00	0.00	5.00	5.00	4.00	5.00	5.00
cycles	1.50	1.50	4.25	4.25	4.17	4.17	4.08	4.08	0.00	0.00	0.00	0.00	5.00	5.00	4.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.13

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.13 cycles. At this rate:

5% of peak load performance is reached (5.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
53% of peak store performance is reached (25.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, #1, #8, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LT 424250 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W25, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X24, X9, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46d1d0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X19, X24, X8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X19, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X4, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X11, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 424254 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-123
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.13 to 0.50 cycles (10.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.25	4.25	4.17	4.17	4.08	4.08	0.00	0.00	0.00	0.00	5.00	5.00	4.00	5.00	5.00
cycles	1.50	1.50	4.25	4.25	4.17	4.17	4.08	4.08	0.00	0.00	0.00	0.00	5.00	5.00	4.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.13

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.13 cycles. At this rate:

5% of peak load performance is reached (5.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
53% of peak store performance is reached (25.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, #1, #8, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LT 424250 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W25, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X24, X9, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46d1d0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #36	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X19, X24, X8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X19, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X4, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X11, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 424254 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
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HINT #0																					N/A
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HINT #0																					N/A
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HINT #0																					N/A
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HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone .omp_outlined.2]–	0.01	0.01
▼Loop 246 - generate_chunk.cpp:85-123 - exec–	0.00	0.00
▼Loop 247 - generate_chunk.cpp:85-123 - exec–	0.00	0.00
○Loop 248 - generate_chunk.cpp:85-98 - exec	0.01	0.01
○Loop 252 - generate_chunk.cpp:85-123 - exec	0.00	0.00
○Loop 249 - generate_chunk.cpp:86-112 - exec	0.00	0.00
○Loop 251 - generate_chunk.cpp:86-123 - exec	0.00	0.00
○Loop 250 - generate_chunk.cpp:85-112 - exec	0.00	0.00

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code