OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone .omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 3.76% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4213b0 SUB	SP, SP, #304

0x4213b4 STR	D10, [SP, #176]

0x4213b8 STP	D9, D8, [SP, #192]

0x4213bc STP	X29, X30, [SP, #208]

0x4213c0 STP	X28, X27, [SP, #224]

0x4213c4 STP	X26, X25, [SP, #240]

0x4213c8 STP	X24, X23, [SP, #256]

0x4213cc STP	X22, X21, [SP, #272]

0x4213d0 STP	X20, X19, [SP, #288]

0x4213d4 ADD	X29, SP, #208

0x4213d8 LDR	W8, [X2]

0x4213dc LDR	W26, [X4]

0x4213e0 LDR	W10, [X5]

0x4213e4 ADD	W27, W8, #1

0x4213e8 LDR	W8, [X3]

0x4213ec ADD	W9, W26, #1

0x4213f0 ADD	W10, W10, #2

0x4213f4 ADD	W8, W8, #2

0x4213f8 SUBS	W8, W8, W27

0x4213fc CCMP	W10, W9, #4, #12

0x421400 B.LE	421afc

0x421404 LDR	W1, [X0]

0x421408 LDR	X24, [X29, #192]

0x42140c SUB	W28, W10, W9

0x421410 MOVN	X9, #0

0x421414 ORR	X20, XZR, X7

0x421418 ORR	X21, XZR, X6

0x42141c ADRP	X0,

0x421420 ADD	X0, X0, #936

0x421424 SUB	X3, X29, #60

0x421428 SUB	X4, X29, #24

0x42142c STUR	XZR, [X29, #488]

0x421430 STUR	WZR, [X29, #452]

0x421434 SUB	X5, X29, #48

0x421438 SUB	X6, X29, #56

0x42143c UMADDL	X19, W28, W8, X9

0x421440 MOVZ	W8, #1

0x421444 MOVN	X9, #32784

0x421448 MOVZ	W2, #34

0x42144c STUR	X9, [X29, #440]

0x421450 MOVZ	W7, #1

0x421454 STR	X8, [SP]

0x421458 STP	X8, X19, [X29, #968]

0x42145c STR	W1, [SP, #52]

0x421460 BL	4034d0

0x421464 LDUR	X8, [X29, #464]

0x421468 CMP	X8, X19

0x42146c CSEL	X6, X8, X19, #11

0x421470 LDUR	X8, [X29, #488]

0x421474 STUR	X6, [X29, #464]

0x421478 STR	X8, [SP, #104]

0x42147c CMP	X8, X6

0x421480 B.GT	421a40

0x421484 LDP	X19, X7, [X29, #176]

0x421488 LDP	X1, X2, [X29, #144]

0x42148c LDP	X11, X13, [X29, #96]

0x421490 ADD	X25, X6, #1

0x421494 MOVN	X6, #32784

0x421498 LDR	X8, [X20, #8]

0x42149c LDP	X15, X16, [X29, #112]

0x4214a0 LDP	X4, X22, [X29, #160]

0x4214a4 LDP	X17, X0, [X29, #128]

0x4214a8 LDR	X30, [X21, #8]

0x4214ac STR	X8, [SP, #96]

0x4214b0 LDR	X8, [X11, #16]

0x4214b4 LDR	D1, [X1]

0x4214b8 LDR	D2, [X19]

0x4214bc LDR	D3, [X7]

0x4214c0 LDR	D0, [X16]

0x4214c4 LDR	X9, [X11]

0x4214c8 FADD	D1, D1, D1

0x4214cc LDR	X11, [SP, #104]

0x4214d0 STP	X9, X8, [X29, #928]

0x4214d4 LDR	X14, [X13, #16]

0x4214d8 LDR	X10, [X13]

0x4214dc LDR	X18, [X15, #16]

0x4214e0 LDR	X21, [X15]

0x4214e4 LDR	X16, [X17, #16]

0x4214e8 LDR	X17, [X17]

0x4214ec LDR	X23, [X0, #16]

0x4214f0 LDR	X8, [X0]

0x4214f4 LDR	X13, [X2, #16]

0x4214f8 LDR	X12, [X2]

0x4214fc LDR	X3, [X4, #16]

0x421500 LDR	X4, [X4]

0x421504 LDR	X5, [X22, #16]

0x421508 LDR	X7, [X22]

0x42150c FADD	D2, D2, D2

0x421510 FNEG	D3, D3

0x421514 SUB	X11, X25, X11

0x421518 CMP	X11, #2

0x42151c B.CS	42153c

0x421520 LDP	X11, X20, [SP, #96]

0x421524 FMOV	D4, X6

0x421528 ORR	X15, XZR, X10

0x42152c ORR	X0, XZR, X21

0x421530 ORR	X1, XZR, X23

0x421534 ORR	X2, XZR, X8

0x421538 B	4218a0

0x42153c DUP	V5.2D, X6

0x421540 MOVZ	X6, #35260

0x421544 STP	X11, X25, [SP, #16]

0x421548 AND	X0, X11, #8127

0x42154c LDR	X11, [SP, #104]

0x421550 DUP	V4.2D, V3.D[0]

0x421554 ORR	X15, XZR, X28

0x421558 STP	X26, X24, [SP, #32]

0x42155c ORR	X28, XZR, XZR

0x421560 STR	X30, [SP, #72]

0x421564 ORR	X1, XZR, X23

0x421568 ORR	X2, XZR, X8

0x42156c MOVK	X6, #38872

0x421570 STP	X0, X15, [SP, #80]

0x421574 SUB	W15, WZR, W15

0x421578 MOVK	X6, #53938

0x42157c STR	W15, [SP, #68]

0x421580 ORR	X15, XZR, X10

0x421584 MOVK	X6, #15516

0x421588 DUP	V6.2D, X6

0x42158c MOVZ	X6, #35260

0x421590 ADD	X20, X11, X0

0x421594 ADD	W11, W26, W11

0x421598 ORR	X0, XZR, X21

0x42159c MOVK	X6, #38872

0x4215a0 STR	X11, [SP, #56]

0x4215a4 MOVK	X6, #53938

0x4215a8 MOVK	X6, #48284

0x4215ac DUP	V7.2D, X6

0x4215b0 MOVZ	X6, #61264

0x4215b4 MOVK	X6, #55010

0x4215b8 MOVK	X6, #6884

0x4215bc MOVK	X6, #17483

0x4215c0 DUP	V16.2D, X6

(219) 0x4215c4 LDR	X8, [SP, #104]

(219) 0x4215c8 ORR	W11, WZR, W27

(219) 0x4215cc ADD	X6, X8, X28

(219) 0x4215d0 LDR	X8, [SP, #88]

(219) 0x4215d4 ADD	X19, X6, #1

(219) 0x4215d8 SDIV	X6, X6, X8

(219) 0x4215dc ADD	W26, W27, W6

(219) 0x4215e0 SDIV	X19, X19, X8

(219) 0x4215e4 LDR	X8, [SP, #56]

(219) 0x4215e8 ADD	W21, W8, W28

(219) 0x4215ec LDR	W8, [SP, #68]

(219) 0x4215f0 ADD	X28, X28, #2

(219) 0x4215f4 MADD	W30, W8, W6, W21

(219) 0x4215f8 ADD	W6, W27, W19

(219) 0x4215fc SBFM	X27, X26, #0, #31

(219) 0x421600 ADD	W22, W30, #1

(219) 0x421604 ADD	W30, W30, #2

(219) 0x421608 MADD	W24, W8, W19, W21

(219) 0x42160c LDR	X8, [SP, #72]

(219) 0x421610 ADD	W19, W24, #2

(219) 0x421614 SBFM	X21, X6, #0, #31

(219) 0x421618 SBFM	X19, X19, #61, #31

(219) 0x42161c ADD	X25, X8, X19

(219) 0x421620 LDR	D17, [X8, X22,SXTW #3]

(219) 0x421624 LDR	X8, [SP, #96]

(219) 0x421628 LDR	D18, [X8, X26,SXTW #3]

(219) 0x42162c ADD	X23, X8, W6,SXTW #3

(219) 0x421630 LDP	X9, X8, [X29, #928]

(219) 0x421634 LD1	{V17.D[1]}, [X25]

(219) 0x421638 MADD	X25, X9, X21, XZR

(219) 0x42163c ADD	X25, X8, X25,LSL #3

(219) 0x421640 LD1	{V18.D[1]}, [X23]

(219) 0x421644 MADD	X23, X9, X27, XZR

(219) 0x421648 ADD	X25, X25, X19

(219) 0x42164c ADD	X23, X8, X23,LSL #3

(219) 0x421650 MADD	X8, X15, X21, XZR

(219) 0x421654 LDR	D19, [X23, X22,SXTW #3]

(219) 0x421658 MADD	X23, X15, X27, XZR

(219) 0x42165c ADD	X8, X14, X8,LSL #3

(219) 0x421660 ADD	X23, X14, X23,LSL #3

(219) 0x421664 ADD	X8, X8, X19

(219) 0x421668 LDR	D20, [X23, X22,SXTW #3]

(219) 0x42166c MADD	X23, X0, X21, XZR

(219) 0x421670 ADD	X23, X18, X23,LSL #3

(219) 0x421674 FMINNM	V17.2D, V17.2D, V18.2D

(219) 0x421678 ADD	X23, X23, X19

(219) 0x42167c LD1	{V19.D[1]}, [X25]

(219) 0x421680 MADD	X25, X17, X21, XZR

(219) 0x421684 FMUL	V17.2D, V17.2D, V0.D[0]

(219) 0x421688 ADD	X25, X16, X25,LSL #3

(219) 0x42168c LD1	{V20.D[1]}, [X8]

(219) 0x421690 MADD	X8, X0, X27, XZR

(219) 0x421694 ADD	X9, X25, X19

(219) 0x421698 ADD	X8, X18, X8,LSL #3

(219) 0x42169c LDR	D21, [X8, X22,SXTW #3]

(219) 0x4216a0 MADD	X8, X17, X27, XZR

(219) 0x4216a4 ADD	X8, X16, X8,LSL #3

(219) 0x4216a8 LDR	D22, [X8, X22,SXTW #3]

(219) 0x4216ac LDR	D24, [X8, X30,SXTW #3]

(219) 0x4216b0 FADD	V20.2D, V20.2D, V20.2D

(219) 0x4216b4 LD1	{V21.D[1]}, [X23]

(219) 0x4216b8 MADD	X23, X2, X21, XZR

(219) 0x4216bc ADD	X23, X1, X23,LSL #3

(219) 0x4216c0 LD1	{V22.D[1]}, [X9]

(219) 0x4216c4 MADD	X9, X2, X27, XZR

(219) 0x4216c8 ADD	X10, X23, X19

(219) 0x4216cc ADD	X9, X1, X9,LSL #3

(219) 0x4216d0 LDR	D23, [X9, X22,SXTW #3]

(219) 0x4216d4 LDR	D28, [X9, X30,SXTW #3]

(219) 0x4216d8 MADD	X9, X12, X21, XZR

(219) 0x4216dc ADD	X9, X13, X9,LSL #3

(219) 0x4216e0 FDIV	V20.2D, V20.2D, V21.2D

(219) 0x4216e4 ADD	X9, X9, X19

(219) 0x4216e8 LD1	{V23.D[1]}, [X10]

(219) 0x4216ec ADD	W10, W26, #1

(219) 0x4216f0 SBFM	X26, X10, #0, #31

(219) 0x4216f4 MADD	X8, X17, X26, XZR

(219) 0x4216f8 ADD	X8, X16, X8,LSL #3

(219) 0x4216fc LDR	D26, [X8, X22,SXTW #3]

(219) 0x421700 LDR	D27, [X8, X30,SXTW #3]

(219) 0x421704 ADD	W8, W24, #3

(219) 0x421708 SBFM	X24, X8, #61, #31

(219) 0x42170c ADD	X8, X25, X24

(219) 0x421710 ADD	X10, X23, X24

(219) 0x421714 LD1	{V24.D[1]}, [X8]

(219) 0x421718 MADD	X8, X12, X27, XZR

(219) 0x42171c LD1	{V28.D[1]}, [X10]

(219) 0x421720 ADD	X8, X13, X8,LSL #3

(219) 0x421724 FMLA	V20.2D, V19.2D, V19.2D

(219) 0x421728 FSQRT	V20.2D, V20.2D

(219) 0x42172c LDR	D25, [X8, X22,SXTW #3]

(219) 0x421730 MADD	X8, X4, X27, XZR

(219) 0x421734 ADD	X8, X3, X8,LSL #3

(219) 0x421738 LDR	D29, [X8, X22,SXTW #3]

(219) 0x42173c LDR	D30, [X8, X30,SXTW #3]

(219) 0x421740 LD1	{V25.D[1]}, [X9]

(219) 0x421744 MADD	X9, X4, X21, XZR

(219) 0x421748 ADD	X9, X3, X9,LSL #3

(219) 0x42174c ADD	X10, X9, X19

(219) 0x421750 ADD	X9, X9, X24

(219) 0x421754 LD1	{V29.D[1]}, [X10]

(219) 0x421758 ADD	W10, W6, #1

(219) 0x42175c LD1	{V30.D[1]}, [X9]

(219) 0x421760 SBFM	X10, X10, #0, #31

(219) 0x421764 MADD	X8, X17, X10, XZR

(219) 0x421768 ADD	X8, X16, X8,LSL #3

(219) 0x42176c FMUL	V19.2D, V25.2D, V6.2D

(219) 0x421770 ADD	X9, X8, X19

(219) 0x421774 ADD	X8, X8, X24

(219) 0x421778 LD1	{V26.D[1]}, [X9]

(219) 0x42177c MADD	X9, X7, X27, XZR

(219) 0x421780 LD1	{V27.D[1]}, [X8]

(219) 0x421784 MADD	X8, X7, X26, XZR

(219) 0x421788 ORR	W27, WZR, W11

(219) 0x42178c ADD	X9, X5, X9,LSL #3

(219) 0x421790 ADD	X8, X5, X8,LSL #3

(219) 0x421794 FMAXNM	V20.2D, V20.2D, V6.2D

(219) 0x421798 LDR	D31, [X9, X22,SXTW #3]

(219) 0x42179c MADD	X9, X7, X21, XZR

(219) 0x4217a0 LDR	D10, [X8, X22,SXTW #3]

(219) 0x4217a4 MADD	X8, X4, X10, XZR

(219) 0x4217a8 FDIV	V17.2D, V17.2D, V20.2D

(219) 0x4217ac ADD	X9, X5, X9,LSL #3

(219) 0x4217b0 ADD	X8, X3, X8,LSL #3

(219) 0x4217b4 ADD	X9, X9, X19

(219) 0x4217b8 FADD	V18.2D, V26.2D, V22.2D

(219) 0x4217bc FADD	V21.2D, V27.2D, V24.2D

(219) 0x4217c0 FMUL	V18.2D, V23.2D, V18.2D

(219) 0x4217c4 LD1	{V31.D[1]}, [X9]

(219) 0x4217c8 MADD	X9, X4, X26, XZR

(219) 0x4217cc FMUL	V21.2D, V21.2D, V28.2D

(219) 0x4217d0 ADD	X9, X3, X9,LSL #3

(219) 0x4217d4 LDR	D8, [X9, X30,SXTW #3]

(219) 0x4217d8 LDR	D9, [X9, X22,SXTW #3]

(219) 0x4217dc ADD	X9, X8, X19

(219) 0x4217e0 ADD	X8, X8, X24

(219) 0x4217e4 FABS	V22.2D, V18.2D

(219) 0x4217e8 FABS	V23.2D, V21.2D

(219) 0x4217ec FMAXNM	V22.2D, V22.2D, V23.2D

(219) 0x4217f0 FMUL	V23.2D, V25.2D, V1.D[0]

(219) 0x4217f4 FMAXNM	V22.2D, V22.2D, V19.2D

(219) 0x4217f8 FDIV	V22.2D, V23.2D, V22.2D

(219) 0x4217fc FADD	V23.2D, V30.2D, V29.2D

(219) 0x421800 LD1	{V8.D[1]}, [X8]

(219) 0x421804 MADD	X8, X7, X10, XZR

(219) 0x421808 LD1	{V9.D[1]}, [X9]

(219) 0x42180c FMUL	V23.2D, V31.2D, V23.2D

(219) 0x421810 ADD	X8, X5, X8,LSL #3

(219) 0x421814 ADD	X8, X8, X19

(219) 0x421818 LD1	{V10.D[1]}, [X8]

(219) 0x42181c FADD	V18.2D, V18.2D, V23.2D

(219) 0x421820 FABS	V23.2D, V23.2D

(219) 0x421824 LDR	X8, [SP, #80]

(219) 0x421828 FSUB	V18.2D, V21.2D, V18.2D

(219) 0x42182c FMUL	V21.2D, V25.2D, V2.D[0]

(219) 0x421830 FADD	V24.2D, V8.2D, V9.2D

(219) 0x421834 FMUL	V24.2D, V24.2D, V10.2D

(219) 0x421838 FABS	V20.2D, V24.2D

(219) 0x42183c FADD	V18.2D, V18.2D, V24.2D

(219) 0x421840 FMAXNM	V20.2D, V23.2D, V20.2D

(219) 0x421844 FMAXNM	V19.2D, V20.2D, V19.2D

(219) 0x421848 FADD	V20.2D, V25.2D, V25.2D

(219) 0x42184c FDIV	V18.2D, V18.2D, V20.2D

(219) 0x421850 FDIV	V19.2D, V21.2D, V19.2D

(219) 0x421854 FCMGT	V20.2D, V7.2D, V18.2D

(219) 0x421858 FDIV	V18.2D, V4.2D, V18.2D

(219) 0x42185c BIF	V18.16B, V16.16B, V20.16B

(219) 0x421860 FMINNM	V18.2D, V18.2D, V16.2D

(219) 0x421864 FMINNM	V18.2D, V19.2D, V18.2D

(219) 0x421868 FMINNM	V18.2D, V22.2D, V18.2D

(219) 0x42186c FMINNM	V17.2D, V17.2D, V18.2D

(219) 0x421870 FMINNM	V5.2D, V17.2D, V5.2D

(219) 0x421874 CMP	X8, X28

(219) 0x421878 B.NE	4215c4

0x42187c LDP	X8, X25, [SP, #16]

0x421880 LDP	X9, X28, [SP, #80]

0x421884 LDP	X26, X24, [SP, #32]

0x421888 FMINNMP	D4, V5.2D

0x42188c LDR	X30, [SP, #72]

0x421890 LDR	X11, [SP, #96]

0x421894 STUR	D4, [X29, #440]

0x421898 CMP	X8, X9

0x42189c B.EQ	421a40

0x4218a0 ADRP	X8,

0x4218a4 SUB	W6, WZR, W28

0x4218a8 LDR	D5, [X8, #2032]

0x4218ac ADRP	X8,

0x4218b0 LDR	D6, [X8, #2152]

0x4218b4 ADRP	X8,

0x4218b8 LDR	D7, [X8, #2160]

0x4218bc HINT	#0

(220) 0x4218c0 SDIV	X8, X20, X28

(220) 0x4218c4 LDP	X21, X22, [X29, #928]

(220) 0x4218c8 ADD	W10, W26, W20

(220) 0x4218cc ADD	X20, X20, #1

(220) 0x4218d0 ADD	W9, W27, W8

(220) 0x4218d4 MADD	W8, W6, W8, W10

(220) 0x4218d8 SBFM	X10, X9, #0, #31

(220) 0x4218dc LDR	D17, [X11, X9,SXTW #3]

(220) 0x4218e0 ADD	W9, W9, #1

(220) 0x4218e4 MADD	X21, X21, X10, XZR

(220) 0x4218e8 ADD	W19, W8, #1

(220) 0x4218ec SBFM	X9, X9, #0, #31

(220) 0x4218f0 MADD	X23, X2, X10, XZR

(220) 0x4218f4 ADD	W8, W8, #2

(220) 0x4218f8 LDR	D16, [X30, X19,SXTW #3]

(220) 0x4218fc ADD	X21, X22, X21,LSL #3

(220) 0x421900 MADD	X22, X17, X9, XZR

(220) 0x421904 ADD	X23, X1, X23,LSL #3

(220) 0x421908 LDR	D18, [X21, X19,SXTW #3]

(220) 0x42190c MADD	X21, X15, X10, XZR

(220) 0x421910 ADD	X22, X16, X22,LSL #3

(220) 0x421914 ADD	X21, X14, X21,LSL #3

(220) 0x421918 LDR	D21, [X22, X19,SXTW #3]

(220) 0x42191c LDR	D19, [X21, X19,SXTW #3]

(220) 0x421920 MADD	X21, X0, X10, XZR

(220) 0x421924 FMINNM	D16, D16, D17

(220) 0x421928 ADD	X21, X18, X21,LSL #3

(220) 0x42192c LDR	D20, [X21, X19,SXTW #3]

(220) 0x421930 MADD	X21, X17, X10, XZR

(220) 0x421934 FMUL	D16, D0, D16

(220) 0x421938 ADD	X21, X16, X21,LSL #3

(220) 0x42193c FADD	D19, D19, D19

(220) 0x421940 LDR	D17, [X21, X19,SXTW #3]

(220) 0x421944 FDIV	D19, D19, D20

(220) 0x421948 LDR	D20, [X23, X19,SXTW #3]

(220) 0x42194c FADD	D17, D21, D17

(220) 0x421950 LDR	D21, [X22, X8,SXTW #3]

(220) 0x421954 FMUL	D17, D20, D17

(220) 0x421958 LDR	D20, [X21, X8,SXTW #3]

(220) 0x42195c MADD	X21, X12, X10, XZR

(220) 0x421960 ADD	X21, X13, X21,LSL #3

(220) 0x421964 FABS	D23, D17

(220) 0x421968 FADD	D20, D21, D20

(220) 0x42196c LDR	D21, [X23, X8,SXTW #3]

(220) 0x421970 FMADD	D18, D18, D18, D19

(220) 0x421974 FMUL	D20, D20, D21

(220) 0x421978 LDR	D21, [X21, X19,SXTW #3]

(220) 0x42197c MADD	X21, X4, X10, XZR

(220) 0x421980 MADD	X10, X7, X10, XZR

(220) 0x421984 FSQRT	D18, D18

(220) 0x421988 ADD	X21, X3, X21,LSL #3

(220) 0x42198c ADD	X10, X5, X10,LSL #3

(220) 0x421990 FABS	D24, D20

(220) 0x421994 FMAXNM	D23, D23, D24

(220) 0x421998 LDR	D24, [X21, X8,SXTW #3]

(220) 0x42199c FMUL	D25, D21, D5

(220) 0x4219a0 FMUL	D22, D21, D1

(220) 0x4219a4 FMAXNM	D23, D23, D25

(220) 0x4219a8 FDIV	D22, D22, D23

(220) 0x4219ac LDR	D23, [X21, X19,SXTW #3]

(220) 0x4219b0 FADD	D23, D24, D23

(220) 0x4219b4 LDR	D24, [X10, X19,SXTW #3]

(220) 0x4219b8 MADD	X10, X4, X9, XZR

(220) 0x4219bc FMAXNM	D18, D18, D5

(220) 0x4219c0 ADD	X10, X3, X10,LSL #3

(220) 0x4219c4 FDIV	D16, D16, D18

(220) 0x4219c8 LDR	D26, [X10, X8,SXTW #3]

(220) 0x4219cc MADD	X8, X7, X9, XZR

(220) 0x4219d0 ADD	X8, X5, X8,LSL #3

(220) 0x4219d4 FMUL	D23, D24, D23

(220) 0x4219d8 LDR	D24, [X10, X19,SXTW #3]

(220) 0x4219dc FADD	D17, D17, D23

(220) 0x4219e0 FABS	D23, D23

(220) 0x4219e4 FSUB	D17, D20, S17

(220) 0x4219e8 FMUL	D20, D21, D2

(220) 0x4219ec FADD	D19, D26, D24

(220) 0x4219f0 LDR	D24, [X8, X19,SXTW #3]

(220) 0x4219f4 FMUL	D19, D19, D24

(220) 0x4219f8 FADD	D17, D17, D19

(220) 0x4219fc FABS	D19, D19

(220) 0x421a00 FMAXNM	D19, D23, D19

(220) 0x421a04 FMAXNM	D18, D19, D25

(220) 0x421a08 FADD	D19, D21, D21

(220) 0x421a0c FDIV	D17, D17, D19

(220) 0x421a10 FDIV	D18, D20, D18

(220) 0x421a14 FCMP	D17, D7

(220) 0x421a18 FDIV	D17, D3, D17

(220) 0x421a1c FCSEL	D17, D6, D17, #10

(220) 0x421a20 FMINNM	D17, D17, D6

(220) 0x421a24 FMINNM	D17, D18, D17

(220) 0x421a28 FMINNM	D17, D22, D17

(220) 0x421a2c FMINNM	D16, D16, D17

(220) 0x421a30 FMINNM	D4, D16, D4

(220) 0x421a34 STUR	D4, [X29, #440]

(220) 0x421a38 CMP	X25, X20

(220) 0x421a3c B.NE	4218c0

0x421a40 LDR	W19, [SP, #52]

0x421a44 ADRP	X0,

0x421a48 ADD	X0, X0, #960

0x421a4c ORR	W1, WZR, W19

0x421a50 BL	403400

0x421a54 SUB	X8, X29, #72

0x421a58 ADRP	X6,

0x421a5c ADRP	X0,

0x421a60 ADD	X0, X0, #984

0x421a64 ADRP	X5, 421a64

0x421a68 ADD	X5, X5, #912

0x421a6c ORR	W1, WZR, W19

0x421a70 STUR	X8, [X29, #432]

0x421a74 SUB	X4, X29, #80

0x421a78 MOVZ	W2, #1

0x421a7c MOVZ	W3, #8

0x421a80 LDR	X6, [X6, #3944]

0x421a84 BL	403370

0x421a88 CMP	W0, #2

0x421a8c B.EQ	421ac4

0x421a90 CMP	W0, #1

0x421a94 B.NE	421afc

0x421a98 LDR	D0, [X24]

0x421a9c LDUR	D1, [X29, #440]

0x421aa0 ADRP	X2,

0x421aa4 ADRP	X0,

0x421aa8 ADD	X0, X0, #984

0x421aac ORR	W1, WZR, W19

0x421ab0 FMINNM	D0, D0, D1

0x421ab4 STR	D0, [X24]

0x421ab8 LDR	X2, [X2, #3944]

0x421abc BL	4031c0

0x421ac0 B	421afc

0x421ac4 LDR	X8, [X24]

0x421ac8 LDUR	D0, [X29, #440]

0x421acc ORR	X9, XZR, X8

0x421ad0 HINT	#0

0x421ad4 HINT	#0

0x421ad8 HINT	#0

0x421adc HINT	#0

(218) 0x421ae0 FMOV	D1, X8

(218) 0x421ae4 FMINNM	D1, D0, D1

(218) 0x421ae8 FMOV	X10, D1

(218) 0x421aec CAS	X9, X10, [X24]

(218) 0x421af0 CMP	X9, X8

(218) 0x421af4 ORR	X8, XZR, X9

(218) 0x421af8 B.NE	421ae0

0x421afc LDP	D9, D8, [SP, #192]

0x421b00 LDR	D10, [SP, #176]

0x421b04 LDP	X20, X19, [SP, #288]

0x421b08 LDP	X22, X21, [SP, #272]

0x421b0c LDP	X24, X23, [SP, #256]

0x421b10 LDP	X26, X25, [SP, #240]

0x421b14 LDP	X28, X27, [SP, #224]

0x421b18 LDP	X29, X30, [SP, #208]

0x421b1c ADD	SP, SP, #304

0x421b20 RET

0x421b24 HINT	#0

0x421b28 HINT	#0

0x421b2c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.83 to 5.33 cycles (5.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 29.83 to 23.33 cycles (1.28x speedup).

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

4% of VPU loads are used in vector version.
3% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
5% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.83 to 2.00 cycles (14.92x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 608 bytes. The binary function is storing 300 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	203
loop length	812
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

24.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.50	6.50	15.08	15.08	15.00	15.00	14.92	14.92	2.75	2.75	2.75	2.75	29.83	29.50	29.67	11.50	11.50
cycles	6.50	6.50	15.08	15.08	15.00	15.00	14.92	14.92	2.75	2.75	2.75	2.75	29.83	29.50	29.67	11.50	11.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.38
Overall L1	29.83

Vectorization ratios

INT

all	4%
load	4%
store	3%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	4%
store	3%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.83 cycles. At this rate:

21% of peak load performance is reached (20.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (10.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4213b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D10, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D9, D8, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W26, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W27, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W9, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 421afc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W28, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46d41c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #936	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR XZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR WZR, [X29, #452]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X5, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X19, W28, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVN X9, #32784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X19, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR W1, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X6, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X6, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 421a40 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X7, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X1, X2, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X11, X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X25, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVN X6, #32784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X16, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X22, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X17, X0, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X30, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D3, [X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D0, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FADD D1, D1, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X11, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X8, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X14, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADD D2, D2, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FNEG D3, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB X11, X25, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 42153c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X20, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
FMOV D4, X6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X15, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4218a0 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V5.2D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ X6, #35260	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X11, X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X0, X11, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V4.2D, V3.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR X15, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X26, X24, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X28, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X30, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #38872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X0, X15, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W15, WZR, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #53938	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W15, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X15, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #15516	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V6.2D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ X6, #35260	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X20, X11, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W11, W26, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #38872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVK X6, #53938	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #48284	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V7.2D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ X6, #61264	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #55010	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #6884	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #17483	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V16.2D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDP X8, X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X24, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
FMINNMP D4, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
LDR X30, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR D4, [X29, #440]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 421a40 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <44b8a0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W6, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D5, [X8, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X8, <44b8ac>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X8, #2152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X8, <44b8b4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X8, #2160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
HINT #0																					N/A
LDR W19, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <46da44>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #960	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X6, <46fa58>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <46da5c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #984	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X5, 421a64 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x6b4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #912	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X6, [X6, #3944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 403370 <@plt_start@+0x500>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 421ac4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 421afc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDUR D1, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X2, <46faa0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <46daa4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #984	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMINNM D0, D0, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X2, [X2, #3944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4031c0 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 421afc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ORR X9, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP D9, D8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.83 to 5.33 cycles (5.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

4% of VPU loads are used in vector version.
3% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
5% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.83 to 2.00 cycles (14.92x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 608 bytes. The binary function is storing 300 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	203
loop length	812
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

24.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.50	6.50	15.08	15.08	15.00	15.00	14.92	14.92	2.75	2.75	2.75	2.75	29.83	29.50	29.67	11.50	11.50
cycles	6.50	6.50	15.08	15.08	15.00	15.00	14.92	14.92	2.75	2.75	2.75	2.75	29.83	29.50	29.67	11.50	11.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.38
Overall L1	29.83

Vectorization ratios

INT

all	4%
load	4%
store	3%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	4%
store	3%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.83 cycles. At this rate:

21% of peak load performance is reached (20.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (10.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4213b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D10, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D9, D8, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W26, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W27, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W9, W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W10, W9, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 421afc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W28, W10, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46d41c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #936	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR XZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR WZR, [X29, #452]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X5, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X6, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X19, W28, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVN X9, #32784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X19, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR W1, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X6, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X6, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 421a40 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X7, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X1, X2, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X11, X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X25, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVN X6, #32784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X16, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X22, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X17, X0, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X30, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D3, [X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D0, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FADD D1, D1, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X11, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X8, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X14, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADD D2, D2, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FNEG D3, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB X11, X25, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 42153c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X20, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
FMOV D4, X6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X15, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4218a0 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V5.2D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ X6, #35260	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X11, X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X0, X11, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V4.2D, V3.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR X15, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X26, X24, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X28, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X30, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #38872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X0, X15, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W15, WZR, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #53938	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W15, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X15, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #15516	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V6.2D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ X6, #35260	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X20, X11, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W11, W26, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #38872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVK X6, #53938	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #48284	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V7.2D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ X6, #61264	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #55010	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #6884	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X6, #17483	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V16.2D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDP X8, X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X24, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
FMINNMP D4, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
LDR X30, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR D4, [X29, #440]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 421a40 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <44b8a0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W6, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D5, [X8, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X8, <44b8ac>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X8, #2152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X8, <44b8b4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X8, #2160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
HINT #0																					N/A
LDR W19, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <46da44>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #960	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X6, <46fa58>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <46da5c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #984	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X5, 421a64 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x6b4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #912	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X6, [X6, #3944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 403370 <@plt_start@+0x500>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 421ac4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 421afc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDUR D1, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X2, <46faa0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <46daa4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #984	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMINNM D0, D0, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X2, [X2, #3944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4031c0 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 421afc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ORR X9, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP D9, D8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	3.76	3.03
○Loop 219 - calc_dt.cpp:50-75 - exec	3.76	3.01
○Loop 220 - calc_dt.cpp:50-75 - exec	0.00	0.00
○Loop 218 - calc_dt.cpp:49-49 - exec	0.00	0.00

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

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Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code